About the Execution of LoLA for NoC3x3-PT-6A
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 1380395.00 | 0.00 | 0.00 | [undef] | Cannot compute |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353800635.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is NoC3x3-PT-6A, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353800635
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 784K
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K May 19 07:12 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 19 16:11 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 173K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Apr 12 07:39 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 51K Apr 12 07:39 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.4K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 19 15:29 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 297K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-00
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-01
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-02
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-03
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-04
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-05
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-06
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-07
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-08
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-09
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-10
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-11
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-12
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-13
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-14
FORMULA_NAME NoC3x3-PT-6A-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717093947828
BK_STOP 1717095328223
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 17 (type CNST) for 16 NoC3x3-PT-6A-LTLCardinality-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 17 (type CNST) for NoC3x3-PT-6A-LTLCardinality-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 NoC3x3-PT-6A-LTLCardinality-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for NoC3x3-PT-6A-LTLCardinality-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 41 (type CNST) for 40 NoC3x3-PT-6A-LTLCardinality-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 41 (type CNST) for NoC3x3-PT-6A-LTLCardinality-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 23 (type CNST) for 22 NoC3x3-PT-6A-LTLCardinality-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 23 (type CNST) for NoC3x3-PT-6A-LTLCardinality-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 NoC3x3-PT-6A-LTLCardinality-14
[[35mlola[0m][I] time limit : 273 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 NoC3x3-PT-6A-LTLCardinality-15
[[35mlola[0m][I] time limit : 296 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 32
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 NoC3x3-PT-6A-LTLCardinality-11
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 4/323 7/2000 NoC3x3-PT-6A-LTLCardinality-11 964128 m, 192825 m/sec, 2058240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 9/323 13/2000 NoC3x3-PT-6A-LTLCardinality-11 1925682 m, 192310 m/sec, 4422760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 14/323 19/2000 NoC3x3-PT-6A-LTLCardinality-11 2853262 m, 185516 m/sec, 6788312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 19/323 25/2000 NoC3x3-PT-6A-LTLCardinality-11 3681311 m, 165609 m/sec, 9179361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 24/323 30/2000 NoC3x3-PT-6A-LTLCardinality-11 4489096 m, 161557 m/sec, 11435230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 29/323 36/2000 NoC3x3-PT-6A-LTLCardinality-11 5397713 m, 181723 m/sec, 13685841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 34/323 42/2000 NoC3x3-PT-6A-LTLCardinality-11 6271871 m, 174831 m/sec, 15950416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 39/323 47/2000 NoC3x3-PT-6A-LTLCardinality-11 7110137 m, 167653 m/sec, 18202234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 44/323 52/2000 NoC3x3-PT-6A-LTLCardinality-11 7807443 m, 139461 m/sec, 20356357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 49/323 57/2000 NoC3x3-PT-6A-LTLCardinality-11 8550643 m, 148640 m/sec, 22720930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 54/323 62/2000 NoC3x3-PT-6A-LTLCardinality-11 9332346 m, 156340 m/sec, 25112870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 59/323 66/2000 NoC3x3-PT-6A-LTLCardinality-11 10059332 m, 145397 m/sec, 27506743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 64/323 71/2000 NoC3x3-PT-6A-LTLCardinality-11 10791694 m, 146472 m/sec, 29884724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 69/323 75/2000 NoC3x3-PT-6A-LTLCardinality-11 11438408 m, 129342 m/sec, 32222463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 74/323 80/2000 NoC3x3-PT-6A-LTLCardinality-11 12102123 m, 132743 m/sec, 34458419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 79/323 85/2000 NoC3x3-PT-6A-LTLCardinality-11 12903252 m, 160225 m/sec, 36675679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 84/323 90/2000 NoC3x3-PT-6A-LTLCardinality-11 13690596 m, 157468 m/sec, 38920763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 89/323 95/2000 NoC3x3-PT-6A-LTLCardinality-11 14458071 m, 153495 m/sec, 41226981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 94/323 101/2000 NoC3x3-PT-6A-LTLCardinality-11 15320437 m, 172473 m/sec, 43549753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 99/323 107/2000 NoC3x3-PT-6A-LTLCardinality-11 16278504 m, 191613 m/sec, 45910470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 104/323 114/2000 NoC3x3-PT-6A-LTLCardinality-11 17212295 m, 186758 m/sec, 48298064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 109/323 119/2000 NoC3x3-PT-6A-LTLCardinality-11 18067755 m, 171092 m/sec, 50702119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 114/323 124/2000 NoC3x3-PT-6A-LTLCardinality-11 18813490 m, 149147 m/sec, 53023580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 119/323 130/2000 NoC3x3-PT-6A-LTLCardinality-11 19694064 m, 176114 m/sec, 55340688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 124/323 136/2000 NoC3x3-PT-6A-LTLCardinality-11 20604031 m, 181993 m/sec, 57650136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 129/323 142/2000 NoC3x3-PT-6A-LTLCardinality-11 21467628 m, 172719 m/sec, 59997044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 134/323 147/2000 NoC3x3-PT-6A-LTLCardinality-11 22246475 m, 155769 m/sec, 62344673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 139/323 152/2000 NoC3x3-PT-6A-LTLCardinality-11 23021120 m, 154929 m/sec, 64634596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 144/323 157/2000 NoC3x3-PT-6A-LTLCardinality-11 23778251 m, 151426 m/sec, 66954046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 149/323 163/2000 NoC3x3-PT-6A-LTLCardinality-11 24616938 m, 167737 m/sec, 69294536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 154/323 168/2000 NoC3x3-PT-6A-LTLCardinality-11 25370209 m, 150654 m/sec, 71666492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 159/323 173/2000 NoC3x3-PT-6A-LTLCardinality-11 26278467 m, 181651 m/sec, 73954774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 164/323 179/2000 NoC3x3-PT-6A-LTLCardinality-11 27199446 m, 184195 m/sec, 76227095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 169/323 185/2000 NoC3x3-PT-6A-LTLCardinality-11 28098844 m, 179879 m/sec, 78495638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 174/323 190/2000 NoC3x3-PT-6A-LTLCardinality-11 28893145 m, 158860 m/sec, 80798440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 179/323 195/2000 NoC3x3-PT-6A-LTLCardinality-11 29604787 m, 142328 m/sec, 82992749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 184/323 200/2000 NoC3x3-PT-6A-LTLCardinality-11 30394766 m, 157995 m/sec, 85091218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 189/323 206/2000 NoC3x3-PT-6A-LTLCardinality-11 31260549 m, 173156 m/sec, 87301167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 194/323 211/2000 NoC3x3-PT-6A-LTLCardinality-11 32111960 m, 170282 m/sec, 89575385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 199/323 216/2000 NoC3x3-PT-6A-LTLCardinality-11 32885993 m, 154806 m/sec, 91802058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 204/323 221/2000 NoC3x3-PT-6A-LTLCardinality-11 33651486 m, 153098 m/sec, 93962787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 209/323 226/2000 NoC3x3-PT-6A-LTLCardinality-11 34436036 m, 156910 m/sec, 96121051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 214/323 232/2000 NoC3x3-PT-6A-LTLCardinality-11 35361849 m, 185162 m/sec, 98422568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 219/323 237/2000 NoC3x3-PT-6A-LTLCardinality-11 36154561 m, 158542 m/sec, 100713551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 224/323 243/2000 NoC3x3-PT-6A-LTLCardinality-11 36965694 m, 162226 m/sec, 103183080 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 229/323 248/2000 NoC3x3-PT-6A-LTLCardinality-11 37741155 m, 155092 m/sec, 105628358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 234/323 253/2000 NoC3x3-PT-6A-LTLCardinality-11 38509017 m, 153572 m/sec, 108094600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 239/323 257/2000 NoC3x3-PT-6A-LTLCardinality-11 39235774 m, 145351 m/sec, 110530873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 244/323 262/2000 NoC3x3-PT-6A-LTLCardinality-11 39897504 m, 132346 m/sec, 112896129 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 249/323 266/2000 NoC3x3-PT-6A-LTLCardinality-11 40516127 m, 123724 m/sec, 115176736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 254/323 270/2000 NoC3x3-PT-6A-LTLCardinality-11 41196250 m, 136024 m/sec, 117419859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 259/323 275/2000 NoC3x3-PT-6A-LTLCardinality-11 41926293 m, 146008 m/sec, 119764645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 264/323 280/2000 NoC3x3-PT-6A-LTLCardinality-11 42655236 m, 145788 m/sec, 122174426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 269/323 284/2000 NoC3x3-PT-6A-LTLCardinality-11 43299211 m, 128795 m/sec, 124522529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 274/323 288/2000 NoC3x3-PT-6A-LTLCardinality-11 43971281 m, 134414 m/sec, 126856649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 279/323 292/2000 NoC3x3-PT-6A-LTLCardinality-11 44618207 m, 129385 m/sec, 129097632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 284/323 297/2000 NoC3x3-PT-6A-LTLCardinality-11 45351231 m, 146604 m/sec, 131453493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 289/323 302/2000 NoC3x3-PT-6A-LTLCardinality-11 46108868 m, 151527 m/sec, 133890187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 294/323 307/2000 NoC3x3-PT-6A-LTLCardinality-11 46804187 m, 139063 m/sec, 136312809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 299/323 313/2000 NoC3x3-PT-6A-LTLCardinality-11 47729967 m, 185156 m/sec, 138694371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 304/323 319/2000 NoC3x3-PT-6A-LTLCardinality-11 48694088 m, 192824 m/sec, 141069625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 319
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 309/323 325/2000 NoC3x3-PT-6A-LTLCardinality-11 49622178 m, 185618 m/sec, 143447499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 314/323 330/2000 NoC3x3-PT-6A-LTLCardinality-11 50429125 m, 161389 m/sec, 145842875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 LTL EXCL 319/323 336/2000 NoC3x3-PT-6A-LTLCardinality-11 51257175 m, 165610 m/sec, 148117898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 38 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 NoC3x3-PT-6A-LTLCardinality-10
[[35mlola[0m][I] time limit : 323 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 NoC3x3-PT-6A-LTLCardinality-11
[[35mlola[0m][I] time limit : 3235 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 32
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 38 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 NoC3x3-PT-6A-LTLCardinality-09
[[35mlola[0m][I] time limit : 358 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 394178
[[35mlola[0m][I] fired transitions : 1075777
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 NoC3x3-PT-6A-LTLCardinality-07
[[35mlola[0m][I] time limit : 403 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 NoC3x3-PT-6A-LTLCardinality-05
[[35mlola[0m][I] time limit : 461 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 3/461 4/2000 NoC3x3-PT-6A-LTLCardinality-05 524491 m, 104898 m/sec, 1521434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 8/461 7/2000 NoC3x3-PT-6A-LTLCardinality-05 999827 m, 95067 m/sec, 4410270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 13/461 10/2000 NoC3x3-PT-6A-LTLCardinality-05 1477061 m, 95446 m/sec, 7284787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 18/461 13/2000 NoC3x3-PT-6A-LTLCardinality-05 1940322 m, 92652 m/sec, 10144247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 23/461 17/2000 NoC3x3-PT-6A-LTLCardinality-05 2411956 m, 94326 m/sec, 13020531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 28/461 20/2000 NoC3x3-PT-6A-LTLCardinality-05 2878963 m, 93401 m/sec, 15880694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 33/461 23/2000 NoC3x3-PT-6A-LTLCardinality-05 3334637 m, 91134 m/sec, 18718910 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 38/461 25/2000 NoC3x3-PT-6A-LTLCardinality-05 3740098 m, 81092 m/sec, 21517792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 43/461 28/2000 NoC3x3-PT-6A-LTLCardinality-05 4135635 m, 79107 m/sec, 24289268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 48/461 31/2000 NoC3x3-PT-6A-LTLCardinality-05 4557351 m, 84343 m/sec, 27064776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 53/461 34/2000 NoC3x3-PT-6A-LTLCardinality-05 5044779 m, 97485 m/sec, 29768876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 58/461 36/2000 NoC3x3-PT-6A-LTLCardinality-05 5450935 m, 81231 m/sec, 32516435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 63/461 39/2000 NoC3x3-PT-6A-LTLCardinality-05 5905952 m, 91003 m/sec, 35235912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 68/461 42/2000 NoC3x3-PT-6A-LTLCardinality-05 6386863 m, 96182 m/sec, 37936799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 73/461 45/2000 NoC3x3-PT-6A-LTLCardinality-05 6813211 m, 85269 m/sec, 40638815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 78/461 48/2000 NoC3x3-PT-6A-LTLCardinality-05 7258444 m, 89046 m/sec, 43364319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 83/461 51/2000 NoC3x3-PT-6A-LTLCardinality-05 7700056 m, 88322 m/sec, 46068931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 88/461 54/2000 NoC3x3-PT-6A-LTLCardinality-05 8151533 m, 90295 m/sec, 48687423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 93/461 55/2000 NoC3x3-PT-6A-LTLCardinality-05 8299902 m, 29673 m/sec, 51364402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 98/461 58/2000 NoC3x3-PT-6A-LTLCardinality-05 8721281 m, 84275 m/sec, 54106599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 103/461 60/2000 NoC3x3-PT-6A-LTLCardinality-05 9102548 m, 76253 m/sec, 56847839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 108/461 63/2000 NoC3x3-PT-6A-LTLCardinality-05 9524394 m, 84369 m/sec, 59531928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 113/461 66/2000 NoC3x3-PT-6A-LTLCardinality-05 9967256 m, 88572 m/sec, 62143035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 118/461 67/2000 NoC3x3-PT-6A-LTLCardinality-05 10100051 m, 26559 m/sec, 64788984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 123/461 70/2000 NoC3x3-PT-6A-LTLCardinality-05 10539071 m, 87804 m/sec, 67537925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 128/461 72/2000 NoC3x3-PT-6A-LTLCardinality-05 10927771 m, 77740 m/sec, 70216392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 133/461 74/2000 NoC3x3-PT-6A-LTLCardinality-05 11266730 m, 67791 m/sec, 72947882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 138/461 77/2000 NoC3x3-PT-6A-LTLCardinality-05 11615269 m, 69707 m/sec, 75627309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 143/461 79/2000 NoC3x3-PT-6A-LTLCardinality-05 11985249 m, 73996 m/sec, 78277133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 148/461 81/2000 NoC3x3-PT-6A-LTLCardinality-05 12374780 m, 77906 m/sec, 80948673 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 153/461 84/2000 NoC3x3-PT-6A-LTLCardinality-05 12700204 m, 65084 m/sec, 83717633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 158/461 86/2000 NoC3x3-PT-6A-LTLCardinality-05 13072102 m, 74379 m/sec, 86444560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 163/461 89/2000 NoC3x3-PT-6A-LTLCardinality-05 13469043 m, 79388 m/sec, 89115074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 168/461 91/2000 NoC3x3-PT-6A-LTLCardinality-05 13873886 m, 80968 m/sec, 91761584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 173/461 94/2000 NoC3x3-PT-6A-LTLCardinality-05 14304083 m, 86039 m/sec, 94356706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 178/461 97/2000 NoC3x3-PT-6A-LTLCardinality-05 14712664 m, 81716 m/sec, 96922114 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 183/461 100/2000 NoC3x3-PT-6A-LTLCardinality-05 15149190 m, 87305 m/sec, 99413477 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 188/461 102/2000 NoC3x3-PT-6A-LTLCardinality-05 15599168 m, 89995 m/sec, 101730680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 193/461 105/2000 NoC3x3-PT-6A-LTLCardinality-05 16037114 m, 87589 m/sec, 104022475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 198/461 108/2000 NoC3x3-PT-6A-LTLCardinality-05 16436628 m, 79902 m/sec, 106390506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 203/461 110/2000 NoC3x3-PT-6A-LTLCardinality-05 16831814 m, 79037 m/sec, 108753881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 208/461 113/2000 NoC3x3-PT-6A-LTLCardinality-05 17220184 m, 77674 m/sec, 111215751 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 213/461 115/2000 NoC3x3-PT-6A-LTLCardinality-05 17542226 m, 64408 m/sec, 113843284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 218/461 117/2000 NoC3x3-PT-6A-LTLCardinality-05 17855384 m, 62631 m/sec, 116549555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 223/461 119/2000 NoC3x3-PT-6A-LTLCardinality-05 18171949 m, 63313 m/sec, 119295567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 228/461 121/2000 NoC3x3-PT-6A-LTLCardinality-05 18398770 m, 45364 m/sec, 121903396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 233/461 121/2000 NoC3x3-PT-6A-LTLCardinality-05 18408887 m, 2023 m/sec, 124216840 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 238/461 121/2000 NoC3x3-PT-6A-LTLCardinality-05 18412750 m, 772 m/sec, 126368788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 243/461 121/2000 NoC3x3-PT-6A-LTLCardinality-05 18413933 m, 236 m/sec, 128548201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 248/461 121/2000 NoC3x3-PT-6A-LTLCardinality-05 18414259 m, 65 m/sec, 130841829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 253/461 123/2000 NoC3x3-PT-6A-LTLCardinality-05 18706630 m, 58474 m/sec, 133586101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 258/461 126/2000 NoC3x3-PT-6A-LTLCardinality-05 19152607 m, 89195 m/sec, 136446181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 263/461 129/2000 NoC3x3-PT-6A-LTLCardinality-05 19618865 m, 93251 m/sec, 139256029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 268/461 131/2000 NoC3x3-PT-6A-LTLCardinality-05 20001315 m, 76490 m/sec, 142096437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 273/461 134/2000 NoC3x3-PT-6A-LTLCardinality-05 20411626 m, 82062 m/sec, 144908676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 278/461 136/2000 NoC3x3-PT-6A-LTLCardinality-05 20821055 m, 81885 m/sec, 147687099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 283/461 139/2000 NoC3x3-PT-6A-LTLCardinality-05 21222789 m, 80346 m/sec, 150447945 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 288/461 141/2000 NoC3x3-PT-6A-LTLCardinality-05 21559559 m, 67354 m/sec, 153227638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 293/461 144/2000 NoC3x3-PT-6A-LTLCardinality-05 21905785 m, 69245 m/sec, 155987625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 298/461 146/2000 NoC3x3-PT-6A-LTLCardinality-05 22293125 m, 77468 m/sec, 158799479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 303/461 149/2000 NoC3x3-PT-6A-LTLCardinality-05 22687374 m, 78849 m/sec, 161533633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 308/461 151/2000 NoC3x3-PT-6A-LTLCardinality-05 23017516 m, 66028 m/sec, 164312211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 313/461 153/2000 NoC3x3-PT-6A-LTLCardinality-05 23347608 m, 66018 m/sec, 167077939 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 318/461 156/2000 NoC3x3-PT-6A-LTLCardinality-05 23794392 m, 89356 m/sec, 169911413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 323/461 158/2000 NoC3x3-PT-6A-LTLCardinality-05 24174738 m, 76069 m/sec, 172727212 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 328/461 161/2000 NoC3x3-PT-6A-LTLCardinality-05 24608444 m, 86741 m/sec, 175537816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 333/461 164/2000 NoC3x3-PT-6A-LTLCardinality-05 25074581 m, 93227 m/sec, 178366599 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 338/461 167/2000 NoC3x3-PT-6A-LTLCardinality-05 25530391 m, 91162 m/sec, 181168401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 343/461 170/2000 NoC3x3-PT-6A-LTLCardinality-05 25924834 m, 78888 m/sec, 183931360 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 348/461 172/2000 NoC3x3-PT-6A-LTLCardinality-05 26282105 m, 71454 m/sec, 186696492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 353/461 174/2000 NoC3x3-PT-6A-LTLCardinality-05 26618305 m, 67240 m/sec, 189413692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 358/461 177/2000 NoC3x3-PT-6A-LTLCardinality-05 27010060 m, 78351 m/sec, 192177988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 363/461 179/2000 NoC3x3-PT-6A-LTLCardinality-05 27381276 m, 74243 m/sec, 194922503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 368/461 182/2000 NoC3x3-PT-6A-LTLCardinality-05 27709300 m, 65604 m/sec, 197646462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 373/461 184/2000 NoC3x3-PT-6A-LTLCardinality-05 28093664 m, 76872 m/sec, 200432054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 378/461 187/2000 NoC3x3-PT-6A-LTLCardinality-05 28515267 m, 84320 m/sec, 203238548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 383/461 189/2000 NoC3x3-PT-6A-LTLCardinality-05 28919110 m, 80768 m/sec, 205974007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 388/461 192/2000 NoC3x3-PT-6A-LTLCardinality-05 29319892 m, 80156 m/sec, 208702516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 393/461 195/2000 NoC3x3-PT-6A-LTLCardinality-05 29732915 m, 82604 m/sec, 211407758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 398/461 197/2000 NoC3x3-PT-6A-LTLCardinality-05 30108751 m, 75167 m/sec, 214142570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 403/461 199/2000 NoC3x3-PT-6A-LTLCardinality-05 30444623 m, 67174 m/sec, 216850170 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 408/461 201/2000 NoC3x3-PT-6A-LTLCardinality-05 30772300 m, 65535 m/sec, 219507388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 413/461 204/2000 NoC3x3-PT-6A-LTLCardinality-05 31154476 m, 76435 m/sec, 222231949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 418/461 206/2000 NoC3x3-PT-6A-LTLCardinality-05 31551292 m, 79363 m/sec, 224967982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 423/461 209/2000 NoC3x3-PT-6A-LTLCardinality-05 31900997 m, 69941 m/sec, 227702300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 428/461 211/2000 NoC3x3-PT-6A-LTLCardinality-05 32240313 m, 67863 m/sec, 230413638 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 433/461 213/2000 NoC3x3-PT-6A-LTLCardinality-05 32586769 m, 69291 m/sec, 233195884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 438/461 216/2000 NoC3x3-PT-6A-LTLCardinality-05 32963646 m, 75375 m/sec, 235992865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 443/461 218/2000 NoC3x3-PT-6A-LTLCardinality-05 33358633 m, 78997 m/sec, 238720242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 448/461 220/2000 NoC3x3-PT-6A-LTLCardinality-05 33689255 m, 66124 m/sec, 241460482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 453/461 223/2000 NoC3x3-PT-6A-LTLCardinality-05 34058593 m, 73867 m/sec, 244183308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 458/461 225/2000 NoC3x3-PT-6A-LTLCardinality-05 34456380 m, 79557 m/sec, 246938793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 20 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 NoC3x3-PT-6A-LTLCardinality-02
[[35mlola[0m][I] time limit : 460 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 NoC3x3-PT-6A-LTLCardinality-05
[[35mlola[0m][I] time limit : 2765 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 20 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 5/460 6/2000 NoC3x3-PT-6A-LTLCardinality-02 737698 m, 147539 m/sec, 2705619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 10/460 8/2000 NoC3x3-PT-6A-LTLCardinality-02 1178157 m, 88091 m/sec, 5613251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 15/460 12/2000 NoC3x3-PT-6A-LTLCardinality-02 1685595 m, 101487 m/sec, 8493750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 20/460 15/2000 NoC3x3-PT-6A-LTLCardinality-02 2117852 m, 86451 m/sec, 11351781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 25/460 18/2000 NoC3x3-PT-6A-LTLCardinality-02 2626288 m, 101687 m/sec, 14254749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 30/460 21/2000 NoC3x3-PT-6A-LTLCardinality-02 3065747 m, 87891 m/sec, 17115976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 35/460 24/2000 NoC3x3-PT-6A-LTLCardinality-02 3529430 m, 92736 m/sec, 19940180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 40/460 26/2000 NoC3x3-PT-6A-LTLCardinality-02 3919184 m, 77950 m/sec, 22785187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 45/460 29/2000 NoC3x3-PT-6A-LTLCardinality-02 4345508 m, 85264 m/sec, 25619224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 50/460 32/2000 NoC3x3-PT-6A-LTLCardinality-02 4819553 m, 94809 m/sec, 28372303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 55/460 35/2000 NoC3x3-PT-6A-LTLCardinality-02 5237827 m, 83654 m/sec, 31102317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 60/460 38/2000 NoC3x3-PT-6A-LTLCardinality-02 5680444 m, 88523 m/sec, 33893876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 65/460 41/2000 NoC3x3-PT-6A-LTLCardinality-02 6157988 m, 95508 m/sec, 36559720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 70/460 44/2000 NoC3x3-PT-6A-LTLCardinality-02 6585647 m, 85531 m/sec, 39253019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 75/460 47/2000 NoC3x3-PT-6A-LTLCardinality-02 7061266 m, 95123 m/sec, 41902166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 80/460 49/2000 NoC3x3-PT-6A-LTLCardinality-02 7457756 m, 79298 m/sec, 44619082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 85/460 52/2000 NoC3x3-PT-6A-LTLCardinality-02 7919750 m, 92398 m/sec, 47224378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 90/460 55/2000 NoC3x3-PT-6A-LTLCardinality-02 8242479 m, 64545 m/sec, 49879331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 95/460 56/2000 NoC3x3-PT-6A-LTLCardinality-02 8503892 m, 52282 m/sec, 52533012 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 100/460 58/2000 NoC3x3-PT-6A-LTLCardinality-02 8843102 m, 67842 m/sec, 55216999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 105/460 61/2000 NoC3x3-PT-6A-LTLCardinality-02 9266993 m, 84778 m/sec, 57943648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 110/460 64/2000 NoC3x3-PT-6A-LTLCardinality-02 9713003 m, 89202 m/sec, 60543777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 115/460 66/2000 NoC3x3-PT-6A-LTLCardinality-02 10061317 m, 69662 m/sec, 63199761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 120/460 68/2000 NoC3x3-PT-6A-LTLCardinality-02 10254943 m, 38725 m/sec, 65843314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 125/460 70/2000 NoC3x3-PT-6A-LTLCardinality-02 10642309 m, 77473 m/sec, 68519119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 130/460 73/2000 NoC3x3-PT-6A-LTLCardinality-02 11016690 m, 74876 m/sec, 71194775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 135/460 75/2000 NoC3x3-PT-6A-LTLCardinality-02 11421510 m, 80964 m/sec, 73880587 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 140/460 77/2000 NoC3x3-PT-6A-LTLCardinality-02 11760684 m, 67834 m/sec, 76498217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 145/460 80/2000 NoC3x3-PT-6A-LTLCardinality-02 12103455 m, 68554 m/sec, 79142168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 150/460 82/2000 NoC3x3-PT-6A-LTLCardinality-02 12445955 m, 68500 m/sec, 81804484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 155/460 84/2000 NoC3x3-PT-6A-LTLCardinality-02 12813344 m, 73477 m/sec, 84526981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 160/460 87/2000 NoC3x3-PT-6A-LTLCardinality-02 13186818 m, 74694 m/sec, 87241443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 165/460 89/2000 NoC3x3-PT-6A-LTLCardinality-02 13569973 m, 76631 m/sec, 89903766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 170/460 92/2000 NoC3x3-PT-6A-LTLCardinality-02 13992085 m, 84422 m/sec, 92502449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 175/460 95/2000 NoC3x3-PT-6A-LTLCardinality-02 14410012 m, 83585 m/sec, 95069637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 180/460 97/2000 NoC3x3-PT-6A-LTLCardinality-02 14813923 m, 80782 m/sec, 97624971 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 185/460 100/2000 NoC3x3-PT-6A-LTLCardinality-02 15262793 m, 89774 m/sec, 100019323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 190/460 103/2000 NoC3x3-PT-6A-LTLCardinality-02 15711068 m, 89655 m/sec, 102297884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 195/460 106/2000 NoC3x3-PT-6A-LTLCardinality-02 16133659 m, 84518 m/sec, 104544375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 200/460 108/2000 NoC3x3-PT-6A-LTLCardinality-02 16522046 m, 77677 m/sec, 106880800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 205/460 111/2000 NoC3x3-PT-6A-LTLCardinality-02 16912645 m, 78119 m/sec, 109252730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 210/460 113/2000 NoC3x3-PT-6A-LTLCardinality-02 17283629 m, 74196 m/sec, 111689836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 215/460 115/2000 NoC3x3-PT-6A-LTLCardinality-02 17592708 m, 61815 m/sec, 114297579 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 220/460 118/2000 NoC3x3-PT-6A-LTLCardinality-02 17911495 m, 63757 m/sec, 116995852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 225/460 120/2000 NoC3x3-PT-6A-LTLCardinality-02 18218351 m, 61371 m/sec, 119685580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 230/460 121/2000 NoC3x3-PT-6A-LTLCardinality-02 18400095 m, 36348 m/sec, 122238367 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 235/460 121/2000 NoC3x3-PT-6A-LTLCardinality-02 18409564 m, 1893 m/sec, 124477803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 240/460 121/2000 NoC3x3-PT-6A-LTLCardinality-02 18412939 m, 675 m/sec, 126614578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 245/460 121/2000 NoC3x3-PT-6A-LTLCardinality-02 18414000 m, 212 m/sec, 128777408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 250/460 121/2000 NoC3x3-PT-6A-LTLCardinality-02 18414271 m, 54 m/sec, 131066452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 255/460 123/2000 NoC3x3-PT-6A-LTLCardinality-02 18745148 m, 66175 m/sec, 133802611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 260/460 126/2000 NoC3x3-PT-6A-LTLCardinality-02 19174646 m, 85899 m/sec, 136608518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 265/460 129/2000 NoC3x3-PT-6A-LTLCardinality-02 19634778 m, 92026 m/sec, 139368044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 357
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 270/460 131/2000 NoC3x3-PT-6A-LTLCardinality-02 20001870 m, 73418 m/sec, 142151607 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 275/460 134/2000 NoC3x3-PT-6A-LTLCardinality-02 20412992 m, 82224 m/sec, 144917916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 280/460 136/2000 NoC3x3-PT-6A-LTLCardinality-02 20813568 m, 80115 m/sec, 147645820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 285/460 139/2000 NoC3x3-PT-6A-LTLCardinality-02 21207461 m, 78778 m/sec, 150365561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 290/460 141/2000 NoC3x3-PT-6A-LTLCardinality-02 21541302 m, 66768 m/sec, 153096041 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 295/460 143/2000 NoC3x3-PT-6A-LTLCardinality-02 21881949 m, 68129 m/sec, 155802726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 300/460 146/2000 NoC3x3-PT-6A-LTLCardinality-02 22255975 m, 74805 m/sec, 158588687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 305/460 148/2000 NoC3x3-PT-6A-LTLCardinality-02 22647743 m, 78353 m/sec, 161299524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 310/460 151/2000 NoC3x3-PT-6A-LTLCardinality-02 22976905 m, 65832 m/sec, 164023713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 379
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 315/460 153/2000 NoC3x3-PT-6A-LTLCardinality-02 23309259 m, 66470 m/sec, 166720000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 320/460 156/2000 NoC3x3-PT-6A-LTLCardinality-02 23726424 m, 83433 m/sec, 169494550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 384
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 325/460 158/2000 NoC3x3-PT-6A-LTLCardinality-02 24110761 m, 76867 m/sec, 172284558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 330/460 161/2000 NoC3x3-PT-6A-LTLCardinality-02 24525696 m, 82987 m/sec, 175070810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 389
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 335/460 164/2000 NoC3x3-PT-6A-LTLCardinality-02 24995115 m, 93883 m/sec, 177855604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 392
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 340/460 167/2000 NoC3x3-PT-6A-LTLCardinality-02 25458124 m, 92601 m/sec, 180624810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 345/460 170/2000 NoC3x3-PT-6A-LTLCardinality-02 25851532 m, 78681 m/sec, 183347780 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 398
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 350/460 172/2000 NoC3x3-PT-6A-LTLCardinality-02 26204128 m, 70519 m/sec, 186068247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 355/460 174/2000 NoC3x3-PT-6A-LTLCardinality-02 26551292 m, 69432 m/sec, 188760404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 402
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 360/460 176/2000 NoC3x3-PT-6A-LTLCardinality-02 26909212 m, 71584 m/sec, 191482992 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 365/460 179/2000 NoC3x3-PT-6A-LTLCardinality-02 27289810 m, 76119 m/sec, 194183569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 370/460 181/2000 NoC3x3-PT-6A-LTLCardinality-02 27614192 m, 64876 m/sec, 196882168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 375/460 183/2000 NoC3x3-PT-6A-LTLCardinality-02 27982722 m, 73706 m/sec, 199624468 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 411
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 380/460 186/2000 NoC3x3-PT-6A-LTLCardinality-02 28385298 m, 80515 m/sec, 202395106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 414
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 385/460 189/2000 NoC3x3-PT-6A-LTLCardinality-02 28787234 m, 80387 m/sec, 205123826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 390/460 191/2000 NoC3x3-PT-6A-LTLCardinality-02 29197675 m, 82088 m/sec, 207819598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 419
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 395/460 194/2000 NoC3x3-PT-6A-LTLCardinality-02 29588879 m, 78240 m/sec, 210485819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 400/460 196/2000 NoC3x3-PT-6A-LTLCardinality-02 29993696 m, 80963 m/sec, 213176677 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 405/460 199/2000 NoC3x3-PT-6A-LTLCardinality-02 30319446 m, 65150 m/sec, 215854116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 410/460 201/2000 NoC3x3-PT-6A-LTLCardinality-02 30644482 m, 65007 m/sec, 218445720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 415/460 203/2000 NoC3x3-PT-6A-LTLCardinality-02 31002565 m, 71616 m/sec, 221124378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 420/460 206/2000 NoC3x3-PT-6A-LTLCardinality-02 31392004 m, 77887 m/sec, 223813135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 425/460 208/2000 NoC3x3-PT-6A-LTLCardinality-02 31759952 m, 73589 m/sec, 226483666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 430/460 210/2000 NoC3x3-PT-6A-LTLCardinality-02 32070157 m, 62041 m/sec, 229123120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 438
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 435/460 212/2000 NoC3x3-PT-6A-LTLCardinality-02 32402420 m, 66452 m/sec, 231815706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 440
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 440/460 214/2000 NoC3x3-PT-6A-LTLCardinality-02 32765573 m, 72630 m/sec, 234569681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 442
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 445/460 217/2000 NoC3x3-PT-6A-LTLCardinality-02 33164293 m, 79744 m/sec, 237293671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 450/460 219/2000 NoC3x3-PT-6A-LTLCardinality-02 33495059 m, 66153 m/sec, 240025223 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 455/460 222/2000 NoC3x3-PT-6A-LTLCardinality-02 33857765 m, 72541 m/sec, 242698401 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 450
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 11 LTL EXCL 460/460 224/2000 NoC3x3-PT-6A-LTLCardinality-02 34233048 m, 75056 m/sec, 245381169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 11 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-02 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 454
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 6 (type EXCL) for 3 NoC3x3-PT-6A-LTLCardinality-01
[[35mlola[0m][I] time limit : 460 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 NoC3x3-PT-6A-LTLCardinality-02
[[35mlola[0m][I] time limit : 2300 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 6 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 32
[[35mlola[0m][I] fired transitions : 32
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 11 (type EXCL) for NoC3x3-PT-6A-LTLCardinality-02 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 459
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 NoC3x3-PT-6A-LTLCardinality-00
[[35mlola[0m][I] time limit : 765 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/765 7/2000 NoC3x3-PT-6A-LTLCardinality-00 929862 m, 185972 m/sec, 2426965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 10/765 10/2000 NoC3x3-PT-6A-LTLCardinality-00 1433352 m, 100698 m/sec, 5149739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 15/765 13/2000 NoC3x3-PT-6A-LTLCardinality-00 1837322 m, 80794 m/sec, 7862122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 467
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 20/765 15/2000 NoC3x3-PT-6A-LTLCardinality-00 2244966 m, 81528 m/sec, 10558980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 25/765 18/2000 NoC3x3-PT-6A-LTLCardinality-00 2703392 m, 91685 m/sec, 13259692 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 30/765 22/2000 NoC3x3-PT-6A-LTLCardinality-00 3232114 m, 105744 m/sec, 15930969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 476
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 35/765 24/2000 NoC3x3-PT-6A-LTLCardinality-00 3604502 m, 74477 m/sec, 18605375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 478
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 40/765 27/2000 NoC3x3-PT-6A-LTLCardinality-00 4044328 m, 87965 m/sec, 21269381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 45/765 30/2000 NoC3x3-PT-6A-LTLCardinality-00 4482448 m, 87624 m/sec, 24001689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 484
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 50/765 33/2000 NoC3x3-PT-6A-LTLCardinality-00 4949536 m, 93417 m/sec, 26769561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 55/765 36/2000 NoC3x3-PT-6A-LTLCardinality-00 5419470 m, 93986 m/sec, 29514073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 60/765 39/2000 NoC3x3-PT-6A-LTLCardinality-00 5843472 m, 84800 m/sec, 32234150 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 493
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 65/765 42/2000 NoC3x3-PT-6A-LTLCardinality-00 6247788 m, 80863 m/sec, 34940509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-01: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-04: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-06: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-07: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-12: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-13: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-6A-LTLCardinality-14: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-6A-LTLCardinality-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-02: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-6A-LTLCardinality-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 72/765 44/2000 NoC3x3-PT-6A-LTLCardinality-00 6662044 m, 82851 m/sec, 37400417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1377 secs. Pages in use: 498
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-6A"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is NoC3x3-PT-6A, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353800635"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-6A.tgz
mv NoC3x3-PT-6A execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;