About the Execution of LoLA for NoC3x3-PT-5B
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 11613.955 | 3600000.00 | 1858799.00 | 7381.10 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353800628.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is NoC3x3-PT-5B, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353800628
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 988K
-rw-r--r-- 1 mcc users 7.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 83K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 23 07:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:24 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 108K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 91K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.4K May 19 07:14 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 19 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 525K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-00
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-01
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-02
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-03
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-04
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-05
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-06
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-07
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-08
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-09
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-10
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-11
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-12
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-13
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-14
FORMULA_NAME NoC3x3-PT-5B-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717091830968
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 9 (type CNST) for 6 NoC3x3-PT-5B-LTLFireability-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 43 NoC3x3-PT-5B-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for NoC3x3-PT-5B-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 9 (type CNST) for NoC3x3-PT-5B-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 60 (type CNST) for 57 NoC3x3-PT-5B-LTLFireability-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 60 (type CNST) for NoC3x3-PT-5B-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[*** LOG ERROR #0001 ***] [2024-05-30 17:57:25] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 NoC3x3-PT-5B-LTLFireability-10
[[35mlola[0m][I] time limit : 256 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for NoC3x3-PT-5B-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 13 NoC3x3-PT-5B-LTLFireability-03
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 14 (type EXCL) for NoC3x3-PT-5B-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7233
[[35mlola[0m][I] fired transitions : 9089
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 NoC3x3-PT-5B-LTLFireability-09
[[35mlola[0m][I] time limit : 298 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for NoC3x3-PT-5B-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 71
[[35mlola[0m][I] fired transitions : 71
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 NoC3x3-PT-5B-LTLFireability-04
[[35mlola[0m][I] time limit : 326 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 4/326 2/2000 NoC3x3-PT-5B-LTLFireability-04 154509 m, 30901 m/sec, 331242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 18 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 9/326 3/2000 NoC3x3-PT-5B-LTLFireability-04 366764 m, 42451 m/sec, 848632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 23 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 14/326 4/2000 NoC3x3-PT-5B-LTLFireability-04 580267 m, 42700 m/sec, 1342983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 28 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 19/326 6/2000 NoC3x3-PT-5B-LTLFireability-04 783365 m, 40619 m/sec, 1834593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 33 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 24/326 7/2000 NoC3x3-PT-5B-LTLFireability-04 984604 m, 40247 m/sec, 2335041 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 38 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 29/326 8/2000 NoC3x3-PT-5B-LTLFireability-04 1181465 m, 39372 m/sec, 2839194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 43 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 34/326 10/2000 NoC3x3-PT-5B-LTLFireability-04 1377285 m, 39164 m/sec, 3362427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 48 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 39/326 11/2000 NoC3x3-PT-5B-LTLFireability-04 1577413 m, 40025 m/sec, 3913094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 53 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 44/326 12/2000 NoC3x3-PT-5B-LTLFireability-04 1776843 m, 39886 m/sec, 4471828 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 58 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 49/326 14/2000 NoC3x3-PT-5B-LTLFireability-04 1995551 m, 43741 m/sec, 5122295 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 63 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 54/326 15/2000 NoC3x3-PT-5B-LTLFireability-04 2242994 m, 49488 m/sec, 5860791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 68 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 59/326 17/2000 NoC3x3-PT-5B-LTLFireability-04 2465012 m, 44403 m/sec, 6360145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 73 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 64/326 18/2000 NoC3x3-PT-5B-LTLFireability-04 2680200 m, 43037 m/sec, 6855370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 78 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 69/326 20/2000 NoC3x3-PT-5B-LTLFireability-04 2896967 m, 43353 m/sec, 7359312 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 83 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 74/326 21/2000 NoC3x3-PT-5B-LTLFireability-04 3094618 m, 39530 m/sec, 7837047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 88 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 79/326 22/2000 NoC3x3-PT-5B-LTLFireability-04 3284793 m, 38035 m/sec, 8309665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 93 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 84/326 23/2000 NoC3x3-PT-5B-LTLFireability-04 3471881 m, 37417 m/sec, 8786461 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 98 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 89/326 25/2000 NoC3x3-PT-5B-LTLFireability-04 3658500 m, 37323 m/sec, 9277787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 103 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 94/326 26/2000 NoC3x3-PT-5B-LTLFireability-04 3847435 m, 37787 m/sec, 9794777 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 108 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 99/326 27/2000 NoC3x3-PT-5B-LTLFireability-04 4035691 m, 37651 m/sec, 10318922 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 113 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 104/326 28/2000 NoC3x3-PT-5B-LTLFireability-04 4228773 m, 38616 m/sec, 10878396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 118 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 109/326 30/2000 NoC3x3-PT-5B-LTLFireability-04 4475357 m, 49316 m/sec, 11631042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 123 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 114/326 31/2000 NoC3x3-PT-5B-LTLFireability-04 4671040 m, 39136 m/sec, 12168452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 128 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 119/326 32/2000 NoC3x3-PT-5B-LTLFireability-04 4864152 m, 38622 m/sec, 12703862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 133 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 124/326 34/2000 NoC3x3-PT-5B-LTLFireability-04 5068240 m, 40817 m/sec, 13238227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 138 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 129/326 35/2000 NoC3x3-PT-5B-LTLFireability-04 5274269 m, 41205 m/sec, 13782014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 143 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 134/326 37/2000 NoC3x3-PT-5B-LTLFireability-04 5488485 m, 42843 m/sec, 14311256 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 148 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 139/326 38/2000 NoC3x3-PT-5B-LTLFireability-04 5708799 m, 44062 m/sec, 14894140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 153 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 144/326 39/2000 NoC3x3-PT-5B-LTLFireability-04 5930614 m, 44363 m/sec, 15470307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 158 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 149/326 41/2000 NoC3x3-PT-5B-LTLFireability-04 6147786 m, 43434 m/sec, 16050266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 163 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 154/326 42/2000 NoC3x3-PT-5B-LTLFireability-04 6357583 m, 41959 m/sec, 16617172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 168 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 159/326 44/2000 NoC3x3-PT-5B-LTLFireability-04 6567507 m, 41984 m/sec, 17198812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 173 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 164/326 45/2000 NoC3x3-PT-5B-LTLFireability-04 6777543 m, 42007 m/sec, 17793329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 178 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 169/326 46/2000 NoC3x3-PT-5B-LTLFireability-04 6990290 m, 42549 m/sec, 18407446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 183 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 174/326 48/2000 NoC3x3-PT-5B-LTLFireability-04 7204579 m, 42857 m/sec, 19031833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 188 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 179/326 49/2000 NoC3x3-PT-5B-LTLFireability-04 7424814 m, 44047 m/sec, 19693230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 193 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 184/326 51/2000 NoC3x3-PT-5B-LTLFireability-04 7701538 m, 55344 m/sec, 20552642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 198 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 189/326 52/2000 NoC3x3-PT-5B-LTLFireability-04 7906636 m, 41019 m/sec, 21054350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 203 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 194/326 54/2000 NoC3x3-PT-5B-LTLFireability-04 8117567 m, 42186 m/sec, 21571076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 208 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 199/326 55/2000 NoC3x3-PT-5B-LTLFireability-04 8319515 m, 40389 m/sec, 22058826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 213 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 204/326 56/2000 NoC3x3-PT-5B-LTLFireability-04 8520534 m, 40203 m/sec, 22557328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 218 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 209/326 58/2000 NoC3x3-PT-5B-LTLFireability-04 8729745 m, 41842 m/sec, 23031635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 223 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 214/326 59/2000 NoC3x3-PT-5B-LTLFireability-04 8938226 m, 41696 m/sec, 23534495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 228 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 219/326 61/2000 NoC3x3-PT-5B-LTLFireability-04 9148016 m, 41958 m/sec, 24005309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 233 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 224/326 62/2000 NoC3x3-PT-5B-LTLFireability-04 9348137 m, 40024 m/sec, 24472848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 238 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 229/326 63/2000 NoC3x3-PT-5B-LTLFireability-04 9547262 m, 39825 m/sec, 24941663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 243 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 234/326 64/2000 NoC3x3-PT-5B-LTLFireability-04 9753420 m, 41231 m/sec, 25401605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 248 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 239/326 66/2000 NoC3x3-PT-5B-LTLFireability-04 9958802 m, 41076 m/sec, 25907156 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 253 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 244/326 67/2000 NoC3x3-PT-5B-LTLFireability-04 10158893 m, 40018 m/sec, 26374405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 258 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 249/326 68/2000 NoC3x3-PT-5B-LTLFireability-04 10359889 m, 40199 m/sec, 26844090 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 263 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 254/326 70/2000 NoC3x3-PT-5B-LTLFireability-04 10563825 m, 40787 m/sec, 27325354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 268 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 259/326 71/2000 NoC3x3-PT-5B-LTLFireability-04 10777569 m, 42748 m/sec, 27893996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 273 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 264/326 73/2000 NoC3x3-PT-5B-LTLFireability-04 11010044 m, 46495 m/sec, 28522271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 278 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 269/326 74/2000 NoC3x3-PT-5B-LTLFireability-04 11249507 m, 47892 m/sec, 29204440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 283 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 274/326 76/2000 NoC3x3-PT-5B-LTLFireability-04 11484079 m, 46914 m/sec, 29877679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 288 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 279/326 77/2000 NoC3x3-PT-5B-LTLFireability-04 11719464 m, 47077 m/sec, 30540649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 293 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 284/326 79/2000 NoC3x3-PT-5B-LTLFireability-04 11931439 m, 42395 m/sec, 31062110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 298 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 289/326 80/2000 NoC3x3-PT-5B-LTLFireability-04 12163154 m, 46343 m/sec, 31715954 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 303 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 294/326 82/2000 NoC3x3-PT-5B-LTLFireability-04 12378811 m, 43131 m/sec, 32251386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 308 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 299/326 83/2000 NoC3x3-PT-5B-LTLFireability-04 12598652 m, 43968 m/sec, 32812026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 313 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 304/326 85/2000 NoC3x3-PT-5B-LTLFireability-04 12811616 m, 42592 m/sec, 33350213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 318 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 309/326 86/2000 NoC3x3-PT-5B-LTLFireability-04 13035973 m, 44871 m/sec, 33943411 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 323 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 314/326 88/2000 NoC3x3-PT-5B-LTLFireability-04 13251096 m, 43024 m/sec, 34525844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 328 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 319/326 89/2000 NoC3x3-PT-5B-LTLFireability-04 13471422 m, 44065 m/sec, 35108820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 333 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 324/326 90/2000 NoC3x3-PT-5B-LTLFireability-04 13678075 m, 41330 m/sec, 35655778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 338 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 17 (type EXCL) for NoC3x3-PT-5B-LTLFireability-04 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 343 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 57 NoC3x3-PT-5B-LTLFireability-15
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 NoC3x3-PT-5B-LTLFireability-04
[[35mlola[0m][I] time limit : 3257 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 5/3257 2/5 NoC3x3-PT-5B-LTLFireability-04 204163 m, -2694782 m/sec, 452266 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 5/325 2/2000 NoC3x3-PT-5B-LTLFireability-15 198416 m, 39683 m/sec, 1126514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 348 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 10/3257 3/5 NoC3x3-PT-5B-LTLFireability-04 412211 m, 41609 m/sec, 962425 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 10/296 4/2000 NoC3x3-PT-5B-LTLFireability-15 364774 m, 33271 m/sec, 2250817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 353 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 LTL EXCL 15/3257 5/5 NoC3x3-PT-5B-LTLFireability-04 617258 m, 41009 m/sec, 1427788 t fired, .
[[35mlola[0m][.] 62 LTL EXCL 15/296 5/2000 NoC3x3-PT-5B-LTLFireability-15 527938 m, 32632 m/sec, 3379120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 358 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 17 (type EXCL) for NoC3x3-PT-5B-LTLFireability-04 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 20/296 7/2000 NoC3x3-PT-5B-LTLFireability-15 683790 m, 31170 m/sec, 4502686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 363 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 25/325 8/2000 NoC3x3-PT-5B-LTLFireability-15 840424 m, 31326 m/sec, 5637006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 368 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 30/325 10/2000 NoC3x3-PT-5B-LTLFireability-15 1004262 m, 32767 m/sec, 6768794 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 373 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 35/325 11/2000 NoC3x3-PT-5B-LTLFireability-15 1161207 m, 31389 m/sec, 7910005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 378 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 40/325 12/2000 NoC3x3-PT-5B-LTLFireability-15 1312964 m, 30351 m/sec, 9039968 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 383 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 45/325 14/2000 NoC3x3-PT-5B-LTLFireability-15 1464634 m, 30334 m/sec, 10172683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 388 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 50/325 15/2000 NoC3x3-PT-5B-LTLFireability-15 1615538 m, 30180 m/sec, 11304024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 393 secs. Pages in use: 107
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 55/325 16/2000 NoC3x3-PT-5B-LTLFireability-15 1761671 m, 29226 m/sec, 12433829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 398 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 60/325 18/2000 NoC3x3-PT-5B-LTLFireability-15 1924476 m, 32561 m/sec, 13549761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 403 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 65/325 19/2000 NoC3x3-PT-5B-LTLFireability-15 2079378 m, 30980 m/sec, 14673519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 408 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 70/325 21/2000 NoC3x3-PT-5B-LTLFireability-15 2236646 m, 31453 m/sec, 15800300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 413 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 75/325 22/2000 NoC3x3-PT-5B-LTLFireability-15 2386094 m, 29889 m/sec, 16921336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 418 secs. Pages in use: 114
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 80/325 23/2000 NoC3x3-PT-5B-LTLFireability-15 2529112 m, 28603 m/sec, 18055095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 423 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 85/325 24/2000 NoC3x3-PT-5B-LTLFireability-15 2668600 m, 27897 m/sec, 19186909 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 428 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 90/325 26/2000 NoC3x3-PT-5B-LTLFireability-15 2813495 m, 28979 m/sec, 20316833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 433 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 95/325 27/2000 NoC3x3-PT-5B-LTLFireability-15 2957427 m, 28786 m/sec, 21441149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 438 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 100/325 28/2000 NoC3x3-PT-5B-LTLFireability-15 3105178 m, 29550 m/sec, 22566957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 443 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 105/325 30/2000 NoC3x3-PT-5B-LTLFireability-15 3250208 m, 29006 m/sec, 23689591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 448 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 110/325 31/2000 NoC3x3-PT-5B-LTLFireability-15 3406488 m, 31256 m/sec, 24812577 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 453 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 115/325 32/2000 NoC3x3-PT-5B-LTLFireability-15 3555443 m, 29791 m/sec, 25942143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 458 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 120/325 34/2000 NoC3x3-PT-5B-LTLFireability-15 3697133 m, 28338 m/sec, 27072130 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 463 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 125/325 35/2000 NoC3x3-PT-5B-LTLFireability-15 3845667 m, 29706 m/sec, 28195217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 468 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 130/325 36/2000 NoC3x3-PT-5B-LTLFireability-15 3984933 m, 27853 m/sec, 29324736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 473 secs. Pages in use: 128
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 135/325 38/2000 NoC3x3-PT-5B-LTLFireability-15 4130110 m, 29035 m/sec, 30448346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 478 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 140/325 39/2000 NoC3x3-PT-5B-LTLFireability-15 4277599 m, 29497 m/sec, 31572591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 483 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 145/325 40/2000 NoC3x3-PT-5B-LTLFireability-15 4434379 m, 31356 m/sec, 32699118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 488 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 150/325 42/2000 NoC3x3-PT-5B-LTLFireability-15 4576190 m, 28362 m/sec, 33824855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 493 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 155/325 43/2000 NoC3x3-PT-5B-LTLFireability-15 4716178 m, 27997 m/sec, 34948152 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 498 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 160/325 44/2000 NoC3x3-PT-5B-LTLFireability-15 4862584 m, 29281 m/sec, 36082580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 503 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 165/325 45/2000 NoC3x3-PT-5B-LTLFireability-15 5006262 m, 28735 m/sec, 37216135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 508 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 170/325 47/2000 NoC3x3-PT-5B-LTLFireability-15 5145900 m, 27927 m/sec, 38354424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 513 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 175/325 48/2000 NoC3x3-PT-5B-LTLFireability-15 5302238 m, 31267 m/sec, 39460191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 518 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 180/325 49/2000 NoC3x3-PT-5B-LTLFireability-15 5448613 m, 29275 m/sec, 40561788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 523 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 185/325 50/2000 NoC3x3-PT-5B-LTLFireability-15 5580752 m, 26427 m/sec, 41667435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 528 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 190/325 52/2000 NoC3x3-PT-5B-LTLFireability-15 5732187 m, 30287 m/sec, 42777457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 533 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 195/325 53/2000 NoC3x3-PT-5B-LTLFireability-15 5879815 m, 29525 m/sec, 43911727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 538 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 200/325 54/2000 NoC3x3-PT-5B-LTLFireability-15 6021367 m, 28310 m/sec, 45044424 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 543 secs. Pages in use: 146
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 205/325 56/2000 NoC3x3-PT-5B-LTLFireability-15 6184618 m, 32650 m/sec, 46174710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 548 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 210/325 57/2000 NoC3x3-PT-5B-LTLFireability-15 6335804 m, 30237 m/sec, 47306321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 553 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 215/325 58/2000 NoC3x3-PT-5B-LTLFireability-15 6474099 m, 27659 m/sec, 48434655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 558 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 220/325 60/2000 NoC3x3-PT-5B-LTLFireability-15 6613413 m, 27862 m/sec, 49570655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 563 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 225/325 61/2000 NoC3x3-PT-5B-LTLFireability-15 6763869 m, 30091 m/sec, 50701889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 568 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 230/325 62/2000 NoC3x3-PT-5B-LTLFireability-15 6910981 m, 29422 m/sec, 51826683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 573 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 235/325 64/2000 NoC3x3-PT-5B-LTLFireability-15 7054133 m, 28630 m/sec, 52934111 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 578 secs. Pages in use: 156
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 240/325 65/2000 NoC3x3-PT-5B-LTLFireability-15 7210772 m, 31327 m/sec, 54031140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 583 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 245/325 66/2000 NoC3x3-PT-5B-LTLFireability-15 7352274 m, 28300 m/sec, 55147684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 588 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 250/325 68/2000 NoC3x3-PT-5B-LTLFireability-15 7492544 m, 28054 m/sec, 56258527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 593 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 255/325 69/2000 NoC3x3-PT-5B-LTLFireability-15 7640658 m, 29622 m/sec, 57365578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 598 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 260/325 70/2000 NoC3x3-PT-5B-LTLFireability-15 7778988 m, 27666 m/sec, 58495053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 603 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 265/325 71/2000 NoC3x3-PT-5B-LTLFireability-15 7918402 m, 27882 m/sec, 59624830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 608 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 270/325 73/2000 NoC3x3-PT-5B-LTLFireability-15 8065816 m, 29482 m/sec, 60742266 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 613 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 275/325 74/2000 NoC3x3-PT-5B-LTLFireability-15 8202981 m, 27433 m/sec, 61868762 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 618 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 280/325 75/2000 NoC3x3-PT-5B-LTLFireability-15 8336389 m, 26681 m/sec, 63015504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 623 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 285/325 76/2000 NoC3x3-PT-5B-LTLFireability-15 8478586 m, 28439 m/sec, 64139185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 628 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 290/325 78/2000 NoC3x3-PT-5B-LTLFireability-15 8623748 m, 29032 m/sec, 65252507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 633 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 295/325 79/2000 NoC3x3-PT-5B-LTLFireability-15 8762997 m, 27849 m/sec, 66365755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 638 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 300/325 80/2000 NoC3x3-PT-5B-LTLFireability-15 8903852 m, 28171 m/sec, 67493902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 643 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 305/325 81/2000 NoC3x3-PT-5B-LTLFireability-15 9043669 m, 27963 m/sec, 68626725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 648 secs. Pages in use: 173
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 310/325 83/2000 NoC3x3-PT-5B-LTLFireability-15 9180104 m, 27287 m/sec, 69765914 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 653 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 315/325 84/2000 NoC3x3-PT-5B-LTLFireability-15 9319449 m, 27869 m/sec, 70909416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 658 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 320/325 85/2000 NoC3x3-PT-5B-LTLFireability-15 9460109 m, 28132 m/sec, 72044369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 663 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 325/325 86/2000 NoC3x3-PT-5B-LTLFireability-15 9604510 m, 28880 m/sec, 73181210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 668 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 62 (type EXCL) for NoC3x3-PT-5B-LTLFireability-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 673 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 NoC3x3-PT-5B-LTLFireability-14
[[35mlola[0m][I] time limit : 325 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 57 NoC3x3-PT-5B-LTLFireability-15
[[35mlola[0m][I] time limit : 2927 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for NoC3x3-PT-5B-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 5/325 2/5 NoC3x3-PT-5B-LTLFireability-15 197638 m, -1881374 m/sec, 1120846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 678 secs. Pages in use: 182
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 10/325 4/5 NoC3x3-PT-5B-LTLFireability-15 364335 m, 33339 m/sec, 2247881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 683 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 15/325 5/5 NoC3x3-PT-5B-LTLFireability-15 528515 m, 32836 m/sec, 3383801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 688 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 62 (type EXCL) for NoC3x3-PT-5B-LTLFireability-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 693 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 NoC3x3-PT-5B-LTLFireability-12
[[35mlola[0m][I] time limit : 363 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for NoC3x3-PT-5B-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 48
[[35mlola[0m][I] fired transitions : 48
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 NoC3x3-PT-5B-LTLFireability-08
[[35mlola[0m][I] time limit : 415 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for NoC3x3-PT-5B-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 48
[[35mlola[0m][I] fired transitions : 48
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 NoC3x3-PT-5B-LTLFireability-07
[[35mlola[0m][I] time limit : 484 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 5/484 2/2000 NoC3x3-PT-5B-LTLFireability-07 201121 m, 40224 m/sec, 1143262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 698 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 10/484 4/2000 NoC3x3-PT-5B-LTLFireability-07 371115 m, 33998 m/sec, 2288765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 703 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 15/484 5/2000 NoC3x3-PT-5B-LTLFireability-07 534798 m, 32736 m/sec, 3432072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 708 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 20/484 7/2000 NoC3x3-PT-5B-LTLFireability-07 694547 m, 31949 m/sec, 4580889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 713 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 25/484 8/2000 NoC3x3-PT-5B-LTLFireability-07 855122 m, 32115 m/sec, 5731550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 718 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 30/484 10/2000 NoC3x3-PT-5B-LTLFireability-07 1019450 m, 32865 m/sec, 6882637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 723 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 35/484 11/2000 NoC3x3-PT-5B-LTLFireability-07 1180383 m, 32186 m/sec, 8044025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 728 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 40/484 13/2000 NoC3x3-PT-5B-LTLFireability-07 1331740 m, 30271 m/sec, 9200447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 733 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 45/484 14/2000 NoC3x3-PT-5B-LTLFireability-07 1488854 m, 31422 m/sec, 10357390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 738 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 50/484 15/2000 NoC3x3-PT-5B-LTLFireability-07 1643432 m, 30915 m/sec, 11508617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 743 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 55/484 17/2000 NoC3x3-PT-5B-LTLFireability-07 1795209 m, 30355 m/sec, 12660747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 748 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 60/484 18/2000 NoC3x3-PT-5B-LTLFireability-07 1958866 m, 32731 m/sec, 13800551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 753 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 65/484 19/2000 NoC3x3-PT-5B-LTLFireability-07 2114997 m, 31226 m/sec, 14950444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 758 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 70/484 21/2000 NoC3x3-PT-5B-LTLFireability-07 2276256 m, 32251 m/sec, 16095696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 763 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 75/484 22/2000 NoC3x3-PT-5B-LTLFireability-07 2428704 m, 30489 m/sec, 17246778 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 768 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 80/484 24/2000 NoC3x3-PT-5B-LTLFireability-07 2569939 m, 28247 m/sec, 18404250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 773 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 85/484 25/2000 NoC3x3-PT-5B-LTLFireability-07 2715015 m, 29015 m/sec, 19555814 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 778 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 90/484 26/2000 NoC3x3-PT-5B-LTLFireability-07 2865541 m, 30105 m/sec, 20707126 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 783 secs. Pages in use: 206
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 95/484 28/2000 NoC3x3-PT-5B-LTLFireability-07 3011612 m, 29214 m/sec, 21854075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 788 secs. Pages in use: 208
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 100/484 29/2000 NoC3x3-PT-5B-LTLFireability-07 3160151 m, 29707 m/sec, 23000378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 793 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 105/484 30/2000 NoC3x3-PT-5B-LTLFireability-07 3313057 m, 30581 m/sec, 24145998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 798 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 110/484 32/2000 NoC3x3-PT-5B-LTLFireability-07 3467690 m, 30926 m/sec, 25283410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 803 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 115/484 33/2000 NoC3x3-PT-5B-LTLFireability-07 3614314 m, 29324 m/sec, 26407499 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 808 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 120/484 34/2000 NoC3x3-PT-5B-LTLFireability-07 3759446 m, 29026 m/sec, 27532785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 813 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 125/484 35/2000 NoC3x3-PT-5B-LTLFireability-07 3904389 m, 28988 m/sec, 28674926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 818 secs. Pages in use: 215
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 130/484 37/2000 NoC3x3-PT-5B-LTLFireability-07 4049988 m, 29119 m/sec, 29807578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 823 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 135/484 38/2000 NoC3x3-PT-5B-LTLFireability-07 4189341 m, 27870 m/sec, 30936415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 828 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 140/484 39/2000 NoC3x3-PT-5B-LTLFireability-07 4347906 m, 31713 m/sec, 32059668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 833 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 145/484 41/2000 NoC3x3-PT-5B-LTLFireability-07 4498982 m, 30215 m/sec, 33187218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 838 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 150/484 42/2000 NoC3x3-PT-5B-LTLFireability-07 4637714 m, 27746 m/sec, 34323752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 843 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 155/484 43/2000 NoC3x3-PT-5B-LTLFireability-07 4783029 m, 29063 m/sec, 35454414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 848 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 160/484 45/2000 NoC3x3-PT-5B-LTLFireability-07 4924741 m, 28342 m/sec, 36583771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 853 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 165/484 46/2000 NoC3x3-PT-5B-LTLFireability-07 5067109 m, 28473 m/sec, 37707413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 858 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 170/484 47/2000 NoC3x3-PT-5B-LTLFireability-07 5208623 m, 28302 m/sec, 38832218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 863 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 175/484 49/2000 NoC3x3-PT-5B-LTLFireability-07 5370468 m, 32369 m/sec, 39947603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 868 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 180/484 50/2000 NoC3x3-PT-5B-LTLFireability-07 5510095 m, 27925 m/sec, 41083643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 873 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 185/484 51/2000 NoC3x3-PT-5B-LTLFireability-07 5649774 m, 27935 m/sec, 42207554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 878 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 190/484 52/2000 NoC3x3-PT-5B-LTLFireability-07 5804146 m, 30874 m/sec, 43330221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 883 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 195/484 54/2000 NoC3x3-PT-5B-LTLFireability-07 5949525 m, 29075 m/sec, 44456695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 888 secs. Pages in use: 234
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 200/484 55/2000 NoC3x3-PT-5B-LTLFireability-07 6099018 m, 29898 m/sec, 45583285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 893 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 205/484 57/2000 NoC3x3-PT-5B-LTLFireability-07 6256217 m, 31439 m/sec, 46707779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 898 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 210/484 58/2000 NoC3x3-PT-5B-LTLFireability-07 6402271 m, 29210 m/sec, 47828048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 903 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 215/484 59/2000 NoC3x3-PT-5B-LTLFireability-07 6536090 m, 26763 m/sec, 48954965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 908 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 220/484 60/2000 NoC3x3-PT-5B-LTLFireability-07 6682083 m, 29198 m/sec, 50083094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 913 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 225/484 62/2000 NoC3x3-PT-5B-LTLFireability-07 6831026 m, 29788 m/sec, 51207747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 918 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 230/484 63/2000 NoC3x3-PT-5B-LTLFireability-07 6976542 m, 29103 m/sec, 52327362 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 923 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 235/484 64/2000 NoC3x3-PT-5B-LTLFireability-07 7130541 m, 30799 m/sec, 53438243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 928 secs. Pages in use: 244
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 240/484 66/2000 NoC3x3-PT-5B-LTLFireability-07 7280003 m, 29892 m/sec, 54557940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 933 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 245/484 67/2000 NoC3x3-PT-5B-LTLFireability-07 7420235 m, 28046 m/sec, 55682083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 938 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 250/484 68/2000 NoC3x3-PT-5B-LTLFireability-07 7563902 m, 28733 m/sec, 56798096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 943 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 255/484 70/2000 NoC3x3-PT-5B-LTLFireability-07 7711096 m, 29438 m/sec, 57920325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 948 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 260/484 71/2000 NoC3x3-PT-5B-LTLFireability-07 7844963 m, 26773 m/sec, 59051466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 953 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 265/484 72/2000 NoC3x3-PT-5B-LTLFireability-07 7993302 m, 29667 m/sec, 60177326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 958 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 270/484 73/2000 NoC3x3-PT-5B-LTLFireability-07 8134061 m, 28151 m/sec, 61302209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 963 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 275/484 75/2000 NoC3x3-PT-5B-LTLFireability-07 8271360 m, 27459 m/sec, 62435600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 968 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 280/484 76/2000 NoC3x3-PT-5B-LTLFireability-07 8404828 m, 26693 m/sec, 63568637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 973 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 285/484 77/2000 NoC3x3-PT-5B-LTLFireability-07 8548882 m, 28810 m/sec, 64696528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 978 secs. Pages in use: 257
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 290/484 78/2000 NoC3x3-PT-5B-LTLFireability-07 8696496 m, 29522 m/sec, 65811267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 983 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 295/484 80/2000 NoC3x3-PT-5B-LTLFireability-07 8829213 m, 26543 m/sec, 66930614 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 988 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 300/484 81/2000 NoC3x3-PT-5B-LTLFireability-07 8970513 m, 28260 m/sec, 68049564 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 993 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 305/484 82/2000 NoC3x3-PT-5B-LTLFireability-07 9108594 m, 27616 m/sec, 69170993 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 998 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 310/484 83/2000 NoC3x3-PT-5B-LTLFireability-07 9245871 m, 27455 m/sec, 70297694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1003 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 315/484 84/2000 NoC3x3-PT-5B-LTLFireability-07 9383933 m, 27612 m/sec, 71429428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1008 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 320/484 86/2000 NoC3x3-PT-5B-LTLFireability-07 9524684 m, 28150 m/sec, 72554530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1013 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 325/484 87/2000 NoC3x3-PT-5B-LTLFireability-07 9666844 m, 28432 m/sec, 73677275 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1018 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 330/484 88/2000 NoC3x3-PT-5B-LTLFireability-07 9810862 m, 28803 m/sec, 74796301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1023 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 335/484 90/2000 NoC3x3-PT-5B-LTLFireability-07 9953183 m, 28464 m/sec, 75913077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1028 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 340/484 91/2000 NoC3x3-PT-5B-LTLFireability-07 10077651 m, 24893 m/sec, 77028583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1033 secs. Pages in use: 271
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 345/484 92/2000 NoC3x3-PT-5B-LTLFireability-07 10217366 m, 27943 m/sec, 78139430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1038 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 350/484 93/2000 NoC3x3-PT-5B-LTLFireability-07 10364109 m, 29348 m/sec, 79256522 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1043 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 355/484 94/2000 NoC3x3-PT-5B-LTLFireability-07 10503019 m, 27782 m/sec, 80383758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1048 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 360/484 96/2000 NoC3x3-PT-5B-LTLFireability-07 10640208 m, 27437 m/sec, 81503816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1053 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 365/484 97/2000 NoC3x3-PT-5B-LTLFireability-07 10775535 m, 27065 m/sec, 82628494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1058 secs. Pages in use: 277
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 370/484 98/2000 NoC3x3-PT-5B-LTLFireability-07 10913459 m, 27584 m/sec, 83757833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1063 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 375/484 99/2000 NoC3x3-PT-5B-LTLFireability-07 11058203 m, 28948 m/sec, 84876634 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1068 secs. Pages in use: 279
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 380/484 101/2000 NoC3x3-PT-5B-LTLFireability-07 11209069 m, 30173 m/sec, 86004002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1073 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 385/484 102/2000 NoC3x3-PT-5B-LTLFireability-07 11359969 m, 30180 m/sec, 87131808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1078 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 390/484 103/2000 NoC3x3-PT-5B-LTLFireability-07 11504530 m, 28912 m/sec, 88262415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1083 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 395/484 105/2000 NoC3x3-PT-5B-LTLFireability-07 11645640 m, 28222 m/sec, 89381534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1088 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 400/484 106/2000 NoC3x3-PT-5B-LTLFireability-07 11796586 m, 30189 m/sec, 90502465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1093 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 405/484 107/2000 NoC3x3-PT-5B-LTLFireability-07 11938077 m, 28298 m/sec, 91623875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1098 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 410/484 108/2000 NoC3x3-PT-5B-LTLFireability-07 12074739 m, 27332 m/sec, 92736120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1103 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 415/484 110/2000 NoC3x3-PT-5B-LTLFireability-07 12217261 m, 28504 m/sec, 93838775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1108 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 420/484 111/2000 NoC3x3-PT-5B-LTLFireability-07 12355521 m, 27652 m/sec, 94945290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1113 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 425/484 112/2000 NoC3x3-PT-5B-LTLFireability-07 12491670 m, 27229 m/sec, 96059309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1118 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 430/484 113/2000 NoC3x3-PT-5B-LTLFireability-07 12635098 m, 28685 m/sec, 97174070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1123 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 435/484 115/2000 NoC3x3-PT-5B-LTLFireability-07 12787797 m, 30539 m/sec, 98287783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1128 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 440/484 116/2000 NoC3x3-PT-5B-LTLFireability-07 12922100 m, 26860 m/sec, 99416356 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1133 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 445/484 117/2000 NoC3x3-PT-5B-LTLFireability-07 13060786 m, 27737 m/sec, 100526062 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1138 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 450/484 119/2000 NoC3x3-PT-5B-LTLFireability-07 13205929 m, 29028 m/sec, 101636864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1143 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 455/484 120/2000 NoC3x3-PT-5B-LTLFireability-07 13346040 m, 28022 m/sec, 102747382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1148 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 460/484 121/2000 NoC3x3-PT-5B-LTLFireability-07 13490788 m, 28949 m/sec, 103854007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1153 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 465/484 122/2000 NoC3x3-PT-5B-LTLFireability-07 13633373 m, 28517 m/sec, 104970821 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1158 secs. Pages in use: 302
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 470/484 124/2000 NoC3x3-PT-5B-LTLFireability-07 13772298 m, 27785 m/sec, 106080366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1163 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 475/484 125/2000 NoC3x3-PT-5B-LTLFireability-07 13902588 m, 26058 m/sec, 107195361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1168 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 480/484 126/2000 NoC3x3-PT-5B-LTLFireability-07 14041028 m, 27688 m/sec, 108308268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1173 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 26 (type EXCL) for NoC3x3-PT-5B-LTLFireability-07 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1178 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 NoC3x3-PT-5B-LTLFireability-06
[[35mlola[0m][I] time limit : 484 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 NoC3x3-PT-5B-LTLFireability-07
[[35mlola[0m][I] time limit : 2422 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for NoC3x3-PT-5B-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 48
[[35mlola[0m][I] fired transitions : 48
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 5/484 2/5 NoC3x3-PT-5B-LTLFireability-07 197004 m, -2768804 m/sec, 1116313 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1183 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 10/484 4/5 NoC3x3-PT-5B-LTLFireability-07 362815 m, 33162 m/sec, 2238185 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1188 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 LTL EXCL 15/484 5/5 NoC3x3-PT-5B-LTLFireability-07 525790 m, 32595 m/sec, 3363229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1193 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 26 (type EXCL) for NoC3x3-PT-5B-LTLFireability-07 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1198 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 NoC3x3-PT-5B-LTLFireability-05
[[35mlola[0m][I] time limit : 600 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 5/600 4/2000 NoC3x3-PT-5B-LTLFireability-05 336213 m, 67242 m/sec, 1076422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1203 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 10/600 6/2000 NoC3x3-PT-5B-LTLFireability-05 613433 m, 55444 m/sec, 2165492 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1208 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 15/600 8/2000 NoC3x3-PT-5B-LTLFireability-05 895455 m, 56404 m/sec, 3247679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1213 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 20/600 11/2000 NoC3x3-PT-5B-LTLFireability-05 1169139 m, 54736 m/sec, 4324619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1218 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 25/600 13/2000 NoC3x3-PT-5B-LTLFireability-05 1452447 m, 56661 m/sec, 5403668 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1223 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 30/600 15/2000 NoC3x3-PT-5B-LTLFireability-05 1719776 m, 53465 m/sec, 6491527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1228 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 35/600 18/2000 NoC3x3-PT-5B-LTLFireability-05 1982297 m, 52504 m/sec, 7571557 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1233 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 40/600 20/2000 NoC3x3-PT-5B-LTLFireability-05 2263086 m, 56157 m/sec, 8659281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1238 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 45/600 22/2000 NoC3x3-PT-5B-LTLFireability-05 2547537 m, 56890 m/sec, 9742558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1243 secs. Pages in use: 329
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 50/600 25/2000 NoC3x3-PT-5B-LTLFireability-05 2825582 m, 55609 m/sec, 10820781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1248 secs. Pages in use: 332
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 55/600 27/2000 NoC3x3-PT-5B-LTLFireability-05 3082502 m, 51384 m/sec, 11899027 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1253 secs. Pages in use: 334
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 60/600 29/2000 NoC3x3-PT-5B-LTLFireability-05 3356568 m, 54813 m/sec, 12991662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1258 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 65/600 32/2000 NoC3x3-PT-5B-LTLFireability-05 3633463 m, 55379 m/sec, 14085573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1263 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 70/600 34/2000 NoC3x3-PT-5B-LTLFireability-05 3888629 m, 51033 m/sec, 15176757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1268 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 75/600 36/2000 NoC3x3-PT-5B-LTLFireability-05 4139066 m, 50087 m/sec, 16266756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1273 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 80/600 38/2000 NoC3x3-PT-5B-LTLFireability-05 4401503 m, 52487 m/sec, 17356047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1278 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 85/600 40/2000 NoC3x3-PT-5B-LTLFireability-05 4652556 m, 50210 m/sec, 18427798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1283 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 90/600 42/2000 NoC3x3-PT-5B-LTLFireability-05 4909104 m, 51309 m/sec, 19507907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1288 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 95/600 44/2000 NoC3x3-PT-5B-LTLFireability-05 5147963 m, 47771 m/sec, 20578523 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1293 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 100/600 47/2000 NoC3x3-PT-5B-LTLFireability-05 5406127 m, 51632 m/sec, 21653923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1298 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 105/600 49/2000 NoC3x3-PT-5B-LTLFireability-05 5664331 m, 51640 m/sec, 22730028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1303 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 110/600 51/2000 NoC3x3-PT-5B-LTLFireability-05 5931675 m, 53468 m/sec, 23807988 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1308 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 115/600 53/2000 NoC3x3-PT-5B-LTLFireability-05 6189913 m, 51647 m/sec, 24888509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1313 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 120/600 55/2000 NoC3x3-PT-5B-LTLFireability-05 6438720 m, 49761 m/sec, 25961218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1318 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 125/600 57/2000 NoC3x3-PT-5B-LTLFireability-05 6680488 m, 48353 m/sec, 27048663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1323 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 130/600 60/2000 NoC3x3-PT-5B-LTLFireability-05 6923388 m, 48580 m/sec, 28127739 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1328 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 135/600 62/2000 NoC3x3-PT-5B-LTLFireability-05 7178787 m, 51079 m/sec, 29202048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1333 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 140/600 64/2000 NoC3x3-PT-5B-LTLFireability-05 7434527 m, 51148 m/sec, 30278197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1338 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 145/600 66/2000 NoC3x3-PT-5B-LTLFireability-05 7689032 m, 50901 m/sec, 31356558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1343 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 150/600 68/2000 NoC3x3-PT-5B-LTLFireability-05 7938362 m, 49866 m/sec, 32443077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1348 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 155/600 70/2000 NoC3x3-PT-5B-LTLFireability-05 8195681 m, 51463 m/sec, 33524374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1353 secs. Pages in use: 377
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 160/600 73/2000 NoC3x3-PT-5B-LTLFireability-05 8465704 m, 54004 m/sec, 34595024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1358 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 165/600 75/2000 NoC3x3-PT-5B-LTLFireability-05 8745467 m, 55952 m/sec, 35671636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1363 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 170/600 77/2000 NoC3x3-PT-5B-LTLFireability-05 9005460 m, 51998 m/sec, 36748396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1368 secs. Pages in use: 384
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 175/600 79/2000 NoC3x3-PT-5B-LTLFireability-05 9239332 m, 46774 m/sec, 37820162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1373 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 180/600 81/2000 NoC3x3-PT-5B-LTLFireability-05 9482414 m, 48616 m/sec, 38879334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1378 secs. Pages in use: 388
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 185/600 83/2000 NoC3x3-PT-5B-LTLFireability-05 9737997 m, 51116 m/sec, 39947754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1383 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 190/600 86/2000 NoC3x3-PT-5B-LTLFireability-05 9987383 m, 49877 m/sec, 41011413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1388 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 195/600 88/2000 NoC3x3-PT-5B-LTLFireability-05 10226619 m, 47847 m/sec, 42085553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1393 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 200/600 90/2000 NoC3x3-PT-5B-LTLFireability-05 10472176 m, 49111 m/sec, 43159112 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1398 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 205/600 92/2000 NoC3x3-PT-5B-LTLFireability-05 10710126 m, 47590 m/sec, 44228905 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1403 secs. Pages in use: 399
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 210/600 94/2000 NoC3x3-PT-5B-LTLFireability-05 10949015 m, 47777 m/sec, 45293919 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1408 secs. Pages in use: 401
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 215/600 96/2000 NoC3x3-PT-5B-LTLFireability-05 11195514 m, 49299 m/sec, 46364097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1413 secs. Pages in use: 403
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 220/600 98/2000 NoC3x3-PT-5B-LTLFireability-05 11452471 m, 51391 m/sec, 47432054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1418 secs. Pages in use: 405
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 225/600 100/2000 NoC3x3-PT-5B-LTLFireability-05 11697831 m, 49072 m/sec, 48514657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1423 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 230/600 102/2000 NoC3x3-PT-5B-LTLFireability-05 11940901 m, 48614 m/sec, 49594349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1428 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 235/600 104/2000 NoC3x3-PT-5B-LTLFireability-05 12181913 m, 48202 m/sec, 50675430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1433 secs. Pages in use: 411
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 240/600 106/2000 NoC3x3-PT-5B-LTLFireability-05 12425545 m, 48726 m/sec, 51749713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1438 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 245/600 108/2000 NoC3x3-PT-5B-LTLFireability-05 12674615 m, 49814 m/sec, 52820972 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1443 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 250/600 110/2000 NoC3x3-PT-5B-LTLFireability-05 12917813 m, 48639 m/sec, 53902447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1448 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 255/600 113/2000 NoC3x3-PT-5B-LTLFireability-05 13163110 m, 49059 m/sec, 54979816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1453 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 260/600 115/2000 NoC3x3-PT-5B-LTLFireability-05 13399405 m, 47259 m/sec, 56055504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1458 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 265/600 117/2000 NoC3x3-PT-5B-LTLFireability-05 13642336 m, 48586 m/sec, 57132177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1463 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 270/600 119/2000 NoC3x3-PT-5B-LTLFireability-05 13897567 m, 51046 m/sec, 58205856 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1468 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 275/600 121/2000 NoC3x3-PT-5B-LTLFireability-05 14146254 m, 49737 m/sec, 59282350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1473 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 280/600 123/2000 NoC3x3-PT-5B-LTLFireability-05 14398580 m, 50465 m/sec, 60350479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1478 secs. Pages in use: 430
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 285/600 125/2000 NoC3x3-PT-5B-LTLFireability-05 14642365 m, 48757 m/sec, 61420507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1483 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 290/600 127/2000 NoC3x3-PT-5B-LTLFireability-05 14893667 m, 50260 m/sec, 62487663 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1488 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 295/600 129/2000 NoC3x3-PT-5B-LTLFireability-05 15145799 m, 50426 m/sec, 63558104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1493 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 300/600 132/2000 NoC3x3-PT-5B-LTLFireability-05 15396196 m, 50079 m/sec, 64624812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1498 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 305/600 134/2000 NoC3x3-PT-5B-LTLFireability-05 15642795 m, 49319 m/sec, 65700296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1503 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 310/600 136/2000 NoC3x3-PT-5B-LTLFireability-05 15869186 m, 45278 m/sec, 66774839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1508 secs. Pages in use: 443
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 315/600 138/2000 NoC3x3-PT-5B-LTLFireability-05 16122023 m, 50567 m/sec, 67847292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1513 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 320/600 140/2000 NoC3x3-PT-5B-LTLFireability-05 16363021 m, 48199 m/sec, 68925651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1518 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 325/600 142/2000 NoC3x3-PT-5B-LTLFireability-05 16615858 m, 50567 m/sec, 69999676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1523 secs. Pages in use: 449
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 330/600 144/2000 NoC3x3-PT-5B-LTLFireability-05 16852952 m, 47418 m/sec, 71076876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1528 secs. Pages in use: 451
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 335/600 146/2000 NoC3x3-PT-5B-LTLFireability-05 17093748 m, 48159 m/sec, 72145371 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1533 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 340/600 148/2000 NoC3x3-PT-5B-LTLFireability-05 17332829 m, 47816 m/sec, 73219759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1538 secs. Pages in use: 455
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 345/600 150/2000 NoC3x3-PT-5B-LTLFireability-05 17578995 m, 49233 m/sec, 74286029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1543 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 350/600 152/2000 NoC3x3-PT-5B-LTLFireability-05 17805276 m, 45256 m/sec, 75357419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1548 secs. Pages in use: 459
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 355/600 154/2000 NoC3x3-PT-5B-LTLFireability-05 18044109 m, 47766 m/sec, 76410610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1553 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 360/600 156/2000 NoC3x3-PT-5B-LTLFireability-05 18280575 m, 47293 m/sec, 77471494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1558 secs. Pages in use: 463
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 365/600 158/2000 NoC3x3-PT-5B-LTLFireability-05 18521069 m, 48098 m/sec, 78545071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1563 secs. Pages in use: 465
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 370/600 160/2000 NoC3x3-PT-5B-LTLFireability-05 18757642 m, 47314 m/sec, 79614208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1568 secs. Pages in use: 467
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 375/600 162/2000 NoC3x3-PT-5B-LTLFireability-05 18996420 m, 47755 m/sec, 80683290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1573 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 380/600 164/2000 NoC3x3-PT-5B-LTLFireability-05 19222798 m, 45275 m/sec, 81745028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1578 secs. Pages in use: 471
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 385/600 166/2000 NoC3x3-PT-5B-LTLFireability-05 19447545 m, 44949 m/sec, 82812250 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1583 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 390/600 168/2000 NoC3x3-PT-5B-LTLFireability-05 19682695 m, 47030 m/sec, 83878715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1588 secs. Pages in use: 475
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 395/600 170/2000 NoC3x3-PT-5B-LTLFireability-05 19919343 m, 47329 m/sec, 84948408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1593 secs. Pages in use: 477
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 400/600 172/2000 NoC3x3-PT-5B-LTLFireability-05 20157164 m, 47564 m/sec, 86020698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1598 secs. Pages in use: 479
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 405/600 174/2000 NoC3x3-PT-5B-LTLFireability-05 20396599 m, 47887 m/sec, 87111356 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1603 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 410/600 176/2000 NoC3x3-PT-5B-LTLFireability-05 20635876 m, 47855 m/sec, 88176349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1608 secs. Pages in use: 483
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 415/600 178/2000 NoC3x3-PT-5B-LTLFireability-05 20892682 m, 51361 m/sec, 89240488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1613 secs. Pages in use: 485
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 420/600 180/2000 NoC3x3-PT-5B-LTLFireability-05 21138139 m, 49091 m/sec, 90310757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1618 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 425/600 182/2000 NoC3x3-PT-5B-LTLFireability-05 21392642 m, 50900 m/sec, 91374134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1623 secs. Pages in use: 489
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 430/600 184/2000 NoC3x3-PT-5B-LTLFireability-05 21618457 m, 45163 m/sec, 92446788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1628 secs. Pages in use: 491
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 435/600 187/2000 NoC3x3-PT-5B-LTLFireability-05 21873538 m, 51016 m/sec, 93518870 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1633 secs. Pages in use: 494
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 440/600 189/2000 NoC3x3-PT-5B-LTLFireability-05 22107904 m, 46873 m/sec, 94581105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1638 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 445/600 191/2000 NoC3x3-PT-5B-LTLFireability-05 22364190 m, 51257 m/sec, 95643202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1643 secs. Pages in use: 498
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 450/600 193/2000 NoC3x3-PT-5B-LTLFireability-05 22620812 m, 51324 m/sec, 96707756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1648 secs. Pages in use: 500
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 455/600 195/2000 NoC3x3-PT-5B-LTLFireability-05 22869900 m, 49817 m/sec, 97782278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1653 secs. Pages in use: 502
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 460/600 197/2000 NoC3x3-PT-5B-LTLFireability-05 23103569 m, 46733 m/sec, 98870149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1658 secs. Pages in use: 504
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 465/600 199/2000 NoC3x3-PT-5B-LTLFireability-05 23334345 m, 46155 m/sec, 99937611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1663 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 470/600 201/2000 NoC3x3-PT-5B-LTLFireability-05 23570004 m, 47131 m/sec, 100998533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1668 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 475/600 203/2000 NoC3x3-PT-5B-LTLFireability-05 23793224 m, 44644 m/sec, 102071874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1673 secs. Pages in use: 510
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 480/600 205/2000 NoC3x3-PT-5B-LTLFireability-05 24012062 m, 43767 m/sec, 103132307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1678 secs. Pages in use: 512
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 485/600 207/2000 NoC3x3-PT-5B-LTLFireability-05 24244760 m, 46539 m/sec, 104196657 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1683 secs. Pages in use: 514
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 490/600 209/2000 NoC3x3-PT-5B-LTLFireability-05 24478343 m, 46716 m/sec, 105255118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1688 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 495/600 211/2000 NoC3x3-PT-5B-LTLFireability-05 24715212 m, 47373 m/sec, 106321551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1693 secs. Pages in use: 518
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 500/600 213/2000 NoC3x3-PT-5B-LTLFireability-05 24970425 m, 51042 m/sec, 107382799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1698 secs. Pages in use: 520
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 505/600 215/2000 NoC3x3-PT-5B-LTLFireability-05 25206309 m, 47176 m/sec, 108445948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1703 secs. Pages in use: 522
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 510/600 217/2000 NoC3x3-PT-5B-LTLFireability-05 25461415 m, 51021 m/sec, 109511376 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1708 secs. Pages in use: 524
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 515/600 219/2000 NoC3x3-PT-5B-LTLFireability-05 25703376 m, 48392 m/sec, 110584381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1713 secs. Pages in use: 526
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 520/600 221/2000 NoC3x3-PT-5B-LTLFireability-05 25942869 m, 47898 m/sec, 111656670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1718 secs. Pages in use: 528
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 525/600 223/2000 NoC3x3-PT-5B-LTLFireability-05 26176214 m, 46669 m/sec, 112719514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1723 secs. Pages in use: 530
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 530/600 225/2000 NoC3x3-PT-5B-LTLFireability-05 26427906 m, 50338 m/sec, 113788873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1728 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 535/600 228/2000 NoC3x3-PT-5B-LTLFireability-05 26673991 m, 49217 m/sec, 114853549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1733 secs. Pages in use: 535
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 540/600 230/2000 NoC3x3-PT-5B-LTLFireability-05 26918741 m, 48950 m/sec, 115921274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1738 secs. Pages in use: 537
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 545/600 232/2000 NoC3x3-PT-5B-LTLFireability-05 27144864 m, 45224 m/sec, 117001779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1743 secs. Pages in use: 539
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 550/600 234/2000 NoC3x3-PT-5B-LTLFireability-05 27379300 m, 46887 m/sec, 118072737 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1748 secs. Pages in use: 541
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 555/600 235/2000 NoC3x3-PT-5B-LTLFireability-05 27599555 m, 44051 m/sec, 119137097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1753 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 560/600 237/2000 NoC3x3-PT-5B-LTLFireability-05 27821944 m, 44477 m/sec, 120204782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1758 secs. Pages in use: 544
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 565/600 239/2000 NoC3x3-PT-5B-LTLFireability-05 28047781 m, 45167 m/sec, 121260402 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1763 secs. Pages in use: 546
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 570/600 241/2000 NoC3x3-PT-5B-LTLFireability-05 28278595 m, 46162 m/sec, 122329509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1768 secs. Pages in use: 548
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 575/600 243/2000 NoC3x3-PT-5B-LTLFireability-05 28523421 m, 48965 m/sec, 123404732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1773 secs. Pages in use: 550
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 580/600 245/2000 NoC3x3-PT-5B-LTLFireability-05 28753495 m, 46014 m/sec, 124468543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1778 secs. Pages in use: 552
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 585/600 247/2000 NoC3x3-PT-5B-LTLFireability-05 28995704 m, 48441 m/sec, 125534660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1783 secs. Pages in use: 554
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 590/600 249/2000 NoC3x3-PT-5B-LTLFireability-05 29218965 m, 44652 m/sec, 126593162 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1788 secs. Pages in use: 556
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 595/600 251/2000 NoC3x3-PT-5B-LTLFireability-05 29460631 m, 48333 m/sec, 127657926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1793 secs. Pages in use: 558
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 600/600 253/2000 NoC3x3-PT-5B-LTLFireability-05 29682778 m, 44429 m/sec, 128711798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1798 secs. Pages in use: 560
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 20 (type EXCL) for NoC3x3-PT-5B-LTLFireability-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1803 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 NoC3x3-PT-5B-LTLFireability-00
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 NoC3x3-PT-5B-LTLFireability-05
[[35mlola[0m][I] time limit : 1797 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for NoC3x3-PT-5B-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 94
[[35mlola[0m][I] fired transitions : 95
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 5/599 4/5 NoC3x3-PT-5B-LTLFireability-05 336161 m, -5869323 m/sec, 1076204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1808 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 20 (type EXCL) for NoC3x3-PT-5B-LTLFireability-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1813 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 NoC3x3-PT-5B-LTLFireability-11
[[35mlola[0m][I] time limit : 893 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for NoC3x3-PT-5B-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 NoC3x3-PT-5B-LTLFireability-01
[[35mlola[0m][I] time limit : 1787 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for NoC3x3-PT-5B-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 22
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1818 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1823 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1828 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1833 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1838 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1843 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1848 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1853 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1858 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1863 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1868 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1873 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1878 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1883 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1888 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1893 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1898 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1903 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1908 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1913 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1918 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1923 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1928 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1933 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1938 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1943 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1948 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1953 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1958 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1963 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1968 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1973 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1978 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1983 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1988 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1993 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1998 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2003 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2008 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2013 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2018 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2023 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2028 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2033 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2038 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2043 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2048 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2053 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2058 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2063 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2068 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2073 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2078 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2083 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2088 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2093 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2098 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2103 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2108 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2113 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2118 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2123 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2128 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2133 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2138 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2143 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2148 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2153 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2158 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2163 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2168 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2173 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2178 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2183 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2188 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2193 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 2198 secs. Pages in use: 562
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-02: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-5B-LTLFireability-13: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-5B-LTLFireability-14: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-04: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-07: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NoC3x3-PT-5B-LTLFireability-15: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-5B"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is NoC3x3-PT-5B, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353800628"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-5B.tgz
mv NoC3x3-PT-5B execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;