About the Execution of LoLA for NoC3x3-PT-1A
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16203.964 | 467586.00 | 476180.00 | 1457.10 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353600555.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is NoC3x3-PT-1A, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353600555
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 23 07:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 23 07:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Apr 23 07:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 23 07:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 07:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 151K Apr 12 07:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Apr 12 07:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 12 07:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 23 07:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 23 07:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 81K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-00
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-01
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-02
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-03
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-04
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-05
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-06
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-07
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-08
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-09
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-10
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-11
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-12
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-13
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-14
FORMULA_NAME NoC3x3-PT-1A-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717083980867
BK_STOP 1717084448453
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 NoC3x3-PT-1A-LTLCardinality-01
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 NoC3x3-PT-1A-LTLCardinality-02
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 13 (type CNST) for 12 NoC3x3-PT-1A-LTLCardinality-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 25 (type CNST) for 24 NoC3x3-PT-1A-LTLCardinality-08
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 25 (type CNST) for NoC3x3-PT-1A-LTLCardinality-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 13 (type CNST) for NoC3x3-PT-1A-LTLCardinality-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 10
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 NoC3x3-PT-1A-LTLCardinality-12
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 37 NoC3x3-PT-1A-LTLCardinality-11
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 37 NoC3x3-PT-1A-LTLCardinality-11
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 30 NoC3x3-PT-1A-LTLCardinality-10
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 NoC3x3-PT-1A-LTLCardinality-05
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 NoC3x3-PT-1A-LTLCardinality-09
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for NoC3x3-PT-1A-LTLCardinality-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 NoC3x3-PT-1A-LTLCardinality-07
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 5/514 9/2000 NoC3x3-PT-1A-LTLCardinality-07 1378625 m, 275725 m/sec, 4817282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 10/514 17/2000 NoC3x3-PT-1A-LTLCardinality-07 2571351 m, 238545 m/sec, 9224278 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 12 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 15/514 27/2000 NoC3x3-PT-1A-LTLCardinality-07 4068264 m, 299382 m/sec, 14415238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 17 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 20/514 36/2000 NoC3x3-PT-1A-LTLCardinality-07 5451526 m, 276652 m/sec, 19225991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 22 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 25/514 43/2000 NoC3x3-PT-1A-LTLCardinality-07 6558964 m, 221487 m/sec, 23409392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 27 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 30/514 50/2000 NoC3x3-PT-1A-LTLCardinality-07 7530650 m, 194337 m/sec, 27175584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 32 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 35/514 55/2000 NoC3x3-PT-1A-LTLCardinality-07 8403324 m, 174534 m/sec, 30515169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 37 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 40/514 63/2000 NoC3x3-PT-1A-LTLCardinality-07 9526977 m, 224730 m/sec, 34571938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 42 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 45/514 71/2000 NoC3x3-PT-1A-LTLCardinality-07 10893001 m, 273204 m/sec, 39427893 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 47 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 50/514 79/2000 NoC3x3-PT-1A-LTLCardinality-07 12068237 m, 235047 m/sec, 43651826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 52 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 55/514 86/2000 NoC3x3-PT-1A-LTLCardinality-07 13146967 m, 215746 m/sec, 47665687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 57 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 60/514 92/2000 NoC3x3-PT-1A-LTLCardinality-07 14109526 m, 192511 m/sec, 51386106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 62 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 65/514 99/2000 NoC3x3-PT-1A-LTLCardinality-07 15069171 m, 191929 m/sec, 55110408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 67 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 70/514 105/2000 NoC3x3-PT-1A-LTLCardinality-07 15970396 m, 180245 m/sec, 58648897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 72 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 75/514 111/2000 NoC3x3-PT-1A-LTLCardinality-07 16880969 m, 182114 m/sec, 62272645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 77 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 80/514 117/2000 NoC3x3-PT-1A-LTLCardinality-07 17826185 m, 189043 m/sec, 65893808 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 82 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 85/514 122/2000 NoC3x3-PT-1A-LTLCardinality-07 18713054 m, 177373 m/sec, 69369031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 87 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 90/514 129/2000 NoC3x3-PT-1A-LTLCardinality-07 19763836 m, 210156 m/sec, 73298849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 92 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 95/514 138/2000 NoC3x3-PT-1A-LTLCardinality-07 21096715 m, 266575 m/sec, 78034643 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 97 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 100/514 148/2000 NoC3x3-PT-1A-LTLCardinality-07 22574411 m, 295539 m/sec, 83244443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 102 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 105/514 155/2000 NoC3x3-PT-1A-LTLCardinality-07 23720307 m, 229179 m/sec, 87327467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 107 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 110/514 162/2000 NoC3x3-PT-1A-LTLCardinality-07 24827780 m, 221494 m/sec, 91299206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 112 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 115/514 172/2000 NoC3x3-PT-1A-LTLCardinality-07 26280946 m, 290633 m/sec, 96544419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 117 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 120/514 180/2000 NoC3x3-PT-1A-LTLCardinality-07 27606335 m, 265077 m/sec, 101808476 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 122 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 125/514 189/2000 NoC3x3-PT-1A-LTLCardinality-07 28911544 m, 261041 m/sec, 106606991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 127 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 130/514 197/2000 NoC3x3-PT-1A-LTLCardinality-07 30157325 m, 249156 m/sec, 111197177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 132 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 135/514 204/2000 NoC3x3-PT-1A-LTLCardinality-07 31238916 m, 216318 m/sec, 115376633 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 137 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 140/514 212/2000 NoC3x3-PT-1A-LTLCardinality-07 32411952 m, 234607 m/sec, 119844056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 142 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 145/514 221/2000 NoC3x3-PT-1A-LTLCardinality-07 33769292 m, 271468 m/sec, 124999934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 147 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 150/514 229/2000 NoC3x3-PT-1A-LTLCardinality-07 35086287 m, 263399 m/sec, 130047618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 152 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 155/514 236/2000 NoC3x3-PT-1A-LTLCardinality-07 36161991 m, 215140 m/sec, 135048024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 157 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 160/514 242/2000 NoC3x3-PT-1A-LTLCardinality-07 37081657 m, 183933 m/sec, 139731529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 162 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 165/514 248/2000 NoC3x3-PT-1A-LTLCardinality-07 37940931 m, 171854 m/sec, 144209358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 167 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 170/514 253/2000 NoC3x3-PT-1A-LTLCardinality-07 38764947 m, 164803 m/sec, 148611848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 172 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 175/514 259/2000 NoC3x3-PT-1A-LTLCardinality-07 39542313 m, 155473 m/sec, 152860493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 177 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 180/514 264/2000 NoC3x3-PT-1A-LTLCardinality-07 40303713 m, 152280 m/sec, 157077789 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 182 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 185/514 269/2000 NoC3x3-PT-1A-LTLCardinality-07 41049012 m, 149059 m/sec, 161270827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 187 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 190/514 273/2000 NoC3x3-PT-1A-LTLCardinality-07 41774132 m, 145024 m/sec, 165394412 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 192 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 195/514 278/2000 NoC3x3-PT-1A-LTLCardinality-07 42487294 m, 142632 m/sec, 169479153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 197 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 200/514 283/2000 NoC3x3-PT-1A-LTLCardinality-07 43193076 m, 141156 m/sec, 173554104 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 202 secs. Pages in use: 283
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 205/514 287/2000 NoC3x3-PT-1A-LTLCardinality-07 43887596 m, 138904 m/sec, 177602459 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 207 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 210/514 292/2000 NoC3x3-PT-1A-LTLCardinality-07 44572647 m, 137010 m/sec, 181616948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 212 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 215/514 296/2000 NoC3x3-PT-1A-LTLCardinality-07 45254966 m, 136463 m/sec, 185647442 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 217 secs. Pages in use: 296
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 220/514 301/2000 NoC3x3-PT-1A-LTLCardinality-07 45935656 m, 136138 m/sec, 189695758 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 222 secs. Pages in use: 301
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 225/514 305/2000 NoC3x3-PT-1A-LTLCardinality-07 46606977 m, 134264 m/sec, 193706169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 227 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 230/514 309/2000 NoC3x3-PT-1A-LTLCardinality-07 47266270 m, 131858 m/sec, 197671214 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 232 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 235/514 314/2000 NoC3x3-PT-1A-LTLCardinality-07 47912685 m, 129283 m/sec, 201570756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 237 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 240/514 318/2000 NoC3x3-PT-1A-LTLCardinality-07 48562339 m, 129930 m/sec, 205514145 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 242 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 245/514 322/2000 NoC3x3-PT-1A-LTLCardinality-07 49203347 m, 128201 m/sec, 209443227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 247 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 250/514 326/2000 NoC3x3-PT-1A-LTLCardinality-07 49845552 m, 128441 m/sec, 213360524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 252 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 255/514 331/2000 NoC3x3-PT-1A-LTLCardinality-07 50478004 m, 126490 m/sec, 217284649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 257 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 260/514 335/2000 NoC3x3-PT-1A-LTLCardinality-07 51102227 m, 124844 m/sec, 221171613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 262 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 265/514 339/2000 NoC3x3-PT-1A-LTLCardinality-07 51728149 m, 125184 m/sec, 225062554 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 267 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 270/514 343/2000 NoC3x3-PT-1A-LTLCardinality-07 52350319 m, 124434 m/sec, 228923247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 272 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 275/514 347/2000 NoC3x3-PT-1A-LTLCardinality-07 52966383 m, 123212 m/sec, 232781449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 277 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 280/514 351/2000 NoC3x3-PT-1A-LTLCardinality-07 53578306 m, 122384 m/sec, 236621471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 282 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 285/514 355/2000 NoC3x3-PT-1A-LTLCardinality-07 54187366 m, 121812 m/sec, 240469200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 287 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 290/514 359/2000 NoC3x3-PT-1A-LTLCardinality-07 54794374 m, 121401 m/sec, 244296238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 292 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 295/514 363/2000 NoC3x3-PT-1A-LTLCardinality-07 55402091 m, 121543 m/sec, 248150040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 297 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 300/514 367/2000 NoC3x3-PT-1A-LTLCardinality-07 56000330 m, 119647 m/sec, 251956210 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 305/514 371/2000 NoC3x3-PT-1A-LTLCardinality-07 56592911 m, 118516 m/sec, 255748617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 307 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 310/514 375/2000 NoC3x3-PT-1A-LTLCardinality-07 57186724 m, 118762 m/sec, 259535615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 312 secs. Pages in use: 375
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 315/514 379/2000 NoC3x3-PT-1A-LTLCardinality-07 57776389 m, 117933 m/sec, 263325115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 317 secs. Pages in use: 379
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 320/514 382/2000 NoC3x3-PT-1A-LTLCardinality-07 58362526 m, 117227 m/sec, 267091547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 322 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 325/514 386/2000 NoC3x3-PT-1A-LTLCardinality-07 58948037 m, 117102 m/sec, 270845656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 327 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 330/514 390/2000 NoC3x3-PT-1A-LTLCardinality-07 59527809 m, 115954 m/sec, 274585841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 332 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 335/514 394/2000 NoC3x3-PT-1A-LTLCardinality-07 60104201 m, 115278 m/sec, 278315206 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 337 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 340/514 398/2000 NoC3x3-PT-1A-LTLCardinality-07 60684866 m, 116133 m/sec, 282077891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 342 secs. Pages in use: 398
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 345/514 401/2000 NoC3x3-PT-1A-LTLCardinality-07 61260384 m, 115103 m/sec, 285814524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 347 secs. Pages in use: 401
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 350/514 405/2000 NoC3x3-PT-1A-LTLCardinality-07 61833672 m, 114657 m/sec, 289552712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 352 secs. Pages in use: 405
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 355/514 409/2000 NoC3x3-PT-1A-LTLCardinality-07 62399711 m, 113207 m/sec, 293259874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 357 secs. Pages in use: 409
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 360/514 413/2000 NoC3x3-PT-1A-LTLCardinality-07 62964633 m, 112984 m/sec, 296982481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 362 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 365/514 416/2000 NoC3x3-PT-1A-LTLCardinality-07 63532082 m, 113489 m/sec, 300713177 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 367 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 370/514 420/2000 NoC3x3-PT-1A-LTLCardinality-07 64092742 m, 112132 m/sec, 304402747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 372 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 375/514 424/2000 NoC3x3-PT-1A-LTLCardinality-07 64659419 m, 113335 m/sec, 308107007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 377 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 380/514 427/2000 NoC3x3-PT-1A-LTLCardinality-07 65220214 m, 112159 m/sec, 311809106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 382 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 385/514 431/2000 NoC3x3-PT-1A-LTLCardinality-07 65778554 m, 111668 m/sec, 315499054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 387 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 390/514 435/2000 NoC3x3-PT-1A-LTLCardinality-07 66337184 m, 111726 m/sec, 319188572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 392 secs. Pages in use: 435
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 395/514 438/2000 NoC3x3-PT-1A-LTLCardinality-07 66892128 m, 110988 m/sec, 322885139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 397 secs. Pages in use: 438
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 400/514 442/2000 NoC3x3-PT-1A-LTLCardinality-07 67444350 m, 110444 m/sec, 326560429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 402 secs. Pages in use: 442
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 405/514 446/2000 NoC3x3-PT-1A-LTLCardinality-07 67994795 m, 110089 m/sec, 330226133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 407 secs. Pages in use: 446
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 410/514 449/2000 NoC3x3-PT-1A-LTLCardinality-07 68541832 m, 109407 m/sec, 333896176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 412 secs. Pages in use: 449
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 415/514 453/2000 NoC3x3-PT-1A-LTLCardinality-07 69084396 m, 108512 m/sec, 337540342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 417 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 420/514 456/2000 NoC3x3-PT-1A-LTLCardinality-07 69627351 m, 108591 m/sec, 341188311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 422 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 425/514 460/2000 NoC3x3-PT-1A-LTLCardinality-07 70169073 m, 108344 m/sec, 344833796 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 427 secs. Pages in use: 460
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 430/514 463/2000 NoC3x3-PT-1A-LTLCardinality-07 70710475 m, 108280 m/sec, 348500705 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 432 secs. Pages in use: 463
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 435/514 467/2000 NoC3x3-PT-1A-LTLCardinality-07 71250572 m, 108019 m/sec, 352158770 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 437 secs. Pages in use: 467
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 440/514 470/2000 NoC3x3-PT-1A-LTLCardinality-07 71785388 m, 106963 m/sec, 355783622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 442 secs. Pages in use: 470
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 445/514 474/2000 NoC3x3-PT-1A-LTLCardinality-07 72320972 m, 107116 m/sec, 359406666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 447 secs. Pages in use: 474
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 450/514 478/2000 NoC3x3-PT-1A-LTLCardinality-07 72856253 m, 107056 m/sec, 363041428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 452 secs. Pages in use: 478
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 455/514 481/2000 NoC3x3-PT-1A-LTLCardinality-07 73389507 m, 106650 m/sec, 366675222 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 457 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-01: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-04: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mNoC3x3-PT-1A-LTLCardinality-08: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-09: LTL/CTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mNoC3x3-PT-1A-LTLCardinality-12: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NoC3x3-PT-1A-LTLCardinality-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 460/514 485/2000 NoC3x3-PT-1A-LTLCardinality-07 73931344 m, 108367 m/sec, 370343092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 462 secs. Pages in use: 485
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NoC3x3-PT-1A"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is NoC3x3-PT-1A, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353600555"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NoC3x3-PT-1A.tgz
mv NoC3x3-PT-1A execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;