About the Execution of LoLA for NeoElection-PT-5
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
0.000 | 605724.00 | 0.00 | 0.00 | [undef] | Cannot compute |
Execution Chart
Sorry, for this execution, no execution chart could be reported.
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353500522.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is NeoElection-PT-5, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353500522
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 13M
-rw-r--r-- 1 mcc users 171K Apr 11 18:51 CTLCardinality.txt
-rw-r--r-- 1 mcc users 581K Apr 11 18:51 CTLCardinality.xml
-rw-r--r-- 1 mcc users 441K Apr 11 18:35 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.5M Apr 11 18:35 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:43 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:43 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 161K Apr 23 07:40 LTLCardinality.txt
-rw-r--r-- 1 mcc users 369K Apr 23 07:40 LTLCardinality.xml
-rw-r--r-- 1 mcc users 91K Apr 23 07:40 LTLFireability.txt
-rw-r--r-- 1 mcc users 232K Apr 23 07:40 LTLFireability.xml
-rw-r--r-- 1 mcc users 670K Apr 11 19:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 2.2M Apr 11 19:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 534K Apr 11 19:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 1.8M Apr 11 19:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 39K Apr 23 07:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 76K Apr 23 07:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 4.2M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-00
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-01
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-02
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-03
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-04
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-05
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-06
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-07
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-08
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-09
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-10
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-11
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-12
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-13
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-14
FORMULA_NAME NeoElection-PT-5-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717079130947
BK_STOP 1717079736671
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 4438 transitions removed,2866 places removed
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 12 NeoElection-PT-5-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 143 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 NeoElection-PT-5-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 20 (type CNST) for 19 NeoElection-PT-5-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 35 (type CNST) for 34 NeoElection-PT-5-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 41 (type CNST) for 40 NeoElection-PT-5-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 20 (type CNST) for NeoElection-PT-5-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 NeoElection-PT-5-CTLFireability-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 35 (type CNST) for NeoElection-PT-5-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 268
[[35mlola[0m][I] fired transitions : 360
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 NeoElection-PT-5-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for NeoElection-PT-5-CTLFireability-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 41 (type CNST) for NeoElection-PT-5-CTLFireability-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 NeoElection-PT-5-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for NeoElection-PT-5-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 3/359 3/2000 NeoElection-PT-5-CTLFireability-2024-09 575789 m, 115157 m/sec, 2632559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 8/359 7/2000 NeoElection-PT-5-CTLFireability-2024-09 1529312 m, 190704 m/sec, 7364556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 13/359 11/2000 NeoElection-PT-5-CTLFireability-2024-09 2483948 m, 190927 m/sec, 12076093 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 18/359 15/2000 NeoElection-PT-5-CTLFireability-2024-09 3400543 m, 183319 m/sec, 16644395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 23/359 19/2000 NeoElection-PT-5-CTLFireability-2024-09 4393708 m, 198633 m/sec, 21498469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 28/359 23/2000 NeoElection-PT-5-CTLFireability-2024-09 5292608 m, 179780 m/sec, 26169484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 33/359 27/2000 NeoElection-PT-5-CTLFireability-2024-09 6186010 m, 178680 m/sec, 30896301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 38/359 31/2000 NeoElection-PT-5-CTLFireability-2024-09 7038556 m, 170509 m/sec, 35378281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 43/359 35/2000 NeoElection-PT-5-CTLFireability-2024-09 7901347 m, 172558 m/sec, 39968307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 48/359 38/2000 NeoElection-PT-5-CTLFireability-2024-09 8778130 m, 175356 m/sec, 44354379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 53/359 42/2000 NeoElection-PT-5-CTLFireability-2024-09 9608219 m, 166017 m/sec, 48764503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 58/359 45/2000 NeoElection-PT-5-CTLFireability-2024-09 10465963 m, 171548 m/sec, 53274592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 63/359 49/2000 NeoElection-PT-5-CTLFireability-2024-09 11278088 m, 162425 m/sec, 57554469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 68/359 52/2000 NeoElection-PT-5-CTLFireability-2024-09 12133820 m, 171146 m/sec, 62076875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 73/359 56/2000 NeoElection-PT-5-CTLFireability-2024-09 13051807 m, 183597 m/sec, 66653180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 78/359 60/2000 NeoElection-PT-5-CTLFireability-2024-09 13904250 m, 170488 m/sec, 71234034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 83/359 64/2000 NeoElection-PT-5-CTLFireability-2024-09 14777742 m, 174698 m/sec, 75817727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 88/359 67/2000 NeoElection-PT-5-CTLFireability-2024-09 15599479 m, 164347 m/sec, 80179405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 93/359 71/2000 NeoElection-PT-5-CTLFireability-2024-09 16490976 m, 178299 m/sec, 84795480 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 98/359 75/2000 NeoElection-PT-5-CTLFireability-2024-09 17383317 m, 178468 m/sec, 89295802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 103/359 78/2000 NeoElection-PT-5-CTLFireability-2024-09 18224210 m, 168178 m/sec, 93847219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 108/359 82/2000 NeoElection-PT-5-CTLFireability-2024-09 19071901 m, 169538 m/sec, 98294530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 113/359 86/2000 NeoElection-PT-5-CTLFireability-2024-09 19914379 m, 168495 m/sec, 102758966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 118/359 90/2000 NeoElection-PT-5-CTLFireability-2024-09 20821992 m, 181522 m/sec, 107503002 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 123/359 94/2000 NeoElection-PT-5-CTLFireability-2024-09 21694205 m, 174442 m/sec, 112223538 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 128/359 97/2000 NeoElection-PT-5-CTLFireability-2024-09 22516113 m, 164381 m/sec, 116782133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 133/359 101/2000 NeoElection-PT-5-CTLFireability-2024-09 23339899 m, 164757 m/sec, 121358979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 138/359 104/2000 NeoElection-PT-5-CTLFireability-2024-09 24166687 m, 165357 m/sec, 125948881 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 143/359 108/2000 NeoElection-PT-5-CTLFireability-2024-09 25050505 m, 176763 m/sec, 130572832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 148/359 111/2000 NeoElection-PT-5-CTLFireability-2024-09 25850424 m, 159983 m/sec, 135002678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 153/359 115/2000 NeoElection-PT-5-CTLFireability-2024-09 26636241 m, 157163 m/sec, 139373525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 158/359 118/2000 NeoElection-PT-5-CTLFireability-2024-09 27426119 m, 157975 m/sec, 143766106 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 163/359 122/2000 NeoElection-PT-5-CTLFireability-2024-09 28290830 m, 172942 m/sec, 148230282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 122
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 168/359 126/2000 NeoElection-PT-5-CTLFireability-2024-09 29190331 m, 179900 m/sec, 152776110 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 173/359 129/2000 NeoElection-PT-5-CTLFireability-2024-09 30089706 m, 179875 m/sec, 157231507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 178/359 133/2000 NeoElection-PT-5-CTLFireability-2024-09 31003116 m, 182682 m/sec, 161807734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 183/359 137/2000 NeoElection-PT-5-CTLFireability-2024-09 31829823 m, 165341 m/sec, 166154660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 188/359 141/2000 NeoElection-PT-5-CTLFireability-2024-09 32641137 m, 162262 m/sec, 170501444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 193/359 144/2000 NeoElection-PT-5-CTLFireability-2024-09 33415963 m, 154965 m/sec, 174655238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 198/359 148/2000 NeoElection-PT-5-CTLFireability-2024-09 34275701 m, 171947 m/sec, 179073774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 203/359 151/2000 NeoElection-PT-5-CTLFireability-2024-09 35098324 m, 164524 m/sec, 183505460 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 208/359 154/2000 NeoElection-PT-5-CTLFireability-2024-09 35906817 m, 161698 m/sec, 187810602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 213/359 158/2000 NeoElection-PT-5-CTLFireability-2024-09 36752091 m, 169054 m/sec, 192328159 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 218/359 162/2000 NeoElection-PT-5-CTLFireability-2024-09 37599957 m, 169573 m/sec, 196633722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 223/359 165/2000 NeoElection-PT-5-CTLFireability-2024-09 38405412 m, 161091 m/sec, 201003023 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 228/359 168/2000 NeoElection-PT-5-CTLFireability-2024-09 39183940 m, 155705 m/sec, 205177392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 233/359 172/2000 NeoElection-PT-5-CTLFireability-2024-09 40033038 m, 169819 m/sec, 209617584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 238/359 176/2000 NeoElection-PT-5-CTLFireability-2024-09 40869608 m, 167314 m/sec, 214052067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 243/359 179/2000 NeoElection-PT-5-CTLFireability-2024-09 41695151 m, 165108 m/sec, 218447869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 248/359 183/2000 NeoElection-PT-5-CTLFireability-2024-09 42504100 m, 161789 m/sec, 222758714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 253/359 187/2000 NeoElection-PT-5-CTLFireability-2024-09 43372308 m, 173641 m/sec, 227346288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 258/359 190/2000 NeoElection-PT-5-CTLFireability-2024-09 44164941 m, 158526 m/sec, 231696385 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 263/359 193/2000 NeoElection-PT-5-CTLFireability-2024-09 44939519 m, 154915 m/sec, 235984763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 268/359 197/2000 NeoElection-PT-5-CTLFireability-2024-09 45720109 m, 156118 m/sec, 240319761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 273/359 200/2000 NeoElection-PT-5-CTLFireability-2024-09 46529104 m, 161799 m/sec, 244792918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 278/359 204/2000 NeoElection-PT-5-CTLFireability-2024-09 47378825 m, 169944 m/sec, 249241807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 283/359 207/2000 NeoElection-PT-5-CTLFireability-2024-09 48148409 m, 153916 m/sec, 253509857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 288/359 210/2000 NeoElection-PT-5-CTLFireability-2024-09 48914624 m, 153243 m/sec, 257751885 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 293/359 214/2000 NeoElection-PT-5-CTLFireability-2024-09 49682232 m, 153521 m/sec, 262017363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 298/359 217/2000 NeoElection-PT-5-CTLFireability-2024-09 50498690 m, 163291 m/sec, 266489798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 303/359 221/2000 NeoElection-PT-5-CTLFireability-2024-09 51364302 m, 173122 m/sec, 271188409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 308/359 224/2000 NeoElection-PT-5-CTLFireability-2024-09 52170866 m, 161312 m/sec, 275890487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 313/359 228/2000 NeoElection-PT-5-CTLFireability-2024-09 52997752 m, 165377 m/sec, 280591725 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 318/359 231/2000 NeoElection-PT-5-CTLFireability-2024-09 53767483 m, 153946 m/sec, 284986584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 323/359 235/2000 NeoElection-PT-5-CTLFireability-2024-09 54565237 m, 159550 m/sec, 289554209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 328/359 238/2000 NeoElection-PT-5-CTLFireability-2024-09 55404493 m, 167851 m/sec, 294299569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 333/359 242/2000 NeoElection-PT-5-CTLFireability-2024-09 56220675 m, 163236 m/sec, 298946307 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 242
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 338/359 245/2000 NeoElection-PT-5-CTLFireability-2024-09 56995573 m, 154979 m/sec, 303610306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 343/359 248/2000 NeoElection-PT-5-CTLFireability-2024-09 57754283 m, 151742 m/sec, 308239381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 348/359 252/2000 NeoElection-PT-5-CTLFireability-2024-09 58523305 m, 153804 m/sec, 312833963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 353/359 255/2000 NeoElection-PT-5-CTLFireability-2024-09 59233845 m, 142108 m/sec, 317083096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 255
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 358/359 258/2000 NeoElection-PT-5-CTLFireability-2024-09 59993283 m, 151887 m/sec, 321680197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 258
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 32 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-15: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 NeoElection-PT-5-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 NeoElection-PT-5-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 3235 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 5/359 5/5 NeoElection-PT-5-CTLFireability-2024-09 1031066 m, -11792443 m/sec, 4812706 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 32 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 NeoElection-PT-5-CTLFireability-2024-14
[[35mlola[0m][I] time limit : 403 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 276
[[35mlola[0m][I] fired transitions : 827
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 NeoElection-PT-5-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 460 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 276
[[35mlola[0m][I] fired transitions : 275
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 NeoElection-PT-5-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 537 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for NeoElection-PT-5-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 276
[[35mlola[0m][I] fired transitions : 276
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 NeoElection-PT-5-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 645 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 5/645 12/2000 NeoElection-PT-5-CTLFireability-2024-07 2679900 m, 535980 m/sec, 4901572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 10/645 23/2000 NeoElection-PT-5-CTLFireability-2024-07 5236158 m, 511251 m/sec, 9680995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 15/645 34/2000 NeoElection-PT-5-CTLFireability-2024-07 7640249 m, 480818 m/sec, 14271645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 20/645 42/2000 NeoElection-PT-5-CTLFireability-2024-07 9619425 m, 395835 m/sec, 18833366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 25/645 52/2000 NeoElection-PT-5-CTLFireability-2024-07 11783986 m, 432912 m/sec, 23280241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 313
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 30/645 61/2000 NeoElection-PT-5-CTLFireability-2024-07 14002461 m, 443695 m/sec, 27615453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 35/645 70/2000 NeoElection-PT-5-CTLFireability-2024-07 16029881 m, 405484 m/sec, 31640383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 40/645 79/2000 NeoElection-PT-5-CTLFireability-2024-07 18319185 m, 457860 m/sec, 36085726 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 45/645 90/2000 NeoElection-PT-5-CTLFireability-2024-07 20698033 m, 475769 m/sec, 40599969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 50/645 101/2000 NeoElection-PT-5-CTLFireability-2024-07 23198913 m, 500176 m/sec, 45280418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 362
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 55/645 111/2000 NeoElection-PT-5-CTLFireability-2024-07 25621903 m, 484598 m/sec, 49882164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 60/645 120/2000 NeoElection-PT-5-CTLFireability-2024-07 27680875 m, 411794 m/sec, 54403955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 65/645 129/2000 NeoElection-PT-5-CTLFireability-2024-07 29753643 m, 414553 m/sec, 58776034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 390
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 70/645 138/2000 NeoElection-PT-5-CTLFireability-2024-07 31920419 m, 433355 m/sec, 63032927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 399
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 75/645 146/2000 NeoElection-PT-5-CTLFireability-2024-07 33873869 m, 390690 m/sec, 66964085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 80/645 156/2000 NeoElection-PT-5-CTLFireability-2024-07 36132949 m, 451816 m/sec, 71367793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 85/645 166/2000 NeoElection-PT-5-CTLFireability-2024-07 38481074 m, 469625 m/sec, 75896718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 90/645 176/2000 NeoElection-PT-5-CTLFireability-2024-07 40626854 m, 429156 m/sec, 80372618 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 437
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 95/645 185/2000 NeoElection-PT-5-CTLFireability-2024-07 42740641 m, 422757 m/sec, 84621024 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 446
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 100/645 195/2000 NeoElection-PT-5-CTLFireability-2024-07 44988148 m, 449501 m/sec, 89133755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 105/645 203/2000 NeoElection-PT-5-CTLFireability-2024-07 47023672 m, 407104 m/sec, 93337382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 110/645 213/2000 NeoElection-PT-5-CTLFireability-2024-07 49232875 m, 441840 m/sec, 97729071 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 474
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 115/645 222/2000 NeoElection-PT-5-CTLFireability-2024-07 51214297 m, 396284 m/sec, 101925519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 483
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 120/645 231/2000 NeoElection-PT-5-CTLFireability-2024-07 53307136 m, 418567 m/sec, 106171531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 492
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 125/645 239/2000 NeoElection-PT-5-CTLFireability-2024-07 55247156 m, 388004 m/sec, 110316700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 500
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 130/645 247/2000 NeoElection-PT-5-CTLFireability-2024-07 57179373 m, 386443 m/sec, 114707394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 135/645 255/2000 NeoElection-PT-5-CTLFireability-2024-07 58877314 m, 339588 m/sec, 118914843 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 140/645 262/2000 NeoElection-PT-5-CTLFireability-2024-07 60539852 m, 332507 m/sec, 123034209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 523
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 145/645 269/2000 NeoElection-PT-5-CTLFireability-2024-07 62146602 m, 321350 m/sec, 126900410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 530
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 150/645 278/2000 NeoElection-PT-5-CTLFireability-2024-07 64171894 m, 405058 m/sec, 131140826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 539
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 155/645 286/2000 NeoElection-PT-5-CTLFireability-2024-07 66082880 m, 382197 m/sec, 135272303 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 547
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 160/645 294/2000 NeoElection-PT-5-CTLFireability-2024-07 67922385 m, 367901 m/sec, 139188853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 555
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 165/645 302/2000 NeoElection-PT-5-CTLFireability-2024-07 69732768 m, 362076 m/sec, 143037520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 170/645 310/2000 NeoElection-PT-5-CTLFireability-2024-07 71660042 m, 385454 m/sec, 147100617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 571
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 175/645 317/2000 NeoElection-PT-5-CTLFireability-2024-07 73412690 m, 350529 m/sec, 150721005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 578
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 180/645 324/2000 NeoElection-PT-5-CTLFireability-2024-07 75065171 m, 330496 m/sec, 154418390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 585
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 185/645 331/2000 NeoElection-PT-5-CTLFireability-2024-07 76683688 m, 323703 m/sec, 157909704 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 592
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 190/645 339/2000 NeoElection-PT-5-CTLFireability-2024-07 78602766 m, 383815 m/sec, 161891871 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 600
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 195/645 348/2000 NeoElection-PT-5-CTLFireability-2024-07 80675841 m, 414615 m/sec, 166169117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 609
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 200/645 357/2000 NeoElection-PT-5-CTLFireability-2024-07 82589219 m, 382675 m/sec, 170355096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 618
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 205/645 364/2000 NeoElection-PT-5-CTLFireability-2024-07 84398682 m, 361892 m/sec, 174153908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 625
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 210/645 374/2000 NeoElection-PT-5-CTLFireability-2024-07 86522788 m, 424821 m/sec, 178413494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 635
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 215/645 383/2000 NeoElection-PT-5-CTLFireability-2024-07 88791470 m, 453736 m/sec, 182817929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 644
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 220/645 393/2000 NeoElection-PT-5-CTLFireability-2024-07 91019751 m, 445656 m/sec, 187177421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 654
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-10: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-12: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-13: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mNeoElection-PT-5-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mNeoElection-PT-5-CTLFireability-2024-15: LTL/CTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-03: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-04: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] NeoElection-PT-5-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 26 CTL EXCL 225/645 402/2000 NeoElection-PT-5-CTLFireability-2024-07 93201407 m, 436331 m/sec, 191508446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 663
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="NeoElection-PT-5"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is NeoElection-PT-5, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353500522"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/NeoElection-PT-5.tgz
mv NeoElection-PT-5 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;