About the Execution of LoLA for Murphy-COL-D3N050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16209.407 | 239963.00 | 245645.00 | 695.70 | FFF??FFF??TF??TT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353000268.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Murphy-COL-D3N050, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353000268
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 492K
-rw-r--r-- 1 mcc users 6.6K Apr 11 23:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Apr 11 23:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Apr 11 23:03 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Apr 11 23:03 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 6 10:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 6 10:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 6 10:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 6 10:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 23:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 162K Apr 11 23:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Apr 11 23:10 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 61K Apr 11 23:10 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 6 10:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 20K May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-00
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-01
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-02
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-03
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-04
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-05
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-06
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-07
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-08
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-09
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-10
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-11
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-12
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-13
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-14
FORMULA_NAME Murphy-COL-D3N050-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717070670854
FORMULA Murphy-COL-D3N050-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Murphy-COL-D3N050-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717070910817
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/CNST) for 7 Murphy-COL-D3N050-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/CNST) for Murphy-COL-D3N050-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 24, Transitions: 28
[[35mlola[0m][W] findlow criterion violated for transition 3
[[35mlola[0m][W] findlow criterion violated for transition 0
[[35mlola[0m][W] findlow criterion violated for 4 clusters
[[35mlola[0m][I] Time for checking findlow: 0
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 7 Murphy-COL-D3N050-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 30 Murphy-COL-D3N050-LTLFireability-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/SRCH) for 49 Murphy-COL-D3N050-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/SRCH) for 40 Murphy-COL-D3N050-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for Murphy-COL-D3N050-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for Murphy-COL-D3N050-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 31
[[35mlola[0m][I] fired transitions : 31
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/SRCH) for Murphy-COL-D3N050-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 31
[[35mlola[0m][I] fired transitions : 31
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/SRCH) for Murphy-COL-D3N050-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 215
[[35mlola[0m][I] fired transitions : 215
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 14 Murphy-COL-D3N050-LTLFireability-02
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 77 (type FNDP) for 0 Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 0 Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[*** LOG ERROR #0001 ***] [2024-05-30 12:04:31] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for Murphy-COL-D3N050-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 125
[[35mlola[0m][I] fired transitions : 194
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 79 (type EXCL) for 0 Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 84 (type EQUN) for 17 Murphy-COL-D3N050-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 79 (type EXCL) for Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 4
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 77 (type FNDP) for Murphy-COL-D3N050-LTLFireability-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 78 (type EQUN) for Murphy-COL-D3N050-LTLFireability-00 (obsolete)
[[35mlola[0m][I] LAUNCH task # 81 (type EXCL) for 17 Murphy-COL-D3N050-LTLFireability-03
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 81 (type EXCL) for Murphy-COL-D3N050-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 84 (type EQUN) for Murphy-COL-D3N050-LTLFireability-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 30 Murphy-COL-D3N050-LTLFireability-06
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 89 (type EQUN) for 69 Murphy-COL-D3N050-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 94 (type EQUN) for 66 Murphy-COL-D3N050-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for Murphy-COL-D3N050-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 22
[[35mlola[0m][I] fired transitions : 29
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 49 Murphy-COL-D3N050-LTLFireability-11
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for Murphy-COL-D3N050-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 Murphy-COL-D3N050-LTLFireability-10
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 89 (type EQUN) for Murphy-COL-D3N050-LTLFireability-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for Murphy-COL-D3N050-LTLFireability-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 Murphy-COL-D3N050-LTLFireability-07
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for Murphy-COL-D3N050-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 Murphy-COL-D3N050-LTLFireability-05
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for Murphy-COL-D3N050-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 91 (type EXCL) for 66 Murphy-COL-D3N050-LTLFireability-14
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 91 (type EXCL) for Murphy-COL-D3N050-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 94 (type EQUN) for Murphy-COL-D3N050-LTLFireability-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 86 (type EXCL) for 69 Murphy-COL-D3N050-LTLFireability-15
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 86 (type EXCL) for Murphy-COL-D3N050-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 63 Murphy-COL-D3N050-LTLFireability-13
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type FNDP) for Murphy-COL-D3N050-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 84 (type EQUN) for Murphy-COL-D3N050-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 94 (type EQUN) for Murphy-COL-D3N050-LTLFireability-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 5/599 13/2000 Murphy-COL-D3N050-LTLFireability-13 1962890 m, 392578 m/sec, 4236623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 10/599 25/2000 Murphy-COL-D3N050-LTLFireability-13 3740644 m, 355550 m/sec, 8182839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 15/599 37/2000 Murphy-COL-D3N050-LTLFireability-13 5491062 m, 350083 m/sec, 12078830 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 20/599 48/2000 Murphy-COL-D3N050-LTLFireability-13 7199164 m, 341620 m/sec, 15897149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 25/599 59/2000 Murphy-COL-D3N050-LTLFireability-13 8901970 m, 340561 m/sec, 19743642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 30/599 70/2000 Murphy-COL-D3N050-LTLFireability-13 10641200 m, 347846 m/sec, 23674556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 35/599 81/2000 Murphy-COL-D3N050-LTLFireability-13 12338821 m, 339524 m/sec, 27519530 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 40/599 93/2000 Murphy-COL-D3N050-LTLFireability-13 14048060 m, 341847 m/sec, 31422955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 45/599 104/2000 Murphy-COL-D3N050-LTLFireability-13 15766129 m, 343613 m/sec, 35307225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 50/599 115/2000 Murphy-COL-D3N050-LTLFireability-13 17443541 m, 335482 m/sec, 39147880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 55/599 126/2000 Murphy-COL-D3N050-LTLFireability-13 19129185 m, 337128 m/sec, 42985405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 60/599 137/2000 Murphy-COL-D3N050-LTLFireability-13 20805079 m, 335178 m/sec, 46792795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 65/599 148/2000 Murphy-COL-D3N050-LTLFireability-13 22452692 m, 329522 m/sec, 50568882 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 70/599 158/2000 Murphy-COL-D3N050-LTLFireability-13 24097050 m, 328871 m/sec, 54325409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 75/599 169/2000 Murphy-COL-D3N050-LTLFireability-13 25746910 m, 329972 m/sec, 58091912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 80/599 180/2000 Murphy-COL-D3N050-LTLFireability-13 27394682 m, 329554 m/sec, 61871140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 85/599 191/2000 Murphy-COL-D3N050-LTLFireability-13 28993599 m, 319783 m/sec, 65565115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 90/599 201/2000 Murphy-COL-D3N050-LTLFireability-13 30583761 m, 318032 m/sec, 69235264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 95/599 212/2000 Murphy-COL-D3N050-LTLFireability-13 32214984 m, 326244 m/sec, 72963073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 100/599 222/2000 Murphy-COL-D3N050-LTLFireability-13 33808551 m, 318713 m/sec, 76656707 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 105/599 232/2000 Murphy-COL-D3N050-LTLFireability-13 35406244 m, 319538 m/sec, 80345930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 110/599 243/2000 Murphy-COL-D3N050-LTLFireability-13 36965880 m, 311927 m/sec, 83950572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 115/599 253/2000 Murphy-COL-D3N050-LTLFireability-13 38558111 m, 318446 m/sec, 87614925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 120/599 264/2000 Murphy-COL-D3N050-LTLFireability-13 40161126 m, 320603 m/sec, 91295107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 264
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 125/599 274/2000 Murphy-COL-D3N050-LTLFireability-13 41725743 m, 312923 m/sec, 94907188 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 130/599 284/2000 Murphy-COL-D3N050-LTLFireability-13 43323085 m, 319468 m/sec, 98559857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 135/599 295/2000 Murphy-COL-D3N050-LTLFireability-13 44919193 m, 319221 m/sec, 102236940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 140/599 305/2000 Murphy-COL-D3N050-LTLFireability-13 46493818 m, 314925 m/sec, 105894685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 305
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 145/599 315/2000 Murphy-COL-D3N050-LTLFireability-13 48050842 m, 311404 m/sec, 109515428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 150/599 325/2000 Murphy-COL-D3N050-LTLFireability-13 49595323 m, 308896 m/sec, 113107918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 155/599 336/2000 Murphy-COL-D3N050-LTLFireability-13 51165078 m, 313951 m/sec, 116732296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 160/599 346/2000 Murphy-COL-D3N050-LTLFireability-13 52711856 m, 309355 m/sec, 120297340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 165/599 356/2000 Murphy-COL-D3N050-LTLFireability-13 54275455 m, 312719 m/sec, 123913578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 170/599 366/2000 Murphy-COL-D3N050-LTLFireability-13 55827634 m, 310435 m/sec, 127478570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 175/599 376/2000 Murphy-COL-D3N050-LTLFireability-13 57317842 m, 298041 m/sec, 130977863 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 180/599 386/2000 Murphy-COL-D3N050-LTLFireability-13 58848466 m, 306124 m/sec, 134511816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 185/599 396/2000 Murphy-COL-D3N050-LTLFireability-13 60384423 m, 307191 m/sec, 138046306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 396
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 190/599 406/2000 Murphy-COL-D3N050-LTLFireability-13 61941543 m, 311424 m/sec, 141627655 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 195/599 416/2000 Murphy-COL-D3N050-LTLFireability-13 63445606 m, 300812 m/sec, 145135775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 416
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 200/599 426/2000 Murphy-COL-D3N050-LTLFireability-13 64974773 m, 305833 m/sec, 148681712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 205/599 436/2000 Murphy-COL-D3N050-LTLFireability-13 66519147 m, 308874 m/sec, 152254749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 210/599 446/2000 Murphy-COL-D3N050-LTLFireability-13 68030869 m, 302344 m/sec, 155763267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 446
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 215/599 456/2000 Murphy-COL-D3N050-LTLFireability-13 69548783 m, 303582 m/sec, 159308551 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 220/599 466/2000 Murphy-COL-D3N050-LTLFireability-13 71086095 m, 307462 m/sec, 162866669 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 225/599 476/2000 Murphy-COL-D3N050-LTLFireability-13 72612687 m, 305318 m/sec, 166393426 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 476
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 230/599 486/2000 Murphy-COL-D3N050-LTLFireability-13 74129540 m, 303370 m/sec, 169910630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 486
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-00: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-01: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-06: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-10: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mMurphy-COL-D3N050-LTLFireability-11: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-14: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mMurphy-COL-D3N050-LTLFireability-15: F true state space / EG[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-03: CONJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] Murphy-COL-D3N050-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 64 LTL EXCL 235/599 496/2000 Murphy-COL-D3N050-LTLFireability-13 75641079 m, 302307 m/sec, 173417047 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 405 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Murphy-COL-D3N050"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Murphy-COL-D3N050, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353000268"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Murphy-COL-D3N050.tgz
mv Murphy-COL-D3N050 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;