MCC'2024- Execution of r247-tall-171654353000260

About the Execution of LoLA for Murphy-COL-D2N100

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16208.831	284484.00	230594.00	1377.60	[undef]	Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r247-tall-171654353000260.qcow2',
Waiting for the VM to be ready (probing ssh)
.........................................................
===================================
Generated by BenchKit 2-5568
Executing tool lola
Input is Murphy-COL-D2N100, examination is LTLFireabi
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654353000260
=========================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 7.6K Apr 11 22:59 CTLCardinality.t
-rw-r--r-- 1 mcc users 89K Apr 11 22:59 CTLCardinality.x
-rw-r--r-- 1 mcc users 4.7K Apr 11 22:57 CTLFireability.t
-rw-r--r-- 1 mcc users 42K Apr 11 22:57 CTLFireability.x
-rw-r--r-- 1 mcc users 3.3K May 6 10:01 LTLCardinality.t
-rw-r--r-- 1 mcc users 25K May 6 10:01 LTLCardinality.x
-rw-r--r-- 1 mcc users 2.1K May 6 10:01 LTLFireability.t
-rw-r--r-- 1 mcc users 19K May 6 10:01 LTLFireability.x
-rw-r--r-- 1 mcc users 14K Apr 11 23:03 ReachabilityCard
-rw-r--r-- 1 mcc users 157K Apr 11 23:03 ReachabilityCard
-rw-r--r-- 1 mcc users 6.1K Apr 11 23:02 ReachabilityFire
-rw-r--r-- 1 mcc users 52K Apr 11 23:02 ReachabilityFire
-rw-r--r-- 1 mcc users 1.6K May 6 10:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 6 10:01 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:43 equiv_pt
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 5 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 20K May 18 16:43 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-00
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-01
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-02
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-03
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-04
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-05
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-06
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-07
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-08
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-09
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-10
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-11
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-12
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-13
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-14
FORMULA_NAME Murphy-COL-D2N100-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717070284796

BK_STOP 1717070569280

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds
[[35mlola[0m][W] [1m[33munknown unit in memory
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format
[[35mlola[0m][I] reading [1m[34mformula[0m
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] nonmoderate token usage
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 18, Transitions: 21
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Rule S: 0 transitions removed,0
[[35mlola[0m][I] LAUNCH task # 18 (type CNST)
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL)
[[35mlola[0m][I] time limit : 163 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 18 (type CNST)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 48 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL)
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL)
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL)
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL)
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL)
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 20 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL)
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL)
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL)
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL)
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL)
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL)
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][W] findlow criterion violated
[[35mlola[0m][I] Time for checking findlow: 0
[[35mlola[0m][I] FINISHED task # 62 (type EXCL)
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings :
[[35mlola[0m][I] fired transitions :
[[35mlola[0m][I] time used :
[[35mlola[0m][I] memory pages used :
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL)
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 5/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 10/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 15/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 20/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 25/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
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[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
[[35mlola[0m][.] 59 LTL EXCL 30/719
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs.
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-01:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-02:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-03:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-04:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-05:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-06:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-07:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-08:
[[35mlola[0m][.] [1m[32mMurphy-COL-D2N100-LTLFireability-09:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-11:
[[35mlola[0m][.] [1m[31mMurphy-COL-D2N100-LTLFireability-15:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-00:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-10:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-12:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-13:
[[35mlola[0m][.] Murphy-COL-D2N100-LTLFireability-14:
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE
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[[35mlola[0m][.]
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================================== lity ============ xt ml xt ml xt ml xt ml inality.txt inality.xml ability.txt ability.xml (invocation template) text file) at most ([1m[36m--timelimit[0m) specification: using default[0m [4m[34mmodel.pnml[0m [0m) [4m[34mmodel.pnml[0m ([1m[36m--xmlformula[0m) from [4m[34mLTLFireability.xml[0m for 15 Murphy-COL-D2N100-LTLFireability-05 for Murphy-COL-D2N100-LTLFireability-05 for transition 3 for transition 0 places removed for 15 Murphy-COL-D2N100-LTLFireability-05 for 45 Murphy-COL-D2N100-LTLFireability-11 for Murphy-COL-D2N100-LTLFireability-05 for Murphy-COL-D2N100-LTLFireability-11 18504 33559 0 1 for 39 Murphy-COL-D2N100-LTLFireability-09 for Murphy-COL-D2N100-LTLFireability-09 1 0 1 for 28 Murphy-COL-D2N100-LTLFireability-08 for Murphy-COL-D2N100-LTLFireability-08 18516 33577 0 1 for 25 Murphy-COL-D2N100-LTLFireability-07 for Murphy-COL-D2N100-LTLFireability-07 55 87 0 1 for 22 Murphy-COL-D2N100-LTLFireability-06 for Murphy-COL-D2N100-LTLFireability-06 1 0 1 for 15 Murphy-COL-D2N100-LTLFireability-05 for Murphy-COL-D2N100-LTLFireability-05 31 43 0 1 for 12 Murphy-COL-D2N100-LTLFireability-04 for Murphy-COL-D2N100-LTLFireability-04 5 5 0 1 for 9 Murphy-COL-D2N100-LTLFireability-03 for Murphy-COL-D2N100-LTLFireability-03 1 0 1 for 6 Murphy-COL-D2N100-LTLFireability-02 for Murphy-COL-D2N100-LTLFireability-02 6 6 0 1 for 3 Murphy-COL-D2N100-LTLFireability-01 for Murphy-COL-D2N100-LTLFireability-01 37404 67840 0 1 for 61 Murphy-COL-D2N100-LTLFireability-15 for 4 clusters for Murphy-COL-D2N100-LTLFireability-15 44029 59071 0 1 for 58 Murphy-COL-D2N100-LTLFireability-14 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 20/2000 Murphy-COL-D2N100-LTLFireability-14 2953284 m, 590656 m/sec, 6021115 t fired, . in use: 20 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 38/2000 Murphy-COL-D2N100-LTLFireability-14 5809203 m, 571183 m/sec, 11993381 t fired, . Pages in use: 38 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 56/2000 Murphy-COL-D2N100-LTLFireability-14 8504892 m, 539137 m/sec, 17673723 t fired, . Pages in use: 56 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 73/2000 Murphy-COL-D2N100-LTLFireability-14 11202064 m, 539434 m/sec, 23369390 t fired, . Pages in use: 73 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 91/2000 Murphy-COL-D2N100-LTLFireability-14 13872089 m, 534005 m/sec, 29035646 t fired, . Pages in use: 91 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 107/2000 Murphy-COL-D2N100-LTLFireability-14 16387607 m, 503103 m/sec, 34383396 t fired, . Pages in use: 107 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 123/2000 Murphy-COL-D2N100-LTLFireability-14 18860358 m, 494550 m/sec, 39656016 t fired, . Pages in use: 123 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 139/2000 Murphy-COL-D2N100-LTLFireability-14 21393739 m, 506676 m/sec, 45043967 t fired, . Pages in use: 139 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 156/2000 Murphy-COL-D2N100-LTLFireability-14 23892324 m, 499717 m/sec, 50377409 t fired, . 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Pages in use: 172 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 187/2000 Murphy-COL-D2N100-LTLFireability-14 28749931 m, 475641 m/sec, 60762761 t fired, . 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Pages in use: 259 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 275/2000 Murphy-COL-D2N100-LTLFireability-14 42256577 m, 476847 m/sec, 89734832 t fired, . Pages in use: 275 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 290/2000 Murphy-COL-D2N100-LTLFireability-14 44533845 m, 455453 m/sec, 94621507 t fired, . Pages in use: 290 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 303/2000 Murphy-COL-D2N100-LTLFireability-14 46588790 m, 410989 m/sec, 99057830 t fired, . Pages in use: 303 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 317/2000 Murphy-COL-D2N100-LTLFireability-14 48763730 m, 434988 m/sec, 103716306 t fired, . Pages in use: 317 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 331/2000 Murphy-COL-D2N100-LTLFireability-14 50839921 m, 415238 m/sec, 108203230 t fired, . Pages in use: 331 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 345/2000 Murphy-COL-D2N100-LTLFireability-14 53088192 m, 449654 m/sec, 113019437 t fired, . Pages in use: 345 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 359/2000 Murphy-COL-D2N100-LTLFireability-14 55208381 m, 424037 m/sec, 117606140 t fired, . Pages in use: 359 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 373/2000 Murphy-COL-D2N100-LTLFireability-14 57424093 m, 443142 m/sec, 122359318 t fired, . Pages in use: 373 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 387/2000 Murphy-COL-D2N100-LTLFireability-14 59497657 m, 414712 m/sec, 126842438 t fired, . Pages in use: 387 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 402/2000 Murphy-COL-D2N100-LTLFireability-14 61758386 m, 452145 m/sec, 131704590 t fired, . Pages in use: 402 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 416/2000 Murphy-COL-D2N100-LTLFireability-14 63964589 m, 441240 m/sec, 136463418 t fired, . Pages in use: 416 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 430/2000 Murphy-COL-D2N100-LTLFireability-14 66132468 m, 433575 m/sec, 141168498 t fired, . Pages in use: 430 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 446/2000 Murphy-COL-D2N100-LTLFireability-14 68558557 m, 485217 m/sec, 146367031 t fired, . Pages in use: 446 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 460/2000 Murphy-COL-D2N100-LTLFireability-14 70675337 m, 423356 m/sec, 150964214 t fired, . Pages in use: 460 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 474/2000 Murphy-COL-D2N100-LTLFireability-14 72872458 m, 439424 m/sec, 155676223 t fired, . Pages in use: 474 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 487/2000 Murphy-COL-D2N100-LTLFireability-14 74890189 m, 403546 m/sec, 160040186 t fired, . Pages in use: 487 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 500/2000 Murphy-COL-D2N100-LTLFireability-14 76861835 m, 394329 m/sec, 164335068 t fired, . Pages in use: 500 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 514/2000 Murphy-COL-D2N100-LTLFireability-14 79120324 m, 451697 m/sec, 169165581 t fired, . Pages in use: 514 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 528/2000 Murphy-COL-D2N100-LTLFireability-14 81163751 m, 408685 m/sec, 173595328 t fired, . Pages in use: 528 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 541/2000 Murphy-COL-D2N100-LTLFireability-14 83215741 m, 410398 m/sec, 178068641 t fired, . Pages in use: 541 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 557/2000 Murphy-COL-D2N100-LTLFireability-14 85684215 m, 493694 m/sec, 183350319 t fired, . Pages in use: 557 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 571/2000 Murphy-COL-D2N100-LTLFireability-14 87806935 m, 424544 m/sec, 187960345 t fired, . Pages in use: 571 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 584/2000 Murphy-COL-D2N100-LTLFireability-14 89894805 m, 417574 m/sec, 192506978 t fired, . Pages in use: 584 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 599/2000 Murphy-COL-D2N100-LTLFireability-14 92144769 m, 449992 m/sec, 197322528 t fired, . Pages in use: 599 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 612/2000 Murphy-COL-D2N100-LTLFireability-14 94210556 m, 413157 m/sec, 201807703 t fired, . Pages in use: 612 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 626/2000 Murphy-COL-D2N100-LTLFireability-14 96258347 m, 409558 m/sec, 206272468 t fired, . Pages in use: 626 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 641/2000 Murphy-COL-D2N100-LTLFireability-14 98579030 m, 464136 m/sec, 211245578 t fired, . Pages in use: 641 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 654/2000 Murphy-COL-D2N100-LTLFireability-14 100588595 m, 401913 m/sec, 215602210 t fired, . Pages in use: 654 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 657/2000 Murphy-COL-D2N100-LTLFireability-14 101039570 m, 90195 m/sec, 216580850 t fired, . Pages in use: 657 CATEGORY VALUE PRODUCED BY[0m LTL false LTL model checker[0m LTL false LTL model checker[0m LTL true LTL model checker[0m LTL false LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL true LTL model checker[0m CONJ false LTL model checker[0m LTL false LTL model checker[0m CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 1 0 0 1 0 0 0 LTL 0 0 1 0 1 0 0 0 TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m 657/2000 Murphy-COL-D2N100-LTLFireability-14 101042281 m, 542 m/sec, 216587006 t fired, . Pages in use: 657 $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Murphy-COL-D2N100"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is Murphy-COL-D2N100, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654353000260"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Murphy-COL-D2N100.tgz
mv Murphy-COL-D2N100 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;