About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S24C05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16194.071 | 230730.00 | 655411.00 | 793.60 | T??????F???????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r247-tall-171654352600084.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S24C05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r247-tall-171654352600084
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 12M
-rw-r--r-- 1 mcc users 15K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.8K May 19 07:11 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 16:05 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K May 19 07:23 LTLFireability.txt
-rw-r--r-- 1 mcc users 22K May 19 18:36 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 12 06:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 120K Apr 12 06:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.4K May 19 07:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.6K May 19 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:43 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:43 instance
-rw-r--r-- 1 mcc users 6 May 18 16:43 iscolored
-rw-r--r-- 1 mcc users 12M May 18 16:43 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14
FORMULA_NAME MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717056395919
FORMULA MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717056626649
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 29 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 34 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 39 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 44 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 49 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 54 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 59 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 36 (type CNST) for 33 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 36 (type CNST) for MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 64 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 69 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 74 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 79 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 84 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 89 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 94 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 99 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 104 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 109 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 114 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-05-30 08:08:34] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 119 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 124 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 129 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 134 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 139 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 144 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 149 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 154 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 159 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 164 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 169 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 174 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 179 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 184 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 189 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 6 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 6 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 2
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 18 (type EXCL) for 17 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03
[[35mlola[0m][I] time limit : 213 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 3/213 1/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 5982 m, 1196 m/sec, 7120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 194 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 8/213 3/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 24208 m, 3645 m/sec, 28815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 199 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 13/213 5/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 42525 m, 3663 m/sec, 50652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 204 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 18/213 6/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 60181 m, 3531 m/sec, 71687 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 209 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 23/213 8/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 77895 m, 3542 m/sec, 92795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 214 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 28/213 10/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 93029 m, 3026 m/sec, 110837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 219 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 5 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 33/213 11/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 113084 m, 4011 m/sec, 134735 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 224 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-00: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mMultiCrashLeafsetExtension-PT-S24C05-LTLFireability-07: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-02: CONJ 0 1 0 0 5 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 18 LTL EXCL 38/213 13/2000 MultiCrashLeafsetExtension-PT-S24C05-LTLFireability-03 131521 m, 3687 m/sec, 156708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 229 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S24C05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S24C05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r247-tall-171654352600084"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S24C05.tgz
mv MultiCrashLeafsetExtension-PT-S24C05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;