About the Execution of LoLA for MAPK-PT-00320
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.712 | 256916.00 | 260655.00 | 981.90 | ????????T???T?F? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r225-tall-171649614100450.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is MAPK-PT-00320, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649614100450
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:52 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:52 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:22 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 19 18:35 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 96K Apr 13 07:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Apr 13 07:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Apr 13 07:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:52 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:52 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 25K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-00
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-01
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-02
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-03
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-04
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-05
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-06
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-07
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-08
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-09
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-10
FORMULA_NAME MAPK-PT-00320-CTLFireability-2024-11
FORMULA_NAME MAPK-PT-00320-CTLFireability-2023-12
FORMULA_NAME MAPK-PT-00320-CTLFireability-2023-13
FORMULA_NAME MAPK-PT-00320-CTLFireability-2023-14
FORMULA_NAME MAPK-PT-00320-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717074699182
FORMULA MAPK-PT-00320-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00320-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00320-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717074956098
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 MAPK-PT-00320-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 180 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 37 (type EXCL) for MAPK-PT-00320-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 MAPK-PT-00320-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for MAPK-PT-00320-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 MAPK-PT-00320-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 52 (type EQUN) for 15 MAPK-PT-00320-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 15 MAPK-PT-00320-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 24 MAPK-PT-00320-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 52 (type EQUN) for MAPK-PT-00320-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 24 MAPK-PT-00320-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for MAPK-PT-00320-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 56 (type EQUN) for MAPK-PT-00320-CTLFireability-2024-08 (obsolete)
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for MAPK-PT-00320-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for MAPK-PT-00320-CTLFireability-2024-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for MAPK-PT-00320-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 203020
[[35mlola[0m][I] fired transitions : 829188
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 MAPK-PT-00320-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for MAPK-PT-00320-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 MAPK-PT-00320-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 40 (type EXCL) for MAPK-PT-00320-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 MAPK-PT-00320-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for MAPK-PT-00320-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 16
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 MAPK-PT-00320-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for MAPK-PT-00320-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 MAPK-PT-00320-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 450 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for MAPK-PT-00320-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 MAPK-PT-00320-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/514 15/2000 MAPK-PT-00320-CTLFireability-2024-06 3302099 m, 660419 m/sec, 7381270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/514 36/2000 MAPK-PT-00320-CTLFireability-2024-06 8195766 m, 978733 m/sec, 14415427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/514 60/2000 MAPK-PT-00320-CTLFireability-2024-06 13782360 m, 1117318 m/sec, 20611715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/514 80/2000 MAPK-PT-00320-CTLFireability-2024-06 18579723 m, 959472 m/sec, 26751838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/514 99/2000 MAPK-PT-00320-CTLFireability-2024-06 23072179 m, 898491 m/sec, 32482795 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/514 118/2000 MAPK-PT-00320-CTLFireability-2024-06 27533426 m, 892249 m/sec, 38166925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/514 138/2000 MAPK-PT-00320-CTLFireability-2024-06 32362602 m, 965835 m/sec, 43561419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/514 158/2000 MAPK-PT-00320-CTLFireability-2024-06 37115493 m, 950578 m/sec, 48833336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/514 179/2000 MAPK-PT-00320-CTLFireability-2024-06 42035638 m, 984029 m/sec, 54295829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/514 200/2000 MAPK-PT-00320-CTLFireability-2024-06 47008396 m, 994551 m/sec, 59802384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/514 219/2000 MAPK-PT-00320-CTLFireability-2024-06 51557573 m, 909835 m/sec, 64798479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/514 235/2000 MAPK-PT-00320-CTLFireability-2024-06 55234537 m, 735392 m/sec, 68791911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/514 248/2000 MAPK-PT-00320-CTLFireability-2024-06 58335367 m, 620166 m/sec, 72792929 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/514 263/2000 MAPK-PT-00320-CTLFireability-2024-06 61907520 m, 714430 m/sec, 77621438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 75/514 278/2000 MAPK-PT-00320-CTLFireability-2024-06 65484268 m, 715349 m/sec, 82775853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 80/514 291/2000 MAPK-PT-00320-CTLFireability-2024-06 68511613 m, 605469 m/sec, 86082535 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 85/514 304/2000 MAPK-PT-00320-CTLFireability-2024-06 71634736 m, 624624 m/sec, 89523048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 90/514 318/2000 MAPK-PT-00320-CTLFireability-2024-06 74825552 m, 638163 m/sec, 93032198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 318
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 95/514 331/2000 MAPK-PT-00320-CTLFireability-2024-06 78037810 m, 642451 m/sec, 96540923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 331
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 100/514 343/2000 MAPK-PT-00320-CTLFireability-2024-06 80974140 m, 587266 m/sec, 100191349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 105/514 354/2000 MAPK-PT-00320-CTLFireability-2024-06 83637711 m, 532714 m/sec, 103555486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 354
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 110/514 366/2000 MAPK-PT-00320-CTLFireability-2024-06 86403490 m, 553155 m/sec, 107039679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/514 379/2000 MAPK-PT-00320-CTLFireability-2024-06 89399710 m, 599244 m/sec, 110802581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 379
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/514 393/2000 MAPK-PT-00320-CTLFireability-2024-06 92848744 m, 689806 m/sec, 115108810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/514 406/2000 MAPK-PT-00320-CTLFireability-2024-06 95791135 m, 588478 m/sec, 118338443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 406
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/514 417/2000 MAPK-PT-00320-CTLFireability-2024-06 98627556 m, 567284 m/sec, 121437284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/514 431/2000 MAPK-PT-00320-CTLFireability-2024-06 101962427 m, 666974 m/sec, 125082419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/514 444/2000 MAPK-PT-00320-CTLFireability-2024-06 104884726 m, 584459 m/sec, 128295444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/514 456/2000 MAPK-PT-00320-CTLFireability-2024-06 107743559 m, 571766 m/sec, 131419479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 150/514 469/2000 MAPK-PT-00320-CTLFireability-2024-06 110906539 m, 632596 m/sec, 134870865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 469
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 155/514 484/2000 MAPK-PT-00320-CTLFireability-2024-06 114464871 m, 711666 m/sec, 138751392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 484
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 160/514 500/2000 MAPK-PT-00320-CTLFireability-2024-06 118214209 m, 749867 m/sec, 144023693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 500
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 165/514 508/2000 MAPK-PT-00320-CTLFireability-2024-06 120093647 m, 375887 m/sec, 149940556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 170/514 515/2000 MAPK-PT-00320-CTLFireability-2024-06 121766459 m, 334562 m/sec, 155772756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 515
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 175/514 529/2000 MAPK-PT-00320-CTLFireability-2024-06 125110602 m, 668828 m/sec, 159450463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 529
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 180/514 542/2000 MAPK-PT-00320-CTLFireability-2024-06 128191918 m, 616263 m/sec, 162821683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 185/514 556/2000 MAPK-PT-00320-CTLFireability-2024-06 131453682 m, 652352 m/sec, 166409487 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 556
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 190/514 569/2000 MAPK-PT-00320-CTLFireability-2024-06 134677216 m, 644706 m/sec, 170035322 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 569
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 195/514 581/2000 MAPK-PT-00320-CTLFireability-2024-06 137472852 m, 559127 m/sec, 173587430 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 581
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 200/514 592/2000 MAPK-PT-00320-CTLFireability-2024-06 140192694 m, 543968 m/sec, 177040510 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 592
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 205/514 604/2000 MAPK-PT-00320-CTLFireability-2024-06 142973083 m, 556077 m/sec, 180557279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 604
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 210/514 617/2000 MAPK-PT-00320-CTLFireability-2024-06 146006848 m, 606753 m/sec, 184383841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 617
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 215/514 631/2000 MAPK-PT-00320-CTLFireability-2024-06 149499400 m, 698510 m/sec, 188629181 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 631
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 220/514 645/2000 MAPK-PT-00320-CTLFireability-2024-06 152643071 m, 628734 m/sec, 192089872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 645
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 225/514 658/2000 MAPK-PT-00320-CTLFireability-2024-06 155821458 m, 635677 m/sec, 195579806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 658
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 230/514 672/2000 MAPK-PT-00320-CTLFireability-2024-06 159303773 m, 696463 m/sec, 199425771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 672
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 235/514 685/2000 MAPK-PT-00320-CTLFireability-2024-06 162384170 m, 616079 m/sec, 202814658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 685
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 240/514 699/2000 MAPK-PT-00320-CTLFireability-2024-06 165699289 m, 663023 m/sec, 206454018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 699
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 245/514 714/2000 MAPK-PT-00320-CTLFireability-2024-06 169279094 m, 715961 m/sec, 210370716 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 714
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 250/514 729/2000 MAPK-PT-00320-CTLFireability-2024-06 172692973 m, 682775 m/sec, 214100514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 729
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-07: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00320-CTLFireability-2023-14: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00320-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-05: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00320-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 255/514 731/2000 MAPK-PT-00320-CTLFireability-2024-06 173153358 m, 92077 m/sec, 214607260 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 731
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 414 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-00320"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is MAPK-PT-00320, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649614100450"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-00320.tgz
mv MAPK-PT-00320 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;