About the Execution of LoLA for MAPK-PT-00008
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1365.292 | 98545.00 | 100492.00 | 336.00 | FTFTTFFFTTFTFFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r225-tall-171649614000410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is MAPK-PT-00008, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649614000410
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 13 07:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 152K Apr 13 07:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K Apr 13 07:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Apr 13 07:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 25K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-00
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-01
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-02
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-03
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-04
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-05
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-06
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-07
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-08
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-09
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-10
FORMULA_NAME MAPK-PT-00008-CTLFireability-2024-11
FORMULA_NAME MAPK-PT-00008-CTLFireability-2023-12
FORMULA_NAME MAPK-PT-00008-CTLFireability-2023-13
FORMULA_NAME MAPK-PT-00008-CTLFireability-2023-14
FORMULA_NAME MAPK-PT-00008-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717073442298
FORMULA MAPK-PT-00008-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA MAPK-PT-00008-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-04: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mMAPK-PT-00008-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 98 secs. Pages in use: 26
BK_STOP 1717073540843
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 MAPK-PT-00008-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 MAPK-PT-00008-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 MAPK-PT-00008-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 101
[[35mlola[0m][I] fired transitions : 205
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 MAPK-PT-00008-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for MAPK-PT-00008-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 69
[[35mlola[0m][I] fired transitions : 130
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 MAPK-PT-00008-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for MAPK-PT-00008-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 MAPK-PT-00008-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 29 MAPK-PT-00008-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 24 (type EXCL) for 23 MAPK-PT-00008-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 44 MAPK-PT-00008-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 35 MAPK-PT-00008-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for MAPK-PT-00008-CTLFireability-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for MAPK-PT-00008-CTLFireability-2024-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 5/327 8/2000 MAPK-PT-00008-CTLFireability-2024-05 1751470 m, 350294 m/sec, 7682282 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 10/327 12/2000 MAPK-PT-00008-CTLFireability-2024-05 2778870 m, 205480 m/sec, 14821742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 15/327 14/2000 MAPK-PT-00008-CTLFireability-2024-05 3270063 m, 98238 m/sec, 21921068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-09: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-12: EG 0 1 0 0 2 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 24 CTL EXCL 20/327 16/2000 MAPK-PT-00008-CTLFireability-2024-05 3758291 m, 97645 m/sec, 29309892 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 24 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4025593
[[35mlola[0m][I] fired transitions : 33473721
[[35mlola[0m][I] time used : 23
[[35mlola[0m][I] memory pages used : 17
[[35mlola[0m][I] LAUNCH task # 15 (type EXCL) for 12 MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 357 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 15 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 MAPK-PT-00008-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 397 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 36672
[[35mlola[0m][I] fired transitions : 178617
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 MAPK-PT-00008-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 447 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 7035
[[35mlola[0m][I] fired transitions : 17412
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 MAPK-PT-00008-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 511 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 113
[[35mlola[0m][I] fired transitions : 242
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 44 MAPK-PT-00008-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 596 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for MAPK-PT-00008-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 35 MAPK-PT-00008-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 715 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 21 (type EXCL) for 12 MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 894 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 21 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 12 MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 1192 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 2/1192 3/2000 MAPK-PT-00008-CTLFireability-2024-04 617360 m, 123472 m/sec, 3055407 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 7/1192 8/2000 MAPK-PT-00008-CTLFireability-2024-04 1753171 m, 227162 m/sec, 9636781 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 12/1192 12/2000 MAPK-PT-00008-CTLFireability-2024-04 2770763 m, 203518 m/sec, 15886308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 17/1192 16/2000 MAPK-PT-00008-CTLFireability-2024-04 3737914 m, 193430 m/sec, 22020393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 22/1192 20/2000 MAPK-PT-00008-CTLFireability-2024-04 4675312 m, 187479 m/sec, 28104007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 27/1192 23/2000 MAPK-PT-00008-CTLFireability-2024-04 5586264 m, 182190 m/sec, 34272650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 32/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6106215 m, 103990 m/sec, 40936336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 37/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6108036 m, 364 m/sec, 47519680 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 42/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6108835 m, 159 m/sec, 53867763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 47/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6109389 m, 110 m/sec, 60103973 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 52/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6109824 m, 87 m/sec, 66270659 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 57/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6110211 m, 77 m/sec, 72423294 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 62/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6110472 m, 52 m/sec, 78771570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 67/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6110576 m, 20 m/sec, 85247686 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-05: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-09: F true state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mMAPK-PT-00008-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-12: EG false state space / EG[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mMAPK-PT-00008-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-04: DISJ 0 0 1 0 5 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] MAPK-PT-00008-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 72/1192 26/2000 MAPK-PT-00008-CTLFireability-2024-04 6110635 m, 11 m/sec, 92002415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6110643
[[35mlola[0m][I] fired transitions : 96585849
[[35mlola[0m][I] time used : 75
[[35mlola[0m][I] memory pages used : 26
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 26 MAPK-PT-00008-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 1751 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for MAPK-PT-00008-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 192
[[35mlola[0m][I] fired transitions : 392
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 MAPK-PT-00008-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 3502 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for MAPK-PT-00008-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 71
[[35mlola[0m][I] fired transitions : 135
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MAPK-PT-00008"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is MAPK-PT-00008, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649614000410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MAPK-PT-00008.tgz
mv MAPK-PT-00008 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;