About the Execution of LoLA for LeafsetExtension-PT-S16C3
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8140.691 | 813298.00 | 827449.00 | 1997.30 | FFFFFTTFTFFFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r225-tall-171649613900348.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is LeafsetExtension-PT-S16C3, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649613900348
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.5M
-rw-r--r-- 1 mcc users 14K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.0K May 19 07:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 19 16:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 12 13:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Apr 12 13:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 20K Apr 12 13:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 97K Apr 12 13:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 905K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-00
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-01
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-02
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-03
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-04
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-05
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-06
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-07
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-08
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-09
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-10
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-11
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-12
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-13
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-14
FORMULA_NAME LeafsetExtension-PT-S16C3-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717063010151
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C3-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-11: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 813 secs. Pages in use: 355
BK_STOP 1717063823449
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 64 (type SKEL/SRCH) for 0 LeafsetExtension-PT-S16C3-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/FNDP) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/EQUN) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/SRCH) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type SKEL/FNDP) for LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-01 (obsolete)
[[35mlola[0m][W] CANCELED task # 69 (type SRCH) for LeafsetExtension-PT-S16C3-LTLFireability-01 (obsolete)
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] FINISHED task # 64 (type SKEL/SRCH) for LeafsetExtension-PT-S16C3-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11112
[[35mlola[0m][I] fired transitions : 32796
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 40 LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 71 (type FNDP) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 3 LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 71 (type FNDP) for LeafsetExtension-PT-S16C3-LTLFireability-01 (obsolete)
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-01 (obsolete)
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 25 LeafsetExtension-PT-S16C3-LTLFireability-07
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 13 LeafsetExtension-PT-S16C3-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 19
[[35mlola[0m][I] fired transitions : 20
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 57 LeafsetExtension-PT-S16C3-LTLFireability-15
[[35mlola[0m][I] time limit : 143 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 71 (type FNDP) for LeafsetExtension-PT-S16C3-LTLFireability-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 LeafsetExtension-PT-S16C3-LTLFireability-04
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 80 (type FNDP) for 40 LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 40 LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type FNDP) for LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 81 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-12
[[35mlola[0m][I] result : unknown
[*** LOG ERROR #0001 ***] [2024-05-30 09:56:51] [status_logger] string pointer is null
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for LeafsetExtension-PT-S16C3-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 42198
[[35mlola[0m][I] fired transitions : 133888
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 54 LeafsetExtension-PT-S16C3-LTLFireability-14
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 LeafsetExtension-PT-S16C3-LTLFireability-10
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 LeafsetExtension-PT-S16C3-LTLFireability-09
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 LeafsetExtension-PT-S16C3-LTLFireability-08
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 137
[[35mlola[0m][I] fired transitions : 136
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 LeafsetExtension-PT-S16C3-LTLFireability-06
[[35mlola[0m][I] time limit : 514 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 LeafsetExtension-PT-S16C3-LTLFireability-02
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 24
[[35mlola[0m][I] fired transitions : 24
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 LeafsetExtension-PT-S16C3-LTLFireability-00
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 45928
[[35mlola[0m][I] fired transitions : 143729
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL) for 13 LeafsetExtension-PT-S16C3-LTLFireability-03
[[35mlola[0m][I] time limit : 899 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 75 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 17
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 LeafsetExtension-PT-S16C3-LTLFireability-05
[[35mlola[0m][I] time limit : 1199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 2/1199 3/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 230315 m, 46063 m/sec, 383143 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 7/1199 8/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 672223 m, 88381 m/sec, 1212471 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 12/1199 11/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 989939 m, 63543 m/sec, 2266740 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 17/1199 14/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 1357059 m, 73424 m/sec, 3215689 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 22/1199 20/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 1817583 m, 92104 m/sec, 4041431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 27/1199 24/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 2243200 m, 85123 m/sec, 4883182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 32/1199 28/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 2651814 m, 81722 m/sec, 5717241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 37/1199 33/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 3094702 m, 88577 m/sec, 6535818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 33
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 42/1199 38/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 3507374 m, 82534 m/sec, 7470197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 47/1199 43/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 3945102 m, 87545 m/sec, 8299658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 52/1199 47/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 4384136 m, 87806 m/sec, 9037979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 47
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 57/1199 52/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 4824864 m, 88145 m/sec, 9857714 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 62/1199 57/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 5253559 m, 85739 m/sec, 10673606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 67/1199 61/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 5680155 m, 85319 m/sec, 11479414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 72/1199 66/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 6105596 m, 85088 m/sec, 12275436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 77/1199 70/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 6493943 m, 77669 m/sec, 13058419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 82/1199 73/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 6847301 m, 70671 m/sec, 13874555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 87/1199 78/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 7287008 m, 87941 m/sec, 14656205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 92/1199 83/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 7733699 m, 89338 m/sec, 15417502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 97/1199 88/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 8181660 m, 89592 m/sec, 16190550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 102/1199 92/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 8573640 m, 78396 m/sec, 16966942 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 107/1199 96/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 8987955 m, 82863 m/sec, 17749418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 112/1199 101/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 9401041 m, 82617 m/sec, 18561550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 117/1199 105/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 9838174 m, 87426 m/sec, 19274888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 122/1199 110/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 10272068 m, 86778 m/sec, 20013567 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 127/1199 115/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 10718567 m, 89299 m/sec, 20769462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 132/1199 120/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 11152278 m, 86742 m/sec, 21595627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 120
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 137/1199 124/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 11572499 m, 84044 m/sec, 22372645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 142/1199 129/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 12022697 m, 90039 m/sec, 23106079 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 147/1199 134/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 12449630 m, 85386 m/sec, 23804570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 134
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 152/1199 139/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 12885136 m, 87101 m/sec, 24524000 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 157/1199 144/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 13325945 m, 88161 m/sec, 25322555 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 162/1199 149/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 13759918 m, 86794 m/sec, 26032981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 167/1199 154/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 14201231 m, 88262 m/sec, 26771135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 172/1199 158/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 14608200 m, 81393 m/sec, 27552792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 177/1199 164/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 15072524 m, 92864 m/sec, 28311109 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 182/1199 169/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 15527746 m, 91044 m/sec, 29061087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 187/1199 174/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 15960341 m, 86519 m/sec, 29807200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 192/1199 179/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 16395616 m, 87055 m/sec, 30515463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 197/1199 184/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 16833791 m, 87635 m/sec, 31239133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 202/1199 188/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 17240824 m, 81406 m/sec, 31962606 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 207/1199 192/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 17648939 m, 81623 m/sec, 32641718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 212/1199 196/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 18054747 m, 81161 m/sec, 33370370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 217/1199 201/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 18466691 m, 82388 m/sec, 34073766 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 222/1199 205/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 18875593 m, 81780 m/sec, 34797800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 205
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 227/1199 210/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 19297590 m, 84399 m/sec, 35534248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 232/1199 214/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 19717865 m, 84055 m/sec, 36237039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 237/1199 219/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 20134879 m, 83402 m/sec, 36914283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 242/1199 224/2000 LeafsetExtension-PT-S16C3-LTLFireability-05 20563355 m, 85695 m/sec, 37643931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 20 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 20911548
[[35mlola[0m][I] fired transitions : 38216637
[[35mlola[0m][I] time used : 247
[[35mlola[0m][I] memory pages used : 227
[[35mlola[0m][I] LAUNCH task # 52 (type EXCL) for 51 LeafsetExtension-PT-S16C3-LTLFireability-13
[[35mlola[0m][I] time limit : 1675 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 0/1675 2/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 84467 m, 16893 m/sec, 132314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 5/1675 5/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 483728 m, 79852 m/sec, 1093344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 10/1675 9/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 884495 m, 80153 m/sec, 2029857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 15/1675 13/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 1280014 m, 79103 m/sec, 2962918 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 20/1675 16/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 1651115 m, 74220 m/sec, 3935095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 25/1675 20/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 2034977 m, 76772 m/sec, 4879908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 30/1675 23/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 2431103 m, 79225 m/sec, 5846211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 35/1675 26/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 2799605 m, 73700 m/sec, 6822381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 40/1675 30/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 3197343 m, 79547 m/sec, 7726584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 45/1675 33/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 3546825 m, 69896 m/sec, 8661060 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 50/1675 37/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 3933608 m, 77356 m/sec, 9597084 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 55/1675 40/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 4298716 m, 73021 m/sec, 10527578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 60/1675 43/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 4646087 m, 69474 m/sec, 11543280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 65/1675 46/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 4973023 m, 65387 m/sec, 12628439 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 70/1675 49/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 5329382 m, 71271 m/sec, 13637233 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 75/1675 52/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 5662732 m, 66670 m/sec, 14614048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 80/1675 56/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 6079849 m, 83423 m/sec, 15479242 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 85/1675 60/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 6448627 m, 73755 m/sec, 16352374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 90/1675 62/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 6792866 m, 68847 m/sec, 17223319 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 95/1675 66/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 7161883 m, 73803 m/sec, 18103953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 100/1675 69/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 7527609 m, 73145 m/sec, 19020679 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 105/1675 72/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 7859121 m, 66302 m/sec, 19934927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 110/1675 75/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 8194111 m, 66998 m/sec, 20831940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 115/1675 79/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 8582575 m, 77692 m/sec, 21744969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 120/1675 82/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 8930527 m, 69590 m/sec, 22674305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 125/1675 84/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 9263171 m, 66528 m/sec, 23571534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 130/1675 88/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 9645343 m, 76434 m/sec, 24471690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 135/1675 91/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 10001967 m, 71324 m/sec, 25309855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 140/1675 94/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 10345513 m, 68709 m/sec, 26219672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 145/1675 97/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 10681506 m, 67198 m/sec, 27129261 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 150/1675 100/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 11021372 m, 67973 m/sec, 28039920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 155/1675 103/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 11365642 m, 68854 m/sec, 28894431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 160/1675 107/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 11762600 m, 79391 m/sec, 29745553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 165/1675 110/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 12110970 m, 69674 m/sec, 30661342 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 170/1675 114/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 12490850 m, 75976 m/sec, 31521228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 175/1675 117/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 12856274 m, 73084 m/sec, 32429784 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 180/1675 120/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 13198232 m, 68391 m/sec, 33326466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 185/1675 123/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 13577074 m, 75768 m/sec, 34231944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 190/1675 126/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 13940944 m, 72774 m/sec, 35089754 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 195/1675 129/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 14280909 m, 67993 m/sec, 35953281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 200/1675 132/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 14631955 m, 70209 m/sec, 36841331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 205/1675 136/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 14981293 m, 69867 m/sec, 37720127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 210/1675 138/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 15303608 m, 64463 m/sec, 38687841 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 215/1675 141/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 15630515 m, 65381 m/sec, 39627570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 220/1675 145/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 15989904 m, 71877 m/sec, 40490646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 225/1675 147/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 16336702 m, 69359 m/sec, 41335805 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 230/1675 150/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 16672297 m, 67119 m/sec, 42146258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 235/1675 153/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 17027161 m, 70972 m/sec, 42997807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 240/1675 156/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 17376477 m, 69863 m/sec, 43834697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 245/1675 159/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 17733971 m, 71498 m/sec, 44686076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 250/1675 162/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 18099010 m, 73007 m/sec, 45594759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 255/1675 166/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 18467177 m, 73633 m/sec, 46476029 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 260/1675 169/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 18851904 m, 76945 m/sec, 47416248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 265/1675 173/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 19198235 m, 69266 m/sec, 48376861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 270/1675 175/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 19517463 m, 63845 m/sec, 49311596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 275/1675 179/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 19902016 m, 76910 m/sec, 50100827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 280/1675 182/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 20241819 m, 67960 m/sec, 50994054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 285/1675 185/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 20607252 m, 73086 m/sec, 51904533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 290/1675 188/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 20943496 m, 67248 m/sec, 52743358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 295/1675 191/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 21304151 m, 72131 m/sec, 53633494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 300/1675 195/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 21656684 m, 70506 m/sec, 54482747 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 305/1675 198/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 21996965 m, 68056 m/sec, 55285651 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 310/1675 200/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 22318981 m, 64403 m/sec, 56073524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 315/1675 204/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 22690584 m, 74320 m/sec, 56968399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 320/1675 207/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 23021986 m, 66280 m/sec, 57847774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 325/1675 210/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 23355592 m, 66721 m/sec, 58833742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 330/1675 213/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 23733004 m, 75482 m/sec, 59749481 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 335/1675 216/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 24089268 m, 71252 m/sec, 60654082 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 340/1675 220/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 24463348 m, 74816 m/sec, 61538803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 345/1675 223/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 24851337 m, 77597 m/sec, 62437014 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 350/1675 227/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 25236660 m, 77064 m/sec, 63353831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 355/1675 230/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 25592053 m, 71078 m/sec, 64268966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 360/1675 233/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 25971363 m, 75862 m/sec, 65171350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 365/1675 236/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 26316355 m, 68998 m/sec, 66146601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 370/1675 240/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 26703676 m, 77464 m/sec, 67054623 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 375/1675 243/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 27074994 m, 74263 m/sec, 67967575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 380/1675 247/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 27451140 m, 75229 m/sec, 68867028 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 385/1675 250/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 27812297 m, 72231 m/sec, 69778257 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 250
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 390/1675 253/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 28166746 m, 70889 m/sec, 70678263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 395/1675 256/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 28522839 m, 71218 m/sec, 71524076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 400/1675 259/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 28855878 m, 66607 m/sec, 72453763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 405/1675 262/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 29216302 m, 72084 m/sec, 73340947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 410/1675 265/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 29578614 m, 72462 m/sec, 74179368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 415/1675 268/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 29931023 m, 70481 m/sec, 75024483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 268
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 420/1675 272/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 30288093 m, 71414 m/sec, 75885359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 425/1675 275/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 30647028 m, 71787 m/sec, 76727782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 430/1675 278/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 30999578 m, 70510 m/sec, 77608445 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 435/1675 281/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 31349161 m, 69916 m/sec, 78477558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 440/1675 284/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 31683084 m, 66784 m/sec, 79298435 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 445/1675 287/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 32009080 m, 65199 m/sec, 80120503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 450/1675 289/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 32337957 m, 65775 m/sec, 80958232 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 289
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 455/1675 292/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 32657918 m, 63992 m/sec, 81751015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 460/1675 295/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 32981195 m, 64655 m/sec, 82577952 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 465/1675 298/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 33296772 m, 63115 m/sec, 83475683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 470/1675 300/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 33634854 m, 67616 m/sec, 84367414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 475/1675 304/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 33992294 m, 71488 m/sec, 85219444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 480/1675 306/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 34305015 m, 62544 m/sec, 86108016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 485/1675 309/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 34628326 m, 64662 m/sec, 86920168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 490/1675 312/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 34948475 m, 64029 m/sec, 87741119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 495/1675 315/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 35296154 m, 69535 m/sec, 88643570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 500/1675 317/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 35608903 m, 62549 m/sec, 89559573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 505/1675 320/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 35943266 m, 66872 m/sec, 90435859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 510/1675 323/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 36300307 m, 71408 m/sec, 91284117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 515/1675 326/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 36648702 m, 69679 m/sec, 92125819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 520/1675 330/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 36998541 m, 69967 m/sec, 93002144 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 525/1675 333/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 37346573 m, 69606 m/sec, 93812416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 530/1675 336/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 37688159 m, 68317 m/sec, 94608032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 535/1675 339/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 38022681 m, 66904 m/sec, 95415102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 339
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 540/1675 342/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 38373733 m, 70210 m/sec, 96274213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 342
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 545/1675 345/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 38713221 m, 67897 m/sec, 97161417 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 345
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 550/1675 348/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 39058195 m, 68994 m/sec, 98011877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 555/1675 350/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 39392399 m, 66840 m/sec, 98867345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-01: CONJ false state space[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-03: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-05: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-06: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C3-LTLFireability-08: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C3-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL EXCL 560/1675 353/2000 LeafsetExtension-PT-S16C3-LTLFireability-13 39711992 m, 63918 m/sec, 99668862 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 52 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 39877784
[[35mlola[0m][I] fired transitions : 100065292
[[35mlola[0m][I] time used : 563
[[35mlola[0m][I] memory pages used : 355
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 LeafsetExtension-PT-S16C3-LTLFireability-11
[[35mlola[0m][I] time limit : 2787 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 38 (type EXCL) for LeafsetExtension-PT-S16C3-LTLFireability-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 18
[[35mlola[0m][I] fired transitions : 18
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S16C3"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is LeafsetExtension-PT-S16C3, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649613900348"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S16C3.tgz
mv LeafsetExtension-PT-S16C3 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;