About the Execution of LoLA for LeafsetExtension-PT-S16C2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1296.775 | 229158.00 | 234446.00 | 550.90 | TTTTFFTFFTTTFFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r225-tall-171649613900338.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is LeafsetExtension-PT-S16C2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649613900338
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.4M
-rw-r--r-- 1 mcc users 14K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 92K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.5K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 12 13:42 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 130K Apr 12 13:42 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 14K Apr 12 13:41 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Apr 12 13:41 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.3K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 905K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-00
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-01
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-02
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-03
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-04
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-05
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-06
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-07
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-08
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-09
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-10
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2024-11
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2023-12
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2023-13
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2023-14
FORMULA_NAME LeafsetExtension-PT-S16C2-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717061880287
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S16C2-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-00: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-05: F false state space / EG[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF false tscc_search[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ true CONJ[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ true state space / EG[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 229 secs. Pages in use: 20
BK_STOP 1717062109445
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 LeafsetExtension-PT-S16C2-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 179 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 15 LeafsetExtension-PT-S16C2-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type EQUN) for 34 LeafsetExtension-PT-S16C2-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for LeafsetExtension-PT-S16C2-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 21 LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 21 LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EQUN) for LeafsetExtension-PT-S16C2-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 78 (type EQUN) for 50 LeafsetExtension-PT-S16C2-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 78 (type EQUN) for LeafsetExtension-PT-S16C2-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-14: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 4/189 3/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-06 225771 m, 45154 m/sec, 815058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 384548
[[35mlola[0m][I] fired transitions : 1425467
[[35mlola[0m][I] time used : 7
[[35mlola[0m][I] memory pages used : 4
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 50 LeafsetExtension-PT-S16C2-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 57 LeafsetExtension-PT-S16C2-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 58 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 283
[[35mlola[0m][I] fired transitions : 300
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 50 LeafsetExtension-PT-S16C2-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2023-14: DISJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 CTL EXCL 2/224 2/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-14 97425 m, 19485 m/sec, 222644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 12/224 7/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-14 533171 m, 43873 m/sec, 1318600 t fired, .
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[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ 0 2 0 0 3 0 0 0
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[[35mlola[0m][.] 45 CTL EXCL 14/254 9/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-12 644025 m, 47090 m/sec, 1573062 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 19/254 12/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-12 876157 m, 46426 m/sec, 2102675 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 24/254 15/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-12 1107409 m, 46250 m/sec, 2631182 t fired, .
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[[35mlola[0m][.] 45 CTL EXCL 29/254 18/2000 LeafsetExtension-PT-S16C2-CTLFireability-2023-12 1331786 m, 44875 m/sec, 3146994 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-08
[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 1 CTL EXCL 1/440 1/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-00 65745 m, 13149 m/sec, 183548 t fired, .
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[[35mlola[0m][.] 1 CTL EXCL 11/440 6/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-00 434400 m, 35733 m/sec, 1337070 t fired, .
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[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 141/440 20/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-00 1465646 m, 280 m/sec, 14857088 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-11: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2023-12: CTL false CTL model checker[0m
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[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ 0 1 0 0 4 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 146/440 20/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-00 1467067 m, 284 m/sec, 15398794 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1468544
[[35mlola[0m][I] fired transitions : 15713751
[[35mlola[0m][I] time used : 149
[[35mlola[0m][I] memory pages used : 20
[[35mlola[0m][I] LAUNCH task # 66 (type EXCL) for 21 LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 482 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 9
[[35mlola[0m][I] fired transitions : 8
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 15 LeafsetExtension-PT-S16C2-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 562 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 61 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 34 LeafsetExtension-PT-S16C2-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 675 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 LeafsetExtension-PT-S16C2-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 844 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 26
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 LeafsetExtension-PT-S16C2-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 1125 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 14
[[35mlola[0m][I] fired transitions : 28
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 LeafsetExtension-PT-S16C2-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 1688 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S16C2-CTLFireability-2024-07: AGEF false tscc_search[0m
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[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-09: CONJ true CONJ[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-10: DISJ true state space / EG[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2024-11: CTL true CTL model checker[0m
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[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S16C2-CTLFireability-2023-15: CTL true CTL model checker[0m
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 7 CTL EXCL 2/1688 2/2000 LeafsetExtension-PT-S16C2-CTLFireability-2024-02 129460 m, 25892 m/sec, 452736 t fired, .
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[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 363770
[[35mlola[0m][I] fired transitions : 1285919
[[35mlola[0m][I] time used : 6
[[35mlola[0m][I] memory pages used : 4
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 LeafsetExtension-PT-S16C2-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3371 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for LeafsetExtension-PT-S16C2-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S16C2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is LeafsetExtension-PT-S16C2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649613900338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S16C2.tgz
mv LeafsetExtension-PT-S16C2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;