About the Execution of LoLA for LeafsetExtension-PT-S08C3
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 5661.100 | 1185784.00 | 1198022.00 | 3269.00 | FTFTFTFFFFTF?TTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r225-tall-171649613900322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is LeafsetExtension-PT-S08C3, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649613900322
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 800K
-rw-r--r-- 1 mcc users 13K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.8K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 21K Apr 12 13:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Apr 12 13:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 20K Apr 12 13:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 99K Apr 12 13:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 254K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-00
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-01
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-02
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-03
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-04
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-05
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-06
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-07
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-08
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-09
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-10
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2024-11
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2023-12
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2023-13
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2023-14
FORMULA_NAME LeafsetExtension-PT-S08C3-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717059897205
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LeafsetExtension-PT-S08C3-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-01: EFAG true tscc_search[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-06: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-07: EFAG false tscc_search[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[33mLeafsetExtension-PT-S08C3-CTLFireability-2023-12: CTL unknown AGGR[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 1185 secs. Pages in use: 80
BK_STOP 1717061082989
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 LeafsetExtension-PT-S08C3-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 156 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 25 (type EXCL) for LeafsetExtension-PT-S08C3-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16
[[35mlola[0m][I] fired transitions : 47
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 LeafsetExtension-PT-S08C3-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for LeafsetExtension-PT-S08C3-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 131
[[35mlola[0m][I] fired transitions : 427
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 LeafsetExtension-PT-S08C3-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 3 LeafsetExtension-PT-S08C3-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 3 LeafsetExtension-PT-S08C3-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 21 LeafsetExtension-PT-S08C3-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type EQUN) for LeafsetExtension-PT-S08C3-CTLFireability-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 59 (type EQUN) for 21 LeafsetExtension-PT-S08C3-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for LeafsetExtension-PT-S08C3-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for LeafsetExtension-PT-S08C3-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 59 (type EQUN) for LeafsetExtension-PT-S08C3-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 5/257 4/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-05 649190 m, 129838 m/sec, 3009045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 CTL EXCL 10/257 7/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-05 1294656 m, 129093 m/sec, 6010903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for LeafsetExtension-PT-S08C3-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1726753
[[35mlola[0m][I] fired transitions : 8041802
[[35mlola[0m][I] time used : 14
[[35mlola[0m][I] memory pages used : 10
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 LeafsetExtension-PT-S08C3-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 1/275 1/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-15 164971 m, 32994 m/sec, 531463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mLeafsetExtension-PT-S08C3-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mLeafsetExtension-PT-S08C3-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LeafsetExtension-PT-S08C3-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 2/344 1/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 86304 m, 17260 m/sec, 863825 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 7/344 2/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 272752 m, 37289 m/sec, 2752428 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 12/344 3/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 454661 m, 36381 m/sec, 4577200 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 17/344 4/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 630256 m, 35119 m/sec, 6364232 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 22/344 5/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 805769 m, 35102 m/sec, 8159306 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 27/344 6/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 977072 m, 34260 m/sec, 9959753 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 72/344 15/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 2500897 m, 34589 m/sec, 25707605 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 327/344 64/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 10813195 m, 32106 m/sec, 111426638 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 332/344 65/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 10975903 m, 32541 m/sec, 113073391 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 337/344 66/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 11139773 m, 32774 m/sec, 114762991 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 342/344 67/2000 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 11324138 m, 36873 m/sec, 116399856 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 5/343 2/5 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 191830 m, -2226461 m/sec, 1947084 t fired, .
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[[35mlola[0m][.] 37 CTL EXCL 15/343 4/5 LeafsetExtension-PT-S08C3-CTLFireability-2023-12 567030 m, 36748 m/sec, 5716721 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 58/481 20/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-02 3288873 m, 37830 m/sec, 19846845 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 388/481 77/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-02 12949922 m, 31595 m/sec, 122993276 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 393/481 78/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-02 13113450 m, 32705 m/sec, 124489137 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 398/481 78/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-02 13260465 m, 29403 m/sec, 125919849 t fired, .
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[[35mlola[0m][.] 7 CTL EXCL 403/481 79/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-02 13411776 m, 30262 m/sec, 127410626 t fired, .
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[[35mlola[0m][I] result : false
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[[35mlola[0m][.] 51 AGEF EXCL 1/496 1/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-07 175143 m, 35028 m/sec, 584889 t fired, .
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[[35mlola[0m][.] 51 AGEF EXCL 6/496 6/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-07 1095622 m, 184095 m/sec, 3790421 t fired, .
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[[35mlola[0m][I] result : false
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[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 LeafsetExtension-PT-S08C3-CTLFireability-2024-00
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[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 16
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 LeafsetExtension-PT-S08C3-CTLFireability-2024-03
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1608
[[35mlola[0m][I] fired transitions : 5614
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 LeafsetExtension-PT-S08C3-CTLFireability-2024-09
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[[35mlola[0m][.] 28 CTL EXCL 1/2471 1/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 65396 m, 13079 m/sec, 738378 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 6/2471 2/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 301668 m, 47254 m/sec, 3589976 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 11/2471 3/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 534993 m, 46665 m/sec, 6385795 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 16/2471 5/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 808999 m, 54801 m/sec, 9130336 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 21/2471 6/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 1012241 m, 40648 m/sec, 11875478 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 26/2471 7/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 1210789 m, 39709 m/sec, 14590299 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 31/2471 8/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 1432436 m, 44329 m/sec, 17200826 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 36/2471 10/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 1644348 m, 42382 m/sec, 19812351 t fired, .
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[[35mlola[0m][.] 28 CTL EXCL 41/2471 11/2000 LeafsetExtension-PT-S08C3-CTLFireability-2024-09 1858099 m, 42750 m/sec, 22408951 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S08C3"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is LeafsetExtension-PT-S08C3, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649613900322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S08C3.tgz
mv LeafsetExtension-PT-S08C3 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;