fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r225-tall-171649613800298
Last Updated
July 7, 2024

About the Execution of LoLA for LamportFastMutEx-PT-7

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16208.367 538716.00 841262.00 3546.20 ???????????F?T?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r225-tall-171649613800298.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is LamportFastMutEx-PT-7, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649613800298
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.7M
-rw-r--r-- 1 mcc users 20K Apr 13 07:37 CTLCardinality.txt
-rw-r--r-- 1 mcc users 139K Apr 13 07:37 CTLCardinality.xml
-rw-r--r-- 1 mcc users 37K Apr 13 07:35 CTLFireability.txt
-rw-r--r-- 1 mcc users 199K Apr 13 07:35 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 19K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 79K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 18K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 76K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 32K Apr 13 07:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 193K Apr 13 07:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 82K Apr 13 07:44 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 417K Apr 13 07:44 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 9.7K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 2 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 265K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-00
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-01
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-02
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-03
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-04
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-05
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-06
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-07
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-08
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-09
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-10
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-11
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-12
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-13
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-14
FORMULA_NAME LamportFastMutEx-PT-7-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717056863160

FORMULA LamportFastMutEx-PT-7-CTLFireability-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-PT-7-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717057401876

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 74 transitions removed,45 places removed
[lola][I] LAUNCH task # 44 (type CNST) for 43 LamportFastMutEx-PT-7-CTLFireability-2024-13
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 38 (type CNST) for 37 LamportFastMutEx-PT-7-CTLFireability-2024-11
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] FINISHED task # 44 (type CNST) for LamportFastMutEx-PT-7-CTLFireability-2024-13
[lola][I] result : true
[lola][I] FINISHED task # 38 (type CNST) for LamportFastMutEx-PT-7-CTLFireability-2024-11
[lola][I] result : false
[lola][I] LAUNCH task # 63 (type SKEL/EQUN) for 31 LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 61 (type SKEL/SRCH) for 31 LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 61 (type SKEL/SRCH) for LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 242
[lola][I] fired transitions : 265
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 63 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-09 (obsolete)
[lola][I] FINISHED task # 63 (type SKEL/EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] result : false
[lola][I] LAUNCH task # 10 (type EXCL) for 9 LamportFastMutEx-PT-7-CTLFireability-2024-03
[lola][I] time limit : 163 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 70 (type EQUN) for 46 LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 71 (type EQUN) for 28 LamportFastMutEx-PT-7-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 73 (type EQUN) for 28 LamportFastMutEx-PT-7-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 70 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] result : unknown
[lola][I] LAUNCH task # 76 (type EQUN) for 31 LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 71 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-08
[lola][I] result : unknown
[lola][I] LAUNCH task # 81 (type EQUN) for 46 LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 73 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-08
[lola][I] result : unknown
[lola][I] FINISHED task # 81 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] result : true
[lola][I] FINISHED task # 76 (type EQUN) for LamportFastMutEx-PT-7-CTLFireability-2024-09
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 3 0 0 5 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 5/211 6/2000 LamportFastMutEx-PT-7-CTLFireability-2024-03 1253094 m, 250618 m/sec, 4438826 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 6
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 3 0 0 5 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 10 CTL EXCL 10/211 11/2000 LamportFastMutEx-PT-7-CTLFireability-2024-03 2351190 m, 219619 m/sec, 9128431 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 11
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 1 0 0 6 0 0 1
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 58 CTL EXCL 247/258 188/2000 LamportFastMutEx-PT-7-CTLFireability-2024-15 42454034 m, 155392 m/sec, 187269525 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 1 0 0 6 0 0 1
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 58 CTL EXCL 252/258 191/2000 LamportFastMutEx-PT-7-CTLFireability-2024-15 43246759 m, 158545 m/sec, 190826530 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 1 0 0 6 0 0 1
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
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[lola][.] 58 CTL EXCL 257/258 194/2000 LamportFastMutEx-PT-7-CTLFireability-2024-15 44002721 m, 151192 m/sec, 194542629 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF true state space /EXEF
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ 0 1 0 0 6 0 0 1
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[lola][I] LAUNCH task # 55 (type EXCL) for 46 LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] time limit : 258 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 58 (type EXCL) for 57 LamportFastMutEx-PT-7-CTLFireability-2024-15
[lola][I] time limit : 3100 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 55 (type EXCL) for LamportFastMutEx-PT-7-CTLFireability-2024-14
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF true state space /EXEF
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ true CONJ
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[lola][I] LAUNCH task # 41 (type EXCL) for 40 LamportFastMutEx-PT-7-CTLFireability-2024-12
[lola][I] time limit : 281 sec
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF true state space /EXEF
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-14: CONJ true CONJ
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 41 CTL EXCL 5/281 7/2000 LamportFastMutEx-PT-7-CTLFireability-2024-12 1350960 m, 270192 m/sec, 3564753 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[lola][.]
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[lola][.] 41 CTL EXCL 10/281 11/2000 LamportFastMutEx-PT-7-CTLFireability-2024-12 2472335 m, 224275 m/sec, 7274760 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[lola][.]
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[lola][.] 41 CTL EXCL 15/281 16/2000 LamportFastMutEx-PT-7-CTLFireability-2024-12 3508686 m, 207270 m/sec, 11212945 t fired, .
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-09: EXEF true state space /EXEF
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[lola][.]
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-11: INITIAL false preprocessing
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-13: INITIAL true preprocessing
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[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-08: AGAF 0 1 0 0 3 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[lola][.] LamportFastMutEx-PT-7-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 404 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-PT-7"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-PT-7, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649613800298"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-PT-7.tgz
mv LamportFastMutEx-PT-7 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;