MCC'2024- Execution of r225-tall-171649613600218

About the Execution of LoLA for LamportFastMutEx-COL-4

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
2174.743	172593.00	353087.00	442.90	FTTTFTTFTTFFTFFF	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r225-tall-171649613600218.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is LamportFastMutEx-COL-4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r225-tall-171649613600218
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 452K
-rw-r--r-- 1 mcc users 6.8K Apr 13 07:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 67K Apr 13 07:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Apr 13 07:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K Apr 13 07:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Apr 22 14:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Apr 13 07:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 07:51 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 78K Apr 13 07:51 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 2 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 40K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-00
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-01
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-02
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-03
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-04
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-05
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-06
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-07
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-08
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-09
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-10
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-11
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-12
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-13
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-14
FORMULA_NAME LamportFastMutEx-COL-4-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717051936180

FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA LamportFastMutEx-COL-4-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-00: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-03: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-05: AGEF true tscc_search[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-09: EF true findpath[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-14: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 172 secs. Pages in use: 9

BK_STOP 1717052108773

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 2 (type SKEL/CNST) for 0 LamportFastMutEx-COL-4-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 2 (type SKEL/CNST) for LamportFastMutEx-COL-4-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Places: 135, Transitions: 230
[[35mlola[0m][I] LAUNCH task # 49 (type SKEL/FNDP) for 27 LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 50 (type SKEL/EQUN) for 27 LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 51 (type SKEL/SRCH) for 27 LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 51 (type SKEL/SRCH) for LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 10
[[35mlola[0m][I] fired transitions : 9
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 49 (type FNDP) for LamportFastMutEx-COL-4-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 50 (type EQUN) for LamportFastMutEx-COL-4-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][I] FINISHED task # 49 (type SKEL/FNDP) for LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 50 (type SKEL/EQUN) for LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 50 transitions removed,33 places removed
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 LamportFastMutEx-COL-4-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 55 (type EQUN) for 15 LamportFastMutEx-COL-4-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EQUN) for 15 LamportFastMutEx-COL-4-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type FNDP) for 27 LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type FNDP) for LamportFastMutEx-COL-4-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-00: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-09: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-05: AGEF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 5/257 6/2000 LamportFastMutEx-COL-4-CTLFireability-2024-15 1236040 m, 247208 m/sec, 5170238 t fired, .
[[35mlola[0m][.] 55 EF STEQ 5/3600 0/5 LamportFastMutEx-COL-4-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.] 57 EF STEQ 5/3600 0/5 LamportFastMutEx-COL-4-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 55 (type EQUN) for LamportFastMutEx-COL-4-CTLFireability-2024-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-00: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-09: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-05: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 10/257 8/2000 LamportFastMutEx-COL-4-CTLFireability-2024-15 1576465 m, 68085 m/sec, 10088450 t fired, .
[[35mlola[0m][.] 57 EF STEQ 10/3600 0/5 LamportFastMutEx-COL-4-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-00: INITIAL false skeleton: preprocessing[0m
[[35mlola[0m][.] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-09: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-05: AGEF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 CTL EXCL 15/257 9/2000 LamportFastMutEx-COL-4-CTLFireability-2024-15 1817796 m, 48266 m/sec, 15213796 t fired, .
[[35mlola[0m][.] 57 EF STEQ 15/3600 0/5 LamportFastMutEx-COL-4-CTLFireability-2024-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 46 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-2024-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1913028
[[35mlola[0m][I] fired transitions : 17799052
[[35mlola[0m][I] time used : 18
[[35mlola[0m][I] memory pages used : 9
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 LamportFastMutEx-COL-4-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 275 sec
[[35mlola[0m][I] memory limit: 2000 pages
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[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-2024-04
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[[35mlola[0m][I] result : true
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[[35mlola[0m][.] 4 CTL EXCL 1/701 1/2000 LamportFastMutEx-COL-4-CTLFireability-2024-01 212967 m, 42593 m/sec, 1041522 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 6/701 5/2000 LamportFastMutEx-COL-4-CTLFireability-2024-01 915898 m, 140586 m/sec, 5577421 t fired, .
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[[35mlola[0m][.] 4 CTL EXCL 11/701 8/2000 LamportFastMutEx-COL-4-CTLFireability-2024-01 1608883 m, 138597 m/sec, 10244844 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 LamportFastMutEx-COL-4-CTLFireability-2024-13
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[[35mlola[0m][.] 40 CTL EXCL 3/873 3/2000 LamportFastMutEx-COL-4-CTLFireability-2024-13 546099 m, 109219 m/sec, 2494753 t fired, .
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[[35mlola[0m][.] 40 CTL EXCL 8/873 6/2000 LamportFastMutEx-COL-4-CTLFireability-2024-13 1296495 m, 150079 m/sec, 7147524 t fired, .
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[[35mlola[0m][I] LAUNCH task # 37 (type EXCL) for 36 LamportFastMutEx-COL-4-CTLFireability-2024-12
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 634
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[[35mlola[0m][.] 22 CTL EXCL 0/1740 1/2000 LamportFastMutEx-COL-4-CTLFireability-2024-07 44646 m, 8929 m/sec, 142275 t fired, .
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[[35mlola[0m][.] [1m[32mLamportFastMutEx-COL-4-CTLFireability-2024-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mLamportFastMutEx-COL-4-CTLFireability-2024-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] LamportFastMutEx-COL-4-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 43 CTL EXCL 34/3464 9/2000 LamportFastMutEx-COL-4-CTLFireability-2024-14 1914688 m, 0 m/sec, 34914219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 43 (type EXCL) for LamportFastMutEx-COL-4-CTLFireability-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1914688
[[35mlola[0m][I] fired transitions : 36795189
[[35mlola[0m][I] time used : 36
[[35mlola[0m][I] memory pages used : 9
[[35mlola[0m][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LamportFastMutEx-COL-4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is LamportFastMutEx-COL-4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r225-tall-171649613600218"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LamportFastMutEx-COL-4.tgz
mv LamportFastMutEx-COL-4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;