About the Execution of 2023-gold for HirschbergSinclair-PT-45
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 581.443 | 53162.00 | 161019.00 | 421.30 | FTFTTFTFFFFTFFFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r219-smll-171649597900079.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool gold2023
Input is HirschbergSinclair-PT-45, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r219-smll-171649597900079
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.9K May 19 07:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:59 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 19 07:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 18:29 LTLFireability.xml
-rw-r--r-- 1 mcc users 24K Apr 13 02:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 176K Apr 13 02:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 13 02:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 88K Apr 13 02:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:49 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:49 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 616K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14
FORMULA_NAME HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1716655433514
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=gold2023
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-45
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2024-05-25 16:43:56] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-05-25 16:43:56] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-25 16:43:56] [INFO ] Load time of PNML (sax parser for PT used): 176 ms
[2024-05-25 16:43:56] [INFO ] Transformed 1138 places.
[2024-05-25 16:43:56] [INFO ] Transformed 1042 transitions.
[2024-05-25 16:43:56] [INFO ] Parsed PT model containing 1138 places and 1042 transitions and 3176 arcs in 291 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 35 ms.
Working with output stream class java.io.PrintStream
Incomplete random walk after 10000 steps, including 9 resets, run finished after 783 ms. (steps per millisecond=12 ) properties (out of 16) seen :6
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 80 ms. (steps per millisecond=125 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 89 ms. (steps per millisecond=112 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 69 ms. (steps per millisecond=144 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 41 ms. (steps per millisecond=243 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 10) seen :0
Running SMT prover for 10 properties.
// Phase 1: matrix 1042 rows 1138 cols
[2024-05-25 16:43:58] [INFO ] Computed 96 invariants in 53 ms
[2024-05-25 16:43:59] [INFO ] After 904ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:10
[2024-05-25 16:43:59] [INFO ] [Nat]Absence check using 90 positive place invariants in 72 ms returned sat
[2024-05-25 16:43:59] [INFO ] [Nat]Absence check using 90 positive and 6 generalized place invariants in 19 ms returned sat
[2024-05-25 16:44:02] [INFO ] After 2805ms SMT Verify possible using state equation in natural domain returned unsat :8 sat :2
[2024-05-25 16:44:04] [INFO ] Deduced a trap composed of 108 places in 543 ms of which 9 ms to minimize.
[2024-05-25 16:44:04] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 918 ms
[2024-05-25 16:44:05] [INFO ] Deduced a trap composed of 105 places in 535 ms of which 2 ms to minimize.
[2024-05-25 16:44:06] [INFO ] Deduced a trap composed of 15 places in 531 ms of which 2 ms to minimize.
[2024-05-25 16:44:06] [INFO ] Trap strengthening (SAT) tested/added 3/2 trap constraints in 1450 ms
[2024-05-25 16:44:06] [INFO ] After 6680ms SMT Verify possible using trap constraints in natural domain returned unsat :9 sat :1
Attempting to minimize the solution found.
Minimization took 1279 ms.
[2024-05-25 16:44:07] [INFO ] After 8912ms SMT Verify possible using all constraints in natural domain returned unsat :9 sat :1
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 10 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 15 ms.
Support contains 39 out of 1138 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 1138/1138 places, 1042/1042 transitions.
Graph (complete) has 2184 edges and 1138 vertex of which 1092 are kept as prefixes of interest. Removing 46 places using SCC suffix rule.6 ms
Discarding 46 places :
Also discarding 0 output transitions
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed 1 transitions.
Drop transitions removed 414 transitions
Trivial Post-agglo rules discarded 414 transitions
Performed 414 trivial Post agglomeration. Transition count delta: 414
Iterating post reduction 0 with 415 rules applied. Total rules applied 416 place count 1092 transition count 627
Reduce places removed 414 places and 0 transitions.
Graph (complete) has 1141 edges and 678 vertex of which 563 are kept as prefixes of interest. Removing 115 places using SCC suffix rule.2 ms
Discarding 115 places :
Also discarding 0 output transitions
Performed 19 Post agglomeration using F-continuation condition.Transition count delta: 19
Iterating post reduction 1 with 434 rules applied. Total rules applied 850 place count 563 transition count 608
Reduce places removed 19 places and 0 transitions.
Drop transitions removed 115 transitions
Reduce isomorphic transitions removed 115 transitions.
Iterating post reduction 2 with 134 rules applied. Total rules applied 984 place count 544 transition count 493
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 987 place count 541 transition count 490
Iterating global reduction 3 with 3 rules applied. Total rules applied 990 place count 541 transition count 490
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 992 place count 539 transition count 488
Iterating global reduction 3 with 2 rules applied. Total rules applied 994 place count 539 transition count 488
Free-agglomeration rule (complex) applied 54 times.
Iterating global reduction 3 with 54 rules applied. Total rules applied 1048 place count 539 transition count 434
Reduce places removed 54 places and 0 transitions.
Iterating post reduction 3 with 54 rules applied. Total rules applied 1102 place count 485 transition count 434
Reduce places removed 41 places and 41 transitions.
Iterating global reduction 4 with 41 rules applied. Total rules applied 1143 place count 444 transition count 393
Applied a total of 1143 rules in 282 ms. Remains 444 /1138 variables (removed 694) and now considering 393/1042 (removed 649) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 283 ms. Remains : 444/1138 places, 393/1042 transitions.
Incomplete random walk after 10000 steps, including 25 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 1) seen :0
Finished Best-First random walk after 1348 steps, including 0 resets, run visited all 1 properties in 6 ms. (steps per millisecond=224 )
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Parikh walk visited 0 properties in 0 ms.
All properties solved without resorting to model-checking.
Total runtime 12299 ms.
starting LoLA
BK_INPUT HirschbergSinclair-PT-45
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1716655486676
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 19 (type CNST) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 36 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 36 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 36 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SRCH) for 36 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-49.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 51 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: result : false
lola: markings : 422529
lola: fired transitions : 556248
lola: time used : 3.000000
lola: memory pages used : 2
lola: CANCELED task # 48 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12 (obsolete)
lola: CANCELED task # 49 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12 (obsolete)
lola: CANCELED task # 52 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12 (obsolete)
lola: LAUNCH task # 72 (type EXCL) for 45 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 142 (type FNDP) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 143 (type EQUN) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 145 (type SRCH) for 24 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: result : unknown
lola: FINISHED task # 48 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12
lola: result : unknown
lola: fired transitions : 1040050
lola: tried executions : 6338
lola: time used : 3.000000
lola: memory pages used : 0
lola: FINISHED task # 72 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15
lola: result : false
lola: markings : 277
lola: fired transitions : 385
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 145 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 142 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08 (obsolete)
lola: CANCELED task # 143 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08 (obsolete)
lola: LAUNCH task # 104 (type EXCL) for 15 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SRCH) for 39 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 142 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-143.sara.
lola: FINISHED task # 104 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05
lola: result : true
lola: markings : 108
lola: fired transitions : 107
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 125 (type EXCL) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
lola: time limit : 326 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: result : true
lola: markings : 37
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 55 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13 (obsolete)
lola: CANCELED task # 56 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 0 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 0 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SRCH) for 0 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 143 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: result : true
lola: fired transitions : 35
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 96 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
lola: result : false
lola: markings : 8534
lola: fired transitions : 11473
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 93 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 94 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00 (obsolete)
lola: LAUNCH task # 128 (type FNDP) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 129 (type EQUN) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 131 (type SRCH) for 6 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 93 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00
lola: result : unknown
lola: fired transitions : 12560
lola: tried executions : 2303
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 131 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: result : true
lola: markings : 18
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 128 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: result : true
lola: fired transitions : 16
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 129 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02 (obsolete)
lola: LAUNCH task # 82 (type FNDP) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type EQUN) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SRCH) for 27 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 106 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: result : false
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 82 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09 (obsolete)
lola: CANCELED task # 86 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09 (obsolete)
lola: LAUNCH task # 115 (type FNDP) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SRCH) for 12 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 82 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: result : unknown
lola: fired transitions : 1531
lola: tried executions : 767
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 115 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04
lola: result : true
lola: fired transitions : 49
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 116 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04 (obsolete)
lola: CANCELED task # 118 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04 (obsolete)
lola: LAUNCH task # 108 (type FNDP) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 109 (type EQUN) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type SRCH) for 9 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-86.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-129.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
lola: FINISHED task # 56 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-109.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-116.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 2/449 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 105108 t fired, 477 attempts, .
109 EF STEQ 2/449 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 sara is running.
111 EF SRCH 2/449 1/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 48004 m, 9600 m/sec, 89922 t fired, .
125 EF EXCL 2/598 1/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 25067 m, 5013 m/sec, 35551 t fired, .
Time elapsed: 10 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 7/447 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 502249 t fired, 2208 attempts, .
109 EF STEQ 7/447 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 sara is running.
111 EF SRCH 7/447 2/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 244386 m, 39276 m/sec, 469433 t fired, .
125 EF EXCL 7/598 1/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 88821 m, 12750 m/sec, 127478 t fired, .
Time elapsed: 15 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 12/442 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 894529 t fired, 3893 attempts, .
109 EF STEQ 12/442 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 sara is running.
111 EF SRCH 12/442 3/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 401737 m, 31470 m/sec, 850058 t fired, .
125 EF EXCL 12/598 1/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 156381 m, 13512 m/sec, 223711 t fired, .
Time elapsed: 20 secs. Pages in use: 4
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 86 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 17/436 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 1324585 t fired, 5738 attempts, .
109 EF STEQ 17/436 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 sara is running.
111 EF SRCH 17/436 4/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 606249 m, 40902 m/sec, 1251348 t fired, .
125 EF EXCL 17/598 2/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 222019 m, 13127 m/sec, 319364 t fired, .
Time elapsed: 25 secs. Pages in use: 6
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 129 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG 0 5 0 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
108 EF FNDP 22/430 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 1803293 t fired, 7785 attempts, .
109 EF STEQ 22/430 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 sara is running.
111 EF SRCH 22/430 5/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 852457 m, 49241 m/sec, 1761963 t fired, .
125 EF EXCL 22/598 2/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 295850 m, 14766 m/sec, 427472 t fired, .
Time elapsed: 30 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 111 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 (memory limit exceeded)
lola: FINISHED task # 109 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
lola: result : false
lola: CANCELED task # 108 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03 (obsolete)
lola: LAUNCH task # 85 (type FNDP) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 42 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 108 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03
lola: result : unknown
lola: fired transitions : 1941621
lola: tried executions : 8376
lola: time used : 23.000000
lola: memory pages used : 0
lola: FINISHED task # 85 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14
lola: result : true
lola: fired transitions : 180
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 88 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14 (obsolete)
lola: CANCELED task # 90 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 76 (type FNDP) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SRCH) for 33 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-77.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-88.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 77 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
lola: result : false
lola: CANCELED task # 76 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11 (obsolete)
lola: CANCELED task # 79 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11 (obsolete)
lola: LAUNCH task # 64 (type FNDP) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 3 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11
lola: result : unknown
lola: fired transitions : 578643
lola: tried executions : 2427
lola: time used : 3.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-65.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG true state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG true state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG 0 2 3 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF 0 4 1 0 1 0 0 0
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EF FNDP 1/891 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 32644 t fired, 6341 attempts, .
65 EF STEQ 1/891 0/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 sara is running.
67 EF SRCH 1/891 1/5 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 22450 m, 4490 m/sec, 24581 t fired, .
125 EF EXCL 27/1197 3/32 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 376477 m, 16125 m/sec, 544169 t fired, .
Time elapsed: 35 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 67 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: result : false
lola: markings : 42475
lola: fired transitions : 51022
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 (obsolete)
lola: CANCELED task # 65 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01 (obsolete)
lola: LAUNCH task # 135 (type FNDP) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 136 (type EQUN) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 138 (type SRCH) for 30 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 138 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 135 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10 (obsolete)
lola: CANCELED task # 136 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10 (obsolete)
lola: LAUNCH task # 121 (type FNDP) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 122 (type EQUN) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 124 (type SRCH) for 21 HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: result : unknown
lola: fired transitions : 53942
lola: tried executions : 10454
lola: time used : 1.000000
lola: memory pages used : 0
lola: FINISHED task # 65 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01
lola: result : unknown
lola: FINISHED task # 135 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: result : true
lola: fired transitions : 9
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-136.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 136 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10
lola: result : true
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-122.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 122 (type EQUN) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07
lola: result : false
lola: CANCELED task # 121 (type FNDP) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 (obsolete)
lola: CANCELED task # 124 (type SRCH) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 (obsolete)
lola: CANCELED task # 125 (type EXCL) for HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-00: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-01: AG true tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-02: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-03: AG true state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-04: EF true findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-05: AG false tandem / relaxed
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-06: INITIAL true preprocessing
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-07: EF false state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-08: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-09: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-10: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-11: AG true state equation
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-12: EF false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-13: AG false tandem / insertion
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-14: AG false findpath
HirschbergSinclair-PT-45-ReachabilityCardinality-2024-15: AG true tandem / relaxed
Time elapsed: 37 secs. Pages in use: 7
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-45"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="gold2023"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool gold2023"
echo " Input is HirschbergSinclair-PT-45, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r219-smll-171649597900079"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-45.tgz
mv HirschbergSinclair-PT-45 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;