fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r219-smll-171649597800049
Last Updated
July 7, 2024

About the Execution of 2023-gold for HirschbergSinclair-PT-15

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
325.892 19929.00 46216.00 528.30 FTFTFFFTFTFFTTTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r219-smll-171649597800049.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool gold2023
Input is HirschbergSinclair-PT-15, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r219-smll-171649597800049
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 696K
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.4K May 19 07:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 19 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 19 07:18 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 22K Apr 13 03:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Apr 13 03:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 03:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Apr 13 03:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 173K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-01
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-02
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-03
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-04
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-05
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-06
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-08
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-09
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-10
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-11
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-12
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-13
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-14
FORMULA_NAME HirschbergSinclair-PT-15-ReachabilityCardinality-2024-15

=== Now, execution of the tool begins

BK_START 1716641236166

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=gold2023
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=HirschbergSinclair-PT-15
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2024-05-25 12:47:18] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-05-25 12:47:19] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-25 12:47:19] [INFO ] Load time of PNML (sax parser for PT used): 96 ms
[2024-05-25 12:47:19] [INFO ] Transformed 330 places.
[2024-05-25 12:47:19] [INFO ] Transformed 296 transitions.
[2024-05-25 12:47:19] [INFO ] Parsed PT model containing 330 places and 296 transitions and 906 arcs in 202 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 31 ms.
Working with output stream class java.io.PrintStream
Incomplete random walk after 10000 steps, including 33 resets, run finished after 708 ms. (steps per millisecond=14 ) properties (out of 16) seen :6
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-14 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-09 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 90 ms. (steps per millisecond=111 ) properties (out of 10) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 79 ms. (steps per millisecond=126 ) properties (out of 10) seen :1
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-02 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 128 ms. (steps per millisecond=78 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 101 ms. (steps per millisecond=99 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 78 ms. (steps per millisecond=128 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 68 ms. (steps per millisecond=147 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 67 ms. (steps per millisecond=149 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
// Phase 1: matrix 296 rows 330 cols
[2024-05-25 12:47:20] [INFO ] Computed 34 invariants in 17 ms
[2024-05-25 12:47:21] [INFO ] After 429ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:9
[2024-05-25 12:47:21] [INFO ] [Nat]Absence check using 30 positive place invariants in 22 ms returned sat
[2024-05-25 12:47:21] [INFO ] [Nat]Absence check using 30 positive and 4 generalized place invariants in 2 ms returned sat
[2024-05-25 12:47:22] [INFO ] After 533ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :4
[2024-05-25 12:47:22] [INFO ] Deduced a trap composed of 11 places in 153 ms of which 8 ms to minimize.
[2024-05-25 12:47:22] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 196 ms
[2024-05-25 12:47:22] [INFO ] Deduced a trap composed of 34 places in 143 ms of which 1 ms to minimize.
[2024-05-25 12:47:22] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 1 trap constraints in 174 ms
[2024-05-25 12:47:23] [INFO ] Deduced a trap composed of 16 places in 137 ms of which 1 ms to minimize.
[2024-05-25 12:47:23] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 171 ms
[2024-05-25 12:47:23] [INFO ] Deduced a trap composed of 14 places in 164 ms of which 2 ms to minimize.
[2024-05-25 12:47:23] [INFO ] Deduced a trap composed of 23 places in 169 ms of which 2 ms to minimize.
[2024-05-25 12:47:23] [INFO ] Trap strengthening procedure managed to obtain unsat after adding 2 trap constraints in 385 ms
[2024-05-25 12:47:23] [INFO ] After 1723ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :2
Attempting to minimize the solution found.
Minimization took 146 ms.
[2024-05-25 12:47:23] [INFO ] After 2212ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :2
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-15 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-13 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-12 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-11 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-08 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-06 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-04 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 9 Parikh solutions to 2 different solutions.
Parikh walk visited 0 properties in 13 ms.
Support contains 58 out of 330 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 330/330 places, 296/296 transitions.
Graph (complete) has 628 edges and 330 vertex of which 312 are kept as prefixes of interest. Removing 18 places using SCC suffix rule.2 ms
Discarding 18 places :
Also discarding 0 output transitions
Drop transitions removed 5 transitions
Reduce isomorphic transitions removed 5 transitions.
Drop transitions removed 63 transitions
Trivial Post-agglo rules discarded 63 transitions
Performed 63 trivial Post agglomeration. Transition count delta: 63
Iterating post reduction 0 with 68 rules applied. Total rules applied 69 place count 312 transition count 228
Reduce places removed 63 places and 0 transitions.
Graph (complete) has 439 edges and 249 vertex of which 234 are kept as prefixes of interest. Removing 15 places using SCC suffix rule.1 ms
Discarding 15 places :
Also discarding 0 output transitions
Performed 15 Post agglomeration using F-continuation condition.Transition count delta: 15
Iterating post reduction 1 with 79 rules applied. Total rules applied 148 place count 234 transition count 213
Reduce places removed 15 places and 0 transitions.
Drop transitions removed 15 transitions
Reduce isomorphic transitions removed 15 transitions.
Iterating post reduction 2 with 30 rules applied. Total rules applied 178 place count 219 transition count 198
Discarding 3 places :
Symmetric choice reduction at 3 with 3 rule applications. Total rules 181 place count 216 transition count 195
Iterating global reduction 3 with 3 rules applied. Total rules applied 184 place count 216 transition count 195
Discarding 2 places :
Symmetric choice reduction at 3 with 2 rule applications. Total rules 186 place count 214 transition count 193
Iterating global reduction 3 with 2 rules applied. Total rules applied 188 place count 214 transition count 193
Free-agglomeration rule (complex) applied 20 times.
Iterating global reduction 3 with 20 rules applied. Total rules applied 208 place count 214 transition count 173
Reduce places removed 20 places and 0 transitions.
Iterating post reduction 3 with 20 rules applied. Total rules applied 228 place count 194 transition count 173
Reduce places removed 8 places and 8 transitions.
Iterating global reduction 4 with 8 rules applied. Total rules applied 236 place count 186 transition count 165
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 237 place count 185 transition count 165
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 4 Pre rules applied. Total rules applied 237 place count 185 transition count 161
Deduced a syphon composed of 4 places in 1 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 5 with 8 rules applied. Total rules applied 245 place count 181 transition count 161
Applied a total of 245 rules in 128 ms. Remains 181 /330 variables (removed 149) and now considering 161/296 (removed 135) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 128 ms. Remains : 181/330 places, 161/296 transitions.
Incomplete random walk after 10000 steps, including 60 resets, run finished after 116 ms. (steps per millisecond=86 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 12 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 2) seen :0
Incomplete Best-First random walk after 10001 steps, including 11 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 2) seen :0
Interrupted probabilistic random walk after 459343 steps, run timeout after 3001 ms. (steps per millisecond=153 ) properties seen :{}
Probabilistic random walk after 459343 steps, saw 98329 distinct states, run finished after 3003 ms. (steps per millisecond=152 ) properties seen :0
Running SMT prover for 2 properties.
// Phase 1: matrix 161 rows 181 cols
[2024-05-25 12:47:27] [INFO ] Computed 20 invariants in 3 ms
[2024-05-25 12:47:27] [INFO ] After 62ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2024-05-25 12:47:27] [INFO ] [Nat]Absence check using 6 positive place invariants in 2 ms returned sat
[2024-05-25 12:47:27] [INFO ] [Nat]Absence check using 6 positive and 14 generalized place invariants in 16 ms returned sat
[2024-05-25 12:47:27] [INFO ] After 155ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2024-05-25 12:47:27] [INFO ] State equation strengthened by 30 read => feed constraints.
[2024-05-25 12:47:27] [INFO ] After 88ms SMT Verify possible using 30 Read/Feed constraints in natural domain returned unsat :0 sat :2
[2024-05-25 12:47:27] [INFO ] Deduced a trap composed of 15 places in 56 ms of which 1 ms to minimize.
[2024-05-25 12:47:27] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 78 ms
[2024-05-25 12:47:27] [INFO ] After 231ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 63 ms.
[2024-05-25 12:47:27] [INFO ] After 540ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Parikh walk visited 0 properties in 7 ms.
Support contains 58 out of 181 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 181/181 places, 161/161 transitions.
Applied a total of 0 rules in 9 ms. Remains 181 /181 variables (removed 0) and now considering 161/161 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 181/181 places, 161/161 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 181/181 places, 161/161 transitions.
Applied a total of 0 rules in 8 ms. Remains 181 /181 variables (removed 0) and now considering 161/161 (removed 0) transitions.
[2024-05-25 12:47:27] [INFO ] Invariant cache hit.
[2024-05-25 12:47:27] [INFO ] Implicit Places using invariants in 146 ms returned []
[2024-05-25 12:47:27] [INFO ] Invariant cache hit.
[2024-05-25 12:47:27] [INFO ] State equation strengthened by 30 read => feed constraints.
[2024-05-25 12:47:28] [INFO ] Implicit Places using invariants and state equation in 345 ms returned []
Implicit Place search using SMT with State Equation took 496 ms to find 0 implicit places.
[2024-05-25 12:47:28] [INFO ] Redundant transitions in 6 ms returned []
[2024-05-25 12:47:28] [INFO ] Invariant cache hit.
[2024-05-25 12:47:28] [INFO ] Dead Transitions using invariants and state equation in 186 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 702 ms. Remains : 181/181 places, 161/161 transitions.
Drop transitions removed 21 transitions
Trivial Post-agglo rules discarded 21 transitions
Performed 21 trivial Post agglomeration. Transition count delta: 21
Iterating post reduction 0 with 21 rules applied. Total rules applied 21 place count 181 transition count 140
Reduce places removed 21 places and 0 transitions.
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Iterating post reduction 1 with 28 rules applied. Total rules applied 49 place count 160 transition count 133
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 2 with 7 rules applied. Total rules applied 56 place count 153 transition count 133
Performed 15 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 15 Pre rules applied. Total rules applied 56 place count 153 transition count 118
Deduced a syphon composed of 15 places in 0 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 3 with 30 rules applied. Total rules applied 86 place count 138 transition count 118
Discarding 1 places :
Implicit places reduction removed 1 places
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 3 with 2 rules applied. Total rules applied 88 place count 137 transition count 117
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 4 with 1 rules applied. Total rules applied 89 place count 136 transition count 117
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 5 with 1 Pre rules applied. Total rules applied 89 place count 136 transition count 116
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 91 place count 135 transition count 116
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 5 with 2 rules applied. Total rules applied 93 place count 134 transition count 115
Applied a total of 93 rules in 24 ms. Remains 134 /181 variables (removed 47) and now considering 115/161 (removed 46) transitions.
Running SMT prover for 2 properties.
// Phase 1: matrix 115 rows 134 cols
[2024-05-25 12:47:28] [INFO ] Computed 19 invariants in 1 ms
[2024-05-25 12:47:28] [INFO ] After 43ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2024-05-25 12:47:28] [INFO ] [Nat]Absence check using 6 positive place invariants in 1 ms returned sat
[2024-05-25 12:47:28] [INFO ] [Nat]Absence check using 6 positive and 13 generalized place invariants in 10 ms returned sat
[2024-05-25 12:47:28] [INFO ] After 101ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2024-05-25 12:47:28] [INFO ] Deduced a trap composed of 8 places in 29 ms of which 1 ms to minimize.
[2024-05-25 12:47:28] [INFO ] Trap strengthening (SAT) tested/added 2/1 trap constraints in 44 ms
[2024-05-25 12:47:28] [INFO ] After 201ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 71 ms.
[2024-05-25 12:47:28] [INFO ] After 337ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
[2024-05-25 12:47:28] [INFO ] Export to MCC of 2 properties in file /home/mcc/execution/ReachabilityCardinality.sr.xml took 5 ms.
[2024-05-25 12:47:28] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 181 places, 161 transitions and 549 arcs took 3 ms.
[2024-05-25 12:47:29] [INFO ] Flatten gal took : 62 ms
Total runtime 10064 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT HirschbergSinclair-PT-15
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/363
ReachabilityCardinality

FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1716641256095

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/363/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/363/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/363/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 11 (type EXCL) for 0 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 7 (type FNDP) for 0 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 8 (type EQUN) for 0 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 10 (type SRCH) for 0 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 10 (type SRCH) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: result : true
lola: markings : 277
lola: fired transitions : 302
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 7 (type FNDP) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 8 (type EQUN) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 11 (type EXCL) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00 (obsolete)
lola: FINISHED task # 7 (type FNDP) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: result : true
lola: fired transitions : 113
lola: tried executions : 5
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 17 (type EXCL) for 3 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 13 (type FNDP) for 3 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 14 (type EQUN) for 3 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 16 (type SRCH) for 3 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/363/ReachabilityCardinality-8.sara.
sara: try reading problem file /home/mcc/execution/363/ReachabilityCardinality-14.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 8 (type EQUN) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00
lola: result : true

lola: FINISHED task # 14 (type EQUN) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: result : unknown
lola: LAUNCH task # 18 (type SRCH) for 3 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 18 (type SRCH) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00: AG false tandem / insertion

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07: EF 0 0 3 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 EF FNDP 5/3600 0/5 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 1931419 t fired, 14839 attempts, .
16 EF SRCH 5/3600 4/5 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 949372 m, 189874 m/sec, 2026128 t fired, .
17 EF EXCL 5/3600 3/32 HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 486670 m, 97334 m/sec, 920815 t fired, .

Time elapsed: 5 secs. Pages in use: 7
# running tasks: 3 of 4 Visible: 2
lola: FINISHED task # 16 (type SRCH) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07
lola: result : true
lola: markings : 1091686
lola: fired transitions : 2377203
lola: time used : 6.000000
lola: memory pages used : 5
lola: CANCELED task # 13 (type FNDP) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 (obsolete)
lola: CANCELED task # 17 (type EXCL) for HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
HirschbergSinclair-PT-15-ReachabilityCardinality-2024-00: AG false tandem / insertion
HirschbergSinclair-PT-15-ReachabilityCardinality-2024-07: EF true tandem / insertion


Time elapsed: 6 secs. Pages in use: 8

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-15"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="gold2023"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool gold2023"
echo " Input is HirschbergSinclair-PT-15, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r219-smll-171649597800049"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-15.tgz
mv HirschbergSinclair-PT-15 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;