About the Execution of LoLA for HirschbergSinclair-PT-15
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16208.812 | 1851541.00 | 1692415.00 | 5441.50 | ???????????T???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r203-smll-171649588300076.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is HirschbergSinclair-PT-15, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r203-smll-171649588300076
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 696K
-rw-r--r-- 1 mcc users 11K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 86K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 5.4K May 19 07:10 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 19 15:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K May 19 07:18 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:27 LTLFireability.xml
-rw-r--r-- 1 mcc users 22K Apr 13 03:06 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 166K Apr 13 03:06 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 13 03:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Apr 13 03:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:48 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Apr 22 14:48 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 173K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-00
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-01
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-02
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-03
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-04
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-05
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-06
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-07
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-08
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-09
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-10
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-11
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-12
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-13
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-14
FORMULA_NAME HirschbergSinclair-PT-15-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717074881380
FORMULA HirschbergSinclair-PT-15-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717076732921
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 34 (type EXCL) for 33 HirschbergSinclair-PT-15-LTLFireability-11
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 34 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 0 HirschbergSinclair-PT-15-LTLFireability-00
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 0 HirschbergSinclair-PT-15-LTLFireability-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 65 (type EQUN) for 49 HirschbergSinclair-PT-15-LTLFireability-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 24 HirschbergSinclair-PT-15-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for HirschbergSinclair-PT-15-LTLFireability-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for HirschbergSinclair-PT-15-LTLFireability-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 65 (type EQUN) for HirschbergSinclair-PT-15-LTLFireability-15
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 5/211 3/2000 HirschbergSinclair-PT-15-LTLFireability-00 635409 m, 127081 m/sec, 1647103 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 10/211 6/2000 HirschbergSinclair-PT-15-LTLFireability-00 1272145 m, 127347 m/sec, 3408137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 15/211 8/2000 HirschbergSinclair-PT-15-LTLFireability-00 1846880 m, 114947 m/sec, 5170545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 20/211 10/2000 HirschbergSinclair-PT-15-LTLFireability-00 2435463 m, 117716 m/sec, 6907860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 25/211 13/2000 HirschbergSinclair-PT-15-LTLFireability-00 3026938 m, 118295 m/sec, 8664935 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 30/211 15/2000 HirschbergSinclair-PT-15-LTLFireability-00 3596929 m, 113998 m/sec, 10410648 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 35/211 17/2000 HirschbergSinclair-PT-15-LTLFireability-00 4120840 m, 104782 m/sec, 12159299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 40/211 19/2000 HirschbergSinclair-PT-15-LTLFireability-00 4631941 m, 102220 m/sec, 13868007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 45/211 21/2000 HirschbergSinclair-PT-15-LTLFireability-00 5239519 m, 121515 m/sec, 15632434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 50/211 24/2000 HirschbergSinclair-PT-15-LTLFireability-00 5802952 m, 112686 m/sec, 17364895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 55/211 26/2000 HirschbergSinclair-PT-15-LTLFireability-00 6326274 m, 104664 m/sec, 19107074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 60/211 28/2000 HirschbergSinclair-PT-15-LTLFireability-00 6857692 m, 106283 m/sec, 20810016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 65/211 30/2000 HirschbergSinclair-PT-15-LTLFireability-00 7434144 m, 115290 m/sec, 22564632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 70/211 32/2000 HirschbergSinclair-PT-15-LTLFireability-00 7984209 m, 110013 m/sec, 24287899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 75/211 35/2000 HirschbergSinclair-PT-15-LTLFireability-00 8538196 m, 110797 m/sec, 26036869 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 80/211 37/2000 HirschbergSinclair-PT-15-LTLFireability-00 9069260 m, 106212 m/sec, 27732791 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 37
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 85/211 39/2000 HirschbergSinclair-PT-15-LTLFireability-00 9589726 m, 104093 m/sec, 29469018 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 90/211 41/2000 HirschbergSinclair-PT-15-LTLFireability-00 10106423 m, 103339 m/sec, 31196389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 95/211 43/2000 HirschbergSinclair-PT-15-LTLFireability-00 10608756 m, 100466 m/sec, 32909849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 100/211 45/2000 HirschbergSinclair-PT-15-LTLFireability-00 11081598 m, 94568 m/sec, 34630052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 105/211 46/2000 HirschbergSinclair-PT-15-LTLFireability-00 11557362 m, 95152 m/sec, 36319321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 110/211 49/2000 HirschbergSinclair-PT-15-LTLFireability-00 12079949 m, 104517 m/sec, 38053180 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 115/211 51/2000 HirschbergSinclair-PT-15-LTLFireability-00 12586057 m, 101221 m/sec, 39755388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 120/211 53/2000 HirschbergSinclair-PT-15-LTLFireability-00 13087637 m, 100316 m/sec, 41490035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 125/211 54/2000 HirschbergSinclair-PT-15-LTLFireability-00 13549183 m, 92309 m/sec, 43185037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 130/211 56/2000 HirschbergSinclair-PT-15-LTLFireability-00 14009306 m, 92024 m/sec, 44870464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 135/211 57/2000 HirschbergSinclair-PT-15-LTLFireability-00 14347078 m, 67554 m/sec, 46398085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 140/211 59/2000 HirschbergSinclair-PT-15-LTLFireability-00 14635035 m, 57591 m/sec, 47934025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 145/211 60/2000 HirschbergSinclair-PT-15-LTLFireability-00 14915971 m, 56187 m/sec, 49601833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 150/211 61/2000 HirschbergSinclair-PT-15-LTLFireability-00 15196823 m, 56170 m/sec, 51240475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 155/211 63/2000 HirschbergSinclair-PT-15-LTLFireability-00 15669737 m, 94582 m/sec, 53010251 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 160/211 65/2000 HirschbergSinclair-PT-15-LTLFireability-00 16248294 m, 115711 m/sec, 54758317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 165/211 67/2000 HirschbergSinclair-PT-15-LTLFireability-00 16801386 m, 110618 m/sec, 56502690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 170/211 69/2000 HirschbergSinclair-PT-15-LTLFireability-00 17313103 m, 102343 m/sec, 58221447 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 175/211 71/2000 HirschbergSinclair-PT-15-LTLFireability-00 17832888 m, 103957 m/sec, 59928253 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 180/211 73/2000 HirschbergSinclair-PT-15-LTLFireability-00 18371403 m, 107703 m/sec, 61653690 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 185/211 75/2000 HirschbergSinclair-PT-15-LTLFireability-00 18874820 m, 100683 m/sec, 63357629 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 75
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 190/211 77/2000 HirschbergSinclair-PT-15-LTLFireability-00 19356978 m, 96431 m/sec, 65067245 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 195/211 79/2000 HirschbergSinclair-PT-15-LTLFireability-00 19838384 m, 96281 m/sec, 66735147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 200/211 81/2000 HirschbergSinclair-PT-15-LTLFireability-00 20316312 m, 95585 m/sec, 68444456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 205/211 83/2000 HirschbergSinclair-PT-15-LTLFireability-00 20831412 m, 103020 m/sec, 70155519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 210/211 85/2000 HirschbergSinclair-PT-15-LTLFireability-00 21337284 m, 101174 m/sec, 71852369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 57 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-00 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 1 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-15: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 49 HirschbergSinclair-PT-15-LTLFireability-15
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 0 HirschbergSinclair-PT-15-LTLFireability-00
[[35mlola[0m][I] time limit : 3385 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 101314
[[35mlola[0m][I] fired transitions : 367123
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 1 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 57 EG EXCL 5/225 3/5 HirschbergSinclair-PT-15-LTLFireability-00 647494 m, -4137958 m/sec, 1698817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 57 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-00 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-12: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 HirschbergSinclair-PT-15-LTLFireability-14
[[35mlola[0m][I] time limit : 241 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 380
[[35mlola[0m][I] fired transitions : 380
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 HirschbergSinclair-PT-15-LTLFireability-13
[[35mlola[0m][I] time limit : 259 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 275
[[35mlola[0m][I] fired transitions : 275
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 36 HirschbergSinclair-PT-15-LTLFireability-12
[[35mlola[0m][I] time limit : 281 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 39 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 275
[[35mlola[0m][I] fired transitions : 275
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 HirschbergSinclair-PT-15-LTLFireability-09
[[35mlola[0m][I] time limit : 337 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 5/337 5/2000 HirschbergSinclair-PT-15-LTLFireability-09 543323 m, 108664 m/sec, 1913979 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 92
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 10/337 8/2000 HirschbergSinclair-PT-15-LTLFireability-09 1053254 m, 101986 m/sec, 3819804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 15/337 12/2000 HirschbergSinclair-PT-15-LTLFireability-09 1500621 m, 89473 m/sec, 5682625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 20/337 15/2000 HirschbergSinclair-PT-15-LTLFireability-09 1960084 m, 91892 m/sec, 7550157 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 102
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 25/337 18/2000 HirschbergSinclair-PT-15-LTLFireability-09 2398993 m, 87781 m/sec, 9378934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 105
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 30/337 21/2000 HirschbergSinclair-PT-15-LTLFireability-09 2751411 m, 70483 m/sec, 11314703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 35/337 23/2000 HirschbergSinclair-PT-15-LTLFireability-09 3017357 m, 53189 m/sec, 13296702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 40/337 25/2000 HirschbergSinclair-PT-15-LTLFireability-09 3265109 m, 49550 m/sec, 15278584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 45/337 26/2000 HirschbergSinclair-PT-15-LTLFireability-09 3504391 m, 47856 m/sec, 17241061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 50/337 28/2000 HirschbergSinclair-PT-15-LTLFireability-09 3738764 m, 46874 m/sec, 19174138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 55/337 31/2000 HirschbergSinclair-PT-15-LTLFireability-09 4062525 m, 64752 m/sec, 21065306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 60/337 34/2000 HirschbergSinclair-PT-15-LTLFireability-09 4509156 m, 89326 m/sec, 22909924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 65/337 37/2000 HirschbergSinclair-PT-15-LTLFireability-09 4912491 m, 80667 m/sec, 24735853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 70/337 40/2000 HirschbergSinclair-PT-15-LTLFireability-09 5310999 m, 79701 m/sec, 26522917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 75/337 42/2000 HirschbergSinclair-PT-15-LTLFireability-09 5579813 m, 53762 m/sec, 28443276 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 80/337 43/2000 HirschbergSinclair-PT-15-LTLFireability-09 5801179 m, 44273 m/sec, 30377813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 85/337 45/2000 HirschbergSinclair-PT-15-LTLFireability-09 6014812 m, 42726 m/sec, 32292722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 90/337 48/2000 HirschbergSinclair-PT-15-LTLFireability-09 6360742 m, 69186 m/sec, 34151838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 95/337 51/2000 HirschbergSinclair-PT-15-LTLFireability-09 6804344 m, 88720 m/sec, 35942924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 100/337 54/2000 HirschbergSinclair-PT-15-LTLFireability-09 7242382 m, 87607 m/sec, 37720560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 141
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 105/337 57/2000 HirschbergSinclair-PT-15-LTLFireability-09 7645031 m, 80529 m/sec, 39499225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 110/337 60/2000 HirschbergSinclair-PT-15-LTLFireability-09 8035824 m, 78158 m/sec, 41258879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 115/337 63/2000 HirschbergSinclair-PT-15-LTLFireability-09 8442183 m, 81271 m/sec, 43031891 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 120/337 65/2000 HirschbergSinclair-PT-15-LTLFireability-09 8826504 m, 76864 m/sec, 44769845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 125/337 68/2000 HirschbergSinclair-PT-15-LTLFireability-09 9204429 m, 75585 m/sec, 46497865 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 130/337 70/2000 HirschbergSinclair-PT-15-LTLFireability-09 9470631 m, 53240 m/sec, 48383981 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 135/337 72/2000 HirschbergSinclair-PT-15-LTLFireability-09 9703660 m, 46605 m/sec, 50255265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 140/337 74/2000 HirschbergSinclair-PT-15-LTLFireability-09 9927066 m, 44681 m/sec, 52151205 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 145/337 75/2000 HirschbergSinclair-PT-15-LTLFireability-09 10134388 m, 41464 m/sec, 54014803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 150/337 77/2000 HirschbergSinclair-PT-15-LTLFireability-09 10344836 m, 42089 m/sec, 55895761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 155/337 78/2000 HirschbergSinclair-PT-15-LTLFireability-09 10553478 m, 41728 m/sec, 57752332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 160/337 80/2000 HirschbergSinclair-PT-15-LTLFireability-09 10757146 m, 40733 m/sec, 59582542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 167
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 165/337 82/2000 HirschbergSinclair-PT-15-LTLFireability-09 11141582 m, 76887 m/sec, 61371849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 170/337 85/2000 HirschbergSinclair-PT-15-LTLFireability-09 11558899 m, 83463 m/sec, 63111785 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 175/337 88/2000 HirschbergSinclair-PT-15-LTLFireability-09 11920237 m, 72267 m/sec, 64886512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 180/337 90/2000 HirschbergSinclair-PT-15-LTLFireability-09 12148037 m, 45560 m/sec, 66752164 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 185/337 91/2000 HirschbergSinclair-PT-15-LTLFireability-09 12389419 m, 48276 m/sec, 68582372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 190/337 94/2000 HirschbergSinclair-PT-15-LTLFireability-09 12792775 m, 80671 m/sec, 70359783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 195/337 96/2000 HirschbergSinclair-PT-15-LTLFireability-09 13072406 m, 55926 m/sec, 72192772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 200/337 98/2000 HirschbergSinclair-PT-15-LTLFireability-09 13331050 m, 51728 m/sec, 74013974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 185
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 205/337 101/2000 HirschbergSinclair-PT-15-LTLFireability-09 13745597 m, 82909 m/sec, 75756115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 188
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 210/337 104/2000 HirschbergSinclair-PT-15-LTLFireability-09 14125103 m, 75901 m/sec, 77498898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 215/337 107/2000 HirschbergSinclair-PT-15-LTLFireability-09 14476873 m, 70354 m/sec, 79197779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 220/337 108/2000 HirschbergSinclair-PT-15-LTLFireability-09 14700645 m, 44754 m/sec, 81050883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 195
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 225/337 110/2000 HirschbergSinclair-PT-15-LTLFireability-09 14901861 m, 40243 m/sec, 82894015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 230/337 112/2000 HirschbergSinclair-PT-15-LTLFireability-09 15145329 m, 48693 m/sec, 84711192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 235/337 115/2000 HirschbergSinclair-PT-15-LTLFireability-09 15579775 m, 86889 m/sec, 86558720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 240/337 117/2000 HirschbergSinclair-PT-15-LTLFireability-09 15814623 m, 46969 m/sec, 88491598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 245/337 120/2000 HirschbergSinclair-PT-15-LTLFireability-09 16169493 m, 70974 m/sec, 90337570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 250/337 122/2000 HirschbergSinclair-PT-15-LTLFireability-09 16496929 m, 65487 m/sec, 92224696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 255/337 125/2000 HirschbergSinclair-PT-15-LTLFireability-09 16881521 m, 76918 m/sec, 94023845 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 260/337 127/2000 HirschbergSinclair-PT-15-LTLFireability-09 17102978 m, 44291 m/sec, 95950211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 265/337 130/2000 HirschbergSinclair-PT-15-LTLFireability-09 17445814 m, 68567 m/sec, 97762191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 270/337 132/2000 HirschbergSinclair-PT-15-LTLFireability-09 17852776 m, 81392 m/sec, 99515310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 219
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 275/337 134/2000 HirschbergSinclair-PT-15-LTLFireability-09 18094086 m, 48262 m/sec, 101387414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 280/337 136/2000 HirschbergSinclair-PT-15-LTLFireability-09 18385054 m, 58193 m/sec, 103153358 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 285/337 138/2000 HirschbergSinclair-PT-15-LTLFireability-09 18696003 m, 62189 m/sec, 104908191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 225
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 290/337 140/2000 HirschbergSinclair-PT-15-LTLFireability-09 18965126 m, 53824 m/sec, 106706015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 227
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 295/337 143/2000 HirschbergSinclair-PT-15-LTLFireability-09 19344243 m, 75823 m/sec, 108406767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 300/337 145/2000 HirschbergSinclair-PT-15-LTLFireability-09 19682106 m, 67572 m/sec, 110110215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 305/337 146/2000 HirschbergSinclair-PT-15-LTLFireability-09 19889269 m, 41432 m/sec, 111946314 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 310/337 148/2000 HirschbergSinclair-PT-15-LTLFireability-09 20121721 m, 46490 m/sec, 113732099 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 315/337 150/2000 HirschbergSinclair-PT-15-LTLFireability-09 20429027 m, 61461 m/sec, 115512782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 320/337 152/2000 HirschbergSinclair-PT-15-LTLFireability-09 20711678 m, 56530 m/sec, 117301305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 325/337 154/2000 HirschbergSinclair-PT-15-LTLFireability-09 21055271 m, 68718 m/sec, 119046241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 330/337 156/2000 HirschbergSinclair-PT-15-LTLFireability-09 21320706 m, 53087 m/sec, 120848396 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 335/337 158/2000 HirschbergSinclair-PT-15-LTLFireability-09 21624140 m, 60686 m/sec, 122680163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 245
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 28 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 HirschbergSinclair-PT-15-LTLFireability-07
[[35mlola[0m][I] time limit : 337 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 HirschbergSinclair-PT-15-LTLFireability-09
[[35mlola[0m][I] time limit : 3035 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 22 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 275
[[35mlola[0m][I] fired transitions : 275
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 LTL EXCL 5/337 4/5 HirschbergSinclair-PT-15-LTLFireability-09 524876 m, -4219852 m/sec, 1844431 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 28 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 HirschbergSinclair-PT-15-LTLFireability-06
[[35mlola[0m][I] time limit : 378 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 5/378 5/2000 HirschbergSinclair-PT-15-LTLFireability-06 561610 m, 112322 m/sec, 1569544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 10/378 9/2000 HirschbergSinclair-PT-15-LTLFireability-06 1086138 m, 104905 m/sec, 3124600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 15/378 13/2000 HirschbergSinclair-PT-15-LTLFireability-06 1595857 m, 101943 m/sec, 4677547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 20/378 16/2000 HirschbergSinclair-PT-15-LTLFireability-06 2032642 m, 87357 m/sec, 6191884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 25/378 20/2000 HirschbergSinclair-PT-15-LTLFireability-06 2503918 m, 94255 m/sec, 7700354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 30/378 23/2000 HirschbergSinclair-PT-15-LTLFireability-06 2892581 m, 77732 m/sec, 9100936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 270
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 35/378 26/2000 HirschbergSinclair-PT-15-LTLFireability-06 3302007 m, 81885 m/sec, 10721573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 40/378 29/2000 HirschbergSinclair-PT-15-LTLFireability-06 3702397 m, 80078 m/sec, 12280815 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 276
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 45/378 33/2000 HirschbergSinclair-PT-15-LTLFireability-06 4114994 m, 82519 m/sec, 13829227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 50/378 35/2000 HirschbergSinclair-PT-15-LTLFireability-06 4452362 m, 67473 m/sec, 15293759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 55/378 38/2000 HirschbergSinclair-PT-15-LTLFireability-06 4817412 m, 73010 m/sec, 16836178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 60/378 40/2000 HirschbergSinclair-PT-15-LTLFireability-06 5123502 m, 61218 m/sec, 18351928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 287
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 65/378 43/2000 HirschbergSinclair-PT-15-LTLFireability-06 5478785 m, 71056 m/sec, 19850938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 290
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 70/378 46/2000 HirschbergSinclair-PT-15-LTLFireability-06 5779282 m, 60099 m/sec, 21307457 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 75/378 48/2000 HirschbergSinclair-PT-15-LTLFireability-06 6087368 m, 61617 m/sec, 22782448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 295
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 80/378 51/2000 HirschbergSinclair-PT-15-LTLFireability-06 6445249 m, 71576 m/sec, 24251544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 85/378 53/2000 HirschbergSinclair-PT-15-LTLFireability-06 6772909 m, 65532 m/sec, 25622602 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 90/378 56/2000 HirschbergSinclair-PT-15-LTLFireability-06 7113565 m, 68131 m/sec, 26959521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 95/378 60/2000 HirschbergSinclair-PT-15-LTLFireability-06 7606832 m, 98653 m/sec, 28476168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 100/378 63/2000 HirschbergSinclair-PT-15-LTLFireability-06 8039751 m, 86583 m/sec, 29965398 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 105/378 67/2000 HirschbergSinclair-PT-15-LTLFireability-06 8503288 m, 92707 m/sec, 31446753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 110/378 70/2000 HirschbergSinclair-PT-15-LTLFireability-06 8927988 m, 84940 m/sec, 32867363 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 317
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 115/378 73/2000 HirschbergSinclair-PT-15-LTLFireability-06 9396969 m, 93796 m/sec, 34329318 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 120/378 77/2000 HirschbergSinclair-PT-15-LTLFireability-06 9824622 m, 85530 m/sec, 35767154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 324
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 125/378 80/2000 HirschbergSinclair-PT-15-LTLFireability-06 10228269 m, 80729 m/sec, 37218836 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 130/378 83/2000 HirschbergSinclair-PT-15-LTLFireability-06 10620258 m, 78397 m/sec, 38608833 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 330
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 135/378 86/2000 HirschbergSinclair-PT-15-LTLFireability-06 11027494 m, 81447 m/sec, 39974889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 140/378 88/2000 HirschbergSinclair-PT-15-LTLFireability-06 11380291 m, 70559 m/sec, 41276393 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 145/378 91/2000 HirschbergSinclair-PT-15-LTLFireability-06 11684276 m, 60797 m/sec, 42650792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 150/378 94/2000 HirschbergSinclair-PT-15-LTLFireability-06 12034098 m, 69964 m/sec, 44179151 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 155/378 96/2000 HirschbergSinclair-PT-15-LTLFireability-06 12398934 m, 72967 m/sec, 45681281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 343
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 160/378 99/2000 HirschbergSinclair-PT-15-LTLFireability-06 12704309 m, 61075 m/sec, 47182911 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 165/378 102/2000 HirschbergSinclair-PT-15-LTLFireability-06 13031168 m, 65371 m/sec, 48646137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 170/378 104/2000 HirschbergSinclair-PT-15-LTLFireability-06 13316771 m, 57120 m/sec, 50072420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 351
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 175/378 106/2000 HirschbergSinclair-PT-15-LTLFireability-06 13652063 m, 67058 m/sec, 51530259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 353
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 180/378 109/2000 HirschbergSinclair-PT-15-LTLFireability-06 13980862 m, 65759 m/sec, 52933967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 185/378 111/2000 HirschbergSinclair-PT-15-LTLFireability-06 14260035 m, 55834 m/sec, 54258021 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 190/378 113/2000 HirschbergSinclair-PT-15-LTLFireability-06 14577092 m, 63411 m/sec, 55615665 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 195/378 116/2000 HirschbergSinclair-PT-15-LTLFireability-06 14897359 m, 64053 m/sec, 57069695 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 363
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 200/378 118/2000 HirschbergSinclair-PT-15-LTLFireability-06 15227988 m, 66125 m/sec, 58490982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 365
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 205/378 120/2000 HirschbergSinclair-PT-15-LTLFireability-06 15502557 m, 54913 m/sec, 59972771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 367
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 210/378 123/2000 HirschbergSinclair-PT-15-LTLFireability-06 15802829 m, 60054 m/sec, 61380631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 215/378 125/2000 HirschbergSinclair-PT-15-LTLFireability-06 16118506 m, 63135 m/sec, 62811045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 372
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 220/378 127/2000 HirschbergSinclair-PT-15-LTLFireability-06 16396352 m, 55569 m/sec, 64214413 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 225/378 129/2000 HirschbergSinclair-PT-15-LTLFireability-06 16672281 m, 55185 m/sec, 65573300 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 230/378 132/2000 HirschbergSinclair-PT-15-LTLFireability-06 16941901 m, 53924 m/sec, 66999504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 379
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 235/378 134/2000 HirschbergSinclair-PT-15-LTLFireability-06 17270045 m, 65628 m/sec, 68399531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 381
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 240/378 136/2000 HirschbergSinclair-PT-15-LTLFireability-06 17572371 m, 60465 m/sec, 69780365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 383
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 245/378 138/2000 HirschbergSinclair-PT-15-LTLFireability-06 17867586 m, 59043 m/sec, 71093422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 250/378 140/2000 HirschbergSinclair-PT-15-LTLFireability-06 18109966 m, 48476 m/sec, 72276771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 255/378 144/2000 HirschbergSinclair-PT-15-LTLFireability-06 18567874 m, 91581 m/sec, 73722721 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 391
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 260/378 148/2000 HirschbergSinclair-PT-15-LTLFireability-06 19028403 m, 92105 m/sec, 75206329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 395
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 265/378 151/2000 HirschbergSinclair-PT-15-LTLFireability-06 19453938 m, 85107 m/sec, 76690916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 398
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 270/378 154/2000 HirschbergSinclair-PT-15-LTLFireability-06 19852384 m, 79689 m/sec, 78123179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 401
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 275/378 157/2000 HirschbergSinclair-PT-15-LTLFireability-06 20212364 m, 71996 m/sec, 79550495 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 280/378 160/2000 HirschbergSinclair-PT-15-LTLFireability-06 20575859 m, 72699 m/sec, 81067094 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 285/378 163/2000 HirschbergSinclair-PT-15-LTLFireability-06 20916216 m, 68071 m/sec, 82528220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 410
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 290/378 165/2000 HirschbergSinclair-PT-15-LTLFireability-06 21221920 m, 61140 m/sec, 83952490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 412
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 295/378 168/2000 HirschbergSinclair-PT-15-LTLFireability-06 21562377 m, 68091 m/sec, 85425531 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 300/378 170/2000 HirschbergSinclair-PT-15-LTLFireability-06 21849301 m, 57384 m/sec, 86865139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 417
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 305/378 173/2000 HirschbergSinclair-PT-15-LTLFireability-06 22145761 m, 59292 m/sec, 88289565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 420
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 310/378 175/2000 HirschbergSinclair-PT-15-LTLFireability-06 22422406 m, 55329 m/sec, 89694820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 422
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 315/378 177/2000 HirschbergSinclair-PT-15-LTLFireability-06 22716493 m, 58817 m/sec, 91099753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 424
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 320/378 180/2000 HirschbergSinclair-PT-15-LTLFireability-06 23096880 m, 76077 m/sec, 92479681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 427
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 325/378 184/2000 HirschbergSinclair-PT-15-LTLFireability-06 23534106 m, 87445 m/sec, 94021351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 431
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 330/378 187/2000 HirschbergSinclair-PT-15-LTLFireability-06 23948267 m, 82832 m/sec, 95511382 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 335/378 191/2000 HirschbergSinclair-PT-15-LTLFireability-06 24375607 m, 85468 m/sec, 96983701 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 438
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 340/378 194/2000 HirschbergSinclair-PT-15-LTLFireability-06 24800631 m, 85004 m/sec, 98488576 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 441
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 345/378 197/2000 HirschbergSinclair-PT-15-LTLFireability-06 25188197 m, 77513 m/sec, 99977009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 350/378 200/2000 HirschbergSinclair-PT-15-LTLFireability-06 25583013 m, 78963 m/sec, 101421491 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 447
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 355/378 203/2000 HirschbergSinclair-PT-15-LTLFireability-06 25924557 m, 68308 m/sec, 102816649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 450
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 360/378 205/2000 HirschbergSinclair-PT-15-LTLFireability-06 26234311 m, 61950 m/sec, 104324966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 365/378 208/2000 HirschbergSinclair-PT-15-LTLFireability-06 26536104 m, 60358 m/sec, 105819616 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 455
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 370/378 211/2000 HirschbergSinclair-PT-15-LTLFireability-06 26864055 m, 65590 m/sec, 107332884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 458
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 LTL EXCL 375/378 213/2000 HirschbergSinclair-PT-15-LTLFireability-06 27148334 m, 56855 m/sec, 108840405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 460
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 19 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-06 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 463
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 HirschbergSinclair-PT-15-LTLFireability-05
[[35mlola[0m][I] time limit : 377 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 HirschbergSinclair-PT-15-LTLFireability-06
[[35mlola[0m][I] time limit : 2645 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 5/377 5/2000 HirschbergSinclair-PT-15-LTLFireability-05 578282 m, 115656 m/sec, 1810445 t fired, .
[[35mlola[0m][.] 19 LTL EXCL 5/2645 5/5 HirschbergSinclair-PT-15-LTLFireability-06 602165 m, -5309233 m/sec, 1675736 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 19 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-06 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 10/377 9/2000 HirschbergSinclair-PT-15-LTLFireability-05 1137813 m, 111906 m/sec, 3613644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 15/377 13/2000 HirschbergSinclair-PT-15-LTLFireability-05 1625497 m, 97536 m/sec, 5381660 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 476
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 20/377 17/2000 HirschbergSinclair-PT-15-LTLFireability-05 2160622 m, 107025 m/sec, 7185630 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 480
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 25/377 20/2000 HirschbergSinclair-PT-15-LTLFireability-05 2622498 m, 92375 m/sec, 8953438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 483
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 30/377 24/2000 HirschbergSinclair-PT-15-LTLFireability-05 3163004 m, 108101 m/sec, 10729724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 35/377 27/2000 HirschbergSinclair-PT-15-LTLFireability-05 3627040 m, 92807 m/sec, 12502077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 40/377 31/2000 HirschbergSinclair-PT-15-LTLFireability-05 4104149 m, 95421 m/sec, 14254374 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 494
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 45/377 34/2000 HirschbergSinclair-PT-15-LTLFireability-05 4585918 m, 96353 m/sec, 16004466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 497
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 50/377 37/2000 HirschbergSinclair-PT-15-LTLFireability-05 5018755 m, 86567 m/sec, 17741542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 500
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 55/377 40/2000 HirschbergSinclair-PT-15-LTLFireability-05 5433679 m, 82984 m/sec, 19477274 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 503
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 60/377 43/2000 HirschbergSinclair-PT-15-LTLFireability-05 5876541 m, 88572 m/sec, 21193857 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 506
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 65/377 47/2000 HirschbergSinclair-PT-15-LTLFireability-05 6350364 m, 94764 m/sec, 22938996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 510
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 70/377 50/2000 HirschbergSinclair-PT-15-LTLFireability-05 6815132 m, 92953 m/sec, 24677667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 513
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 75/377 53/2000 HirschbergSinclair-PT-15-LTLFireability-05 7234715 m, 83916 m/sec, 26390061 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 80/377 57/2000 HirschbergSinclair-PT-15-LTLFireability-05 7773957 m, 107848 m/sec, 28181769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 520
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 85/377 61/2000 HirschbergSinclair-PT-15-LTLFireability-05 8264212 m, 98051 m/sec, 29979380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 524
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 90/377 64/2000 HirschbergSinclair-PT-15-LTLFireability-05 8713525 m, 89862 m/sec, 31722995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 527
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 95/377 67/2000 HirschbergSinclair-PT-15-LTLFireability-05 9158118 m, 88918 m/sec, 33479316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 530
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 100/377 71/2000 HirschbergSinclair-PT-15-LTLFireability-05 9609574 m, 90291 m/sec, 35209203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 534
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 105/377 74/2000 HirschbergSinclair-PT-15-LTLFireability-05 10040774 m, 86240 m/sec, 36945138 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 537
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 110/377 77/2000 HirschbergSinclair-PT-15-LTLFireability-05 10476043 m, 87053 m/sec, 38671961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 540
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 115/377 80/2000 HirschbergSinclair-PT-15-LTLFireability-05 10893675 m, 83526 m/sec, 40400937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 543
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 120/377 82/2000 HirschbergSinclair-PT-15-LTLFireability-05 11249855 m, 71236 m/sec, 42114088 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 545
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 125/377 85/2000 HirschbergSinclair-PT-15-LTLFireability-05 11645878 m, 79204 m/sec, 43799844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 548
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 130/377 88/2000 HirschbergSinclair-PT-15-LTLFireability-05 12089840 m, 88792 m/sec, 45519732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 551
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 135/377 91/2000 HirschbergSinclair-PT-15-LTLFireability-05 12483490 m, 78730 m/sec, 47224995 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 554
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 140/377 94/2000 HirschbergSinclair-PT-15-LTLFireability-05 12915783 m, 86458 m/sec, 48969849 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 557
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 145/377 97/2000 HirschbergSinclair-PT-15-LTLFireability-05 13369302 m, 90703 m/sec, 50748215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 560
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 150/377 100/2000 HirschbergSinclair-PT-15-LTLFireability-05 13798130 m, 85765 m/sec, 52534155 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 155/377 104/2000 HirschbergSinclair-PT-15-LTLFireability-05 14316176 m, 103609 m/sec, 54288139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 567
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 160/377 108/2000 HirschbergSinclair-PT-15-LTLFireability-05 14756341 m, 88033 m/sec, 56013956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 571
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 165/377 111/2000 HirschbergSinclair-PT-15-LTLFireability-05 15241388 m, 97009 m/sec, 57726049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 170/377 114/2000 HirschbergSinclair-PT-15-LTLFireability-05 15691118 m, 89946 m/sec, 59423700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 577
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 175/377 117/2000 HirschbergSinclair-PT-15-LTLFireability-05 16104564 m, 82689 m/sec, 61108820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 580
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 180/377 120/2000 HirschbergSinclair-PT-15-LTLFireability-05 16501881 m, 79463 m/sec, 62797525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 583
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 185/377 123/2000 HirschbergSinclair-PT-15-LTLFireability-05 16935499 m, 86723 m/sec, 64480380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 586
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 190/377 127/2000 HirschbergSinclair-PT-15-LTLFireability-05 17361368 m, 85173 m/sec, 66195632 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 590
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 195/377 130/2000 HirschbergSinclair-PT-15-LTLFireability-05 17797599 m, 87246 m/sec, 67901243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 593
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 200/377 133/2000 HirschbergSinclair-PT-15-LTLFireability-05 18198354 m, 80151 m/sec, 69581489 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 596
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 205/377 136/2000 HirschbergSinclair-PT-15-LTLFireability-05 18569654 m, 74260 m/sec, 71251128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 599
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 210/377 139/2000 HirschbergSinclair-PT-15-LTLFireability-05 19038123 m, 93693 m/sec, 72965983 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 602
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 215/377 142/2000 HirschbergSinclair-PT-15-LTLFireability-05 19471641 m, 86703 m/sec, 74680779 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 605
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 220/377 145/2000 HirschbergSinclair-PT-15-LTLFireability-05 19899195 m, 85510 m/sec, 76395838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 608
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 225/377 148/2000 HirschbergSinclair-PT-15-LTLFireability-05 20290304 m, 78221 m/sec, 78096713 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 611
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 230/377 150/2000 HirschbergSinclair-PT-15-LTLFireability-05 20640281 m, 69995 m/sec, 79775346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 613
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 235/377 153/2000 HirschbergSinclair-PT-15-LTLFireability-05 21057226 m, 83389 m/sec, 81466621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 616
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 240/377 156/2000 HirschbergSinclair-PT-15-LTLFireability-05 21499236 m, 88402 m/sec, 83167506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 619
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 245/377 159/2000 HirschbergSinclair-PT-15-LTLFireability-05 21884940 m, 77140 m/sec, 84857116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 622
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 250/377 162/2000 HirschbergSinclair-PT-15-LTLFireability-05 22289172 m, 80846 m/sec, 86526685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 625
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 255/377 164/2000 HirschbergSinclair-PT-15-LTLFireability-05 22640561 m, 70277 m/sec, 88206226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 627
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 260/377 167/2000 HirschbergSinclair-PT-15-LTLFireability-05 23015778 m, 75043 m/sec, 89855698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 630
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 265/377 170/2000 HirschbergSinclair-PT-15-LTLFireability-05 23398861 m, 76616 m/sec, 91523744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 633
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 270/377 172/2000 HirschbergSinclair-PT-15-LTLFireability-05 23728688 m, 65965 m/sec, 93196341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 635
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 275/377 174/2000 HirschbergSinclair-PT-15-LTLFireability-05 24064112 m, 67084 m/sec, 94838086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 637
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 280/377 177/2000 HirschbergSinclair-PT-15-LTLFireability-05 24480798 m, 83337 m/sec, 96506187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 640
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 285/377 180/2000 HirschbergSinclair-PT-15-LTLFireability-05 24904462 m, 84732 m/sec, 98189067 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 643
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 290/377 183/2000 HirschbergSinclair-PT-15-LTLFireability-05 25271370 m, 73381 m/sec, 99851400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 646
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 295/377 186/2000 HirschbergSinclair-PT-15-LTLFireability-05 25699580 m, 85642 m/sec, 101534996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 649
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 300/377 188/2000 HirschbergSinclair-PT-15-LTLFireability-05 26089398 m, 77963 m/sec, 103190866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 651
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 305/377 191/2000 HirschbergSinclair-PT-15-LTLFireability-05 26446538 m, 71428 m/sec, 104816218 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 654
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 310/377 193/2000 HirschbergSinclair-PT-15-LTLFireability-05 26802110 m, 71114 m/sec, 106451066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 656
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 315/377 196/2000 HirschbergSinclair-PT-15-LTLFireability-05 27176211 m, 74820 m/sec, 108085315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 659
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 320/377 200/2000 HirschbergSinclair-PT-15-LTLFireability-05 27644982 m, 93754 m/sec, 109783991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 663
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 325/377 203/2000 HirschbergSinclair-PT-15-LTLFireability-05 28059370 m, 82877 m/sec, 111460077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 666
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 330/377 206/2000 HirschbergSinclair-PT-15-LTLFireability-05 28479138 m, 83953 m/sec, 113160627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 669
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 335/377 209/2000 HirschbergSinclair-PT-15-LTLFireability-05 28870991 m, 78370 m/sec, 114851710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 672
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 340/377 211/2000 HirschbergSinclair-PT-15-LTLFireability-05 29212320 m, 68265 m/sec, 116518039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 674
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 345/377 214/2000 HirschbergSinclair-PT-15-LTLFireability-05 29618906 m, 81317 m/sec, 118180850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 677
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 350/377 217/2000 HirschbergSinclair-PT-15-LTLFireability-05 30018473 m, 79913 m/sec, 119876434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 680
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 355/377 220/2000 HirschbergSinclair-PT-15-LTLFireability-05 30398214 m, 75948 m/sec, 121558610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 683
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 360/377 223/2000 HirschbergSinclair-PT-15-LTLFireability-05 30727688 m, 65894 m/sec, 123226166 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 686
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 365/377 225/2000 HirschbergSinclair-PT-15-LTLFireability-05 31128264 m, 80115 m/sec, 124910350 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 688
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 370/377 228/2000 HirschbergSinclair-PT-15-LTLFireability-05 31550530 m, 84453 m/sec, 126613299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 691
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 16 LTL EXCL 375/377 231/2000 HirschbergSinclair-PT-15-LTLFireability-05 31905659 m, 71025 m/sec, 128297743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 694
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 16 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-05 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 696
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 HirschbergSinclair-PT-15-LTLFireability-03
[[35mlola[0m][I] time limit : 377 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 HirschbergSinclair-PT-15-LTLFireability-05
[[35mlola[0m][I] time limit : 2265 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 5/377 4/2000 HirschbergSinclair-PT-15-LTLFireability-03 414208 m, 82841 m/sec, 1750218 t fired, .
[[35mlola[0m][.] 16 LTL EXCL 5/2265 5/5 HirschbergSinclair-PT-15-LTLFireability-05 561286 m, -6268874 m/sec, 1754429 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 705
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 16 (type EXCL) for HirschbergSinclair-PT-15-LTLFireability-05 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 10/377 7/2000 HirschbergSinclair-PT-15-LTLFireability-03 791323 m, 75423 m/sec, 3471838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 705
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 15/377 9/2000 HirschbergSinclair-PT-15-LTLFireability-03 1139231 m, 69581 m/sec, 5187951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 705
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 20/377 12/2000 HirschbergSinclair-PT-15-LTLFireability-03 1453770 m, 62907 m/sec, 6912711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 708
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 25/377 14/2000 HirschbergSinclair-PT-15-LTLFireability-03 1777188 m, 64683 m/sec, 8568772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 710
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 30/377 16/2000 HirschbergSinclair-PT-15-LTLFireability-03 2091911 m, 62944 m/sec, 10194285 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 712
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 35/377 19/2000 HirschbergSinclair-PT-15-LTLFireability-03 2435372 m, 68692 m/sec, 11889776 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 715
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 40/377 21/2000 HirschbergSinclair-PT-15-LTLFireability-03 2744753 m, 61876 m/sec, 13587384 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 717
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 45/377 24/2000 HirschbergSinclair-PT-15-LTLFireability-03 3065987 m, 64246 m/sec, 15224264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 720
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 50/377 26/2000 HirschbergSinclair-PT-15-LTLFireability-03 3342738 m, 55350 m/sec, 16834286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 722
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 55/377 28/2000 HirschbergSinclair-PT-15-LTLFireability-03 3608644 m, 53181 m/sec, 18368197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 724
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 60/377 30/2000 HirschbergSinclair-PT-15-LTLFireability-03 3908360 m, 59943 m/sec, 20014040 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 726
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 65/377 32/2000 HirschbergSinclair-PT-15-LTLFireability-03 4170196 m, 52367 m/sec, 21675064 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 728
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 70/377 34/2000 HirschbergSinclair-PT-15-LTLFireability-03 4438728 m, 53706 m/sec, 23323838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 730
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 75/377 36/2000 HirschbergSinclair-PT-15-LTLFireability-03 4681752 m, 48604 m/sec, 24928378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 732
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 80/377 38/2000 HirschbergSinclair-PT-15-LTLFireability-03 4954676 m, 54584 m/sec, 26545414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 734
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 85/377 40/2000 HirschbergSinclair-PT-15-LTLFireability-03 5207134 m, 50491 m/sec, 28096147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 736
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 90/377 41/2000 HirschbergSinclair-PT-15-LTLFireability-03 5427720 m, 44117 m/sec, 29496999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 737
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 95/377 44/2000 HirschbergSinclair-PT-15-LTLFireability-03 5752816 m, 65019 m/sec, 31170759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 740
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 100/377 46/2000 HirschbergSinclair-PT-15-LTLFireability-03 6102909 m, 70018 m/sec, 32882244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 742
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 105/377 49/2000 HirschbergSinclair-PT-15-LTLFireability-03 6411170 m, 61652 m/sec, 34545116 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 745
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 110/377 51/2000 HirschbergSinclair-PT-15-LTLFireability-03 6700771 m, 57920 m/sec, 36135389 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 747
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 115/377 53/2000 HirschbergSinclair-PT-15-LTLFireability-03 7010527 m, 61951 m/sec, 37737172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 749
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 120/377 55/2000 HirschbergSinclair-PT-15-LTLFireability-03 7333877 m, 64670 m/sec, 39354395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 751
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 125/377 58/2000 HirschbergSinclair-PT-15-LTLFireability-03 7628316 m, 58887 m/sec, 41016511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 754
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 130/377 60/2000 HirschbergSinclair-PT-15-LTLFireability-03 7901766 m, 54690 m/sec, 42628475 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 756
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 135/377 62/2000 HirschbergSinclair-PT-15-LTLFireability-03 8198635 m, 59373 m/sec, 44230744 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 758
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 140/377 64/2000 HirschbergSinclair-PT-15-LTLFireability-03 8432216 m, 46716 m/sec, 45673010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 760
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 145/377 66/2000 HirschbergSinclair-PT-15-LTLFireability-03 8690776 m, 51712 m/sec, 47243820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 762
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 150/377 68/2000 HirschbergSinclair-PT-15-LTLFireability-03 8983367 m, 58518 m/sec, 48841199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 764
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 155/377 70/2000 HirschbergSinclair-PT-15-LTLFireability-03 9242987 m, 51924 m/sec, 50378341 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 766
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 160/377 72/2000 HirschbergSinclair-PT-15-LTLFireability-03 9536179 m, 58638 m/sec, 52028873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 768
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 165/377 74/2000 HirschbergSinclair-PT-15-LTLFireability-03 9795623 m, 51888 m/sec, 53659625 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 770
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 170/377 76/2000 HirschbergSinclair-PT-15-LTLFireability-03 10039472 m, 48769 m/sec, 55248286 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 772
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 175/377 78/2000 HirschbergSinclair-PT-15-LTLFireability-03 10290036 m, 50112 m/sec, 56833592 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 774
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 180/377 80/2000 HirschbergSinclair-PT-15-LTLFireability-03 10561658 m, 54324 m/sec, 58415309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 776
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 185/377 82/2000 HirschbergSinclair-PT-15-LTLFireability-03 10794099 m, 46488 m/sec, 59923357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 778
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 190/377 83/2000 HirschbergSinclair-PT-15-LTLFireability-03 11039403 m, 49060 m/sec, 61448566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 779
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 195/377 85/2000 HirschbergSinclair-PT-15-LTLFireability-03 11304141 m, 52947 m/sec, 62915955 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 781
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 200/377 87/2000 HirschbergSinclair-PT-15-LTLFireability-03 11537398 m, 46651 m/sec, 64366506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 783
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 205/377 89/2000 HirschbergSinclair-PT-15-LTLFireability-03 11804534 m, 53427 m/sec, 65916637 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 785
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 210/377 91/2000 HirschbergSinclair-PT-15-LTLFireability-03 12066617 m, 52416 m/sec, 67499427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 787
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 215/377 93/2000 HirschbergSinclair-PT-15-LTLFireability-03 12296955 m, 46067 m/sec, 69103121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 789
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 220/377 95/2000 HirschbergSinclair-PT-15-LTLFireability-03 12548005 m, 50210 m/sec, 70687075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 791
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 225/377 96/2000 HirschbergSinclair-PT-15-LTLFireability-03 12779909 m, 46380 m/sec, 72246092 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 792
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 230/377 98/2000 HirschbergSinclair-PT-15-LTLFireability-03 12990241 m, 42066 m/sec, 73769353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 794
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 235/377 100/2000 HirschbergSinclair-PT-15-LTLFireability-03 13229679 m, 47887 m/sec, 75308649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 796
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 240/377 102/2000 HirschbergSinclair-PT-15-LTLFireability-03 13481934 m, 50451 m/sec, 76860311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 798
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 245/377 103/2000 HirschbergSinclair-PT-15-LTLFireability-03 13713806 m, 46374 m/sec, 78372192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 799
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 250/377 104/2000 HirschbergSinclair-PT-15-LTLFireability-03 13900728 m, 37384 m/sec, 79682963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 800
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 255/377 106/2000 HirschbergSinclair-PT-15-LTLFireability-03 14102439 m, 40342 m/sec, 81047803 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 802
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 260/377 108/2000 HirschbergSinclair-PT-15-LTLFireability-03 14433575 m, 66227 m/sec, 82679912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 804
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 265/377 111/2000 HirschbergSinclair-PT-15-LTLFireability-03 14751971 m, 63679 m/sec, 84332102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 807
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 270/377 113/2000 HirschbergSinclair-PT-15-LTLFireability-03 15061386 m, 61883 m/sec, 86015193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 809
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 275/377 116/2000 HirschbergSinclair-PT-15-LTLFireability-03 15343471 m, 56417 m/sec, 87659148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 812
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 280/377 118/2000 HirschbergSinclair-PT-15-LTLFireability-03 15628736 m, 57053 m/sec, 89236797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 814
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 285/377 120/2000 HirschbergSinclair-PT-15-LTLFireability-03 15931201 m, 60493 m/sec, 90896516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 816
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 290/377 122/2000 HirschbergSinclair-PT-15-LTLFireability-03 16206731 m, 55106 m/sec, 92498516 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 818
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 295/377 124/2000 HirschbergSinclair-PT-15-LTLFireability-03 16463503 m, 51354 m/sec, 94049947 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 820
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 300/377 126/2000 HirschbergSinclair-PT-15-LTLFireability-03 16718262 m, 50951 m/sec, 95599277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 822
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 305/377 128/2000 HirschbergSinclair-PT-15-LTLFireability-03 16963415 m, 49030 m/sec, 97222596 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 824
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 310/377 130/2000 HirschbergSinclair-PT-15-LTLFireability-03 17204481 m, 48213 m/sec, 98823209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 826
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 315/377 132/2000 HirschbergSinclair-PT-15-LTLFireability-03 17438043 m, 46712 m/sec, 100399783 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 828
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 320/377 134/2000 HirschbergSinclair-PT-15-LTLFireability-03 17663146 m, 45020 m/sec, 101925493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 830
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 325/377 136/2000 HirschbergSinclair-PT-15-LTLFireability-03 17932157 m, 53802 m/sec, 103472774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 832
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 330/377 138/2000 HirschbergSinclair-PT-15-LTLFireability-03 18222474 m, 58063 m/sec, 105049897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 834
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 335/377 140/2000 HirschbergSinclair-PT-15-LTLFireability-03 18485181 m, 52541 m/sec, 106580128 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 836
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-00: F 0 0 0 0 2 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-03: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-05: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-06: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-08: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-09: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] HirschbergSinclair-PT-15-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 LTL EXCL 359/377 140/2000 HirschbergSinclair-PT-15-LTLFireability-03 18527716 m, 8507 m/sec, 106826506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1694 secs. Pages in use: 836
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-07: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mHirschbergSinclair-PT-15-LTLFireability-11: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-12: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-13: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mHirschbergSinclair-PT-15-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="HirschbergSinclair-PT-15"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is HirschbergSinclair-PT-15, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r203-smll-171649588300076"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/HirschbergSinclair-PT-15.tgz
mv HirschbergSinclair-PT-15 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;