Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r181-tall-171640605700626.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is GlobalResAllocation-COL-03, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r181-tall-171640605700626
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 508K
-rw-r--r-- 1 mcc users 8.0K Apr 12 14:06 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Apr 12 14:06 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Apr 12 13:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 12 13:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Apr 22 14:47 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:47 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:47 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 17:01 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 100K Apr 12 17:01 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Apr 12 16:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 104K Apr 12 16:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:47 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:47 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 28K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-00
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-01
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-02
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-03
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-04
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-05
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-06
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-07
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-08
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-09
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-10
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-11
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-12
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-13
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-14
FORMULA_NAME GlobalResAllocation-COL-03-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717069964237

FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GlobalResAllocation-COL-03-CTLFireability-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-00: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-01: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-02: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-03: EFAG false tscc_search
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-04: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-05: CTL false CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-06: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-07: CONJ true CONJ
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-08: CTL false CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-09: CTL false CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-10: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-11: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-12: CTL true CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-13: CTL false CTL model checker
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-14: CONJ false CONJ
[lola] GlobalResAllocation-COL-03-CTLFireability-2024-15: CTL true CTL model checker
[lola]
[lola] Time elapsed: 30 secs. Pages in use: 1

BK_STOP 1717069994355

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from CTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] Places: 33, Transitions: 4791
[lola][W] findlow criterion violated for transition 6
[lola][I] nonmoderate token usage
[lola][I] nonmoderate token usage
[lola][I] nonmoderate token usage
[lola][W] findlow criterion violated for transition 5
[lola][W] findlow criterion violated for 5 clusters
[lola][I] Time for checking findlow: 0
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 68 (type SKEL/SRCH) for 46 GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 68 (type SKEL/SRCH) for GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] result : false
[lola][I] markings : 6
[lola][I] fired transitions : 6
[lola][I] time used : 0
[lola][I] memory pages used : 1
[*** LOG ERROR #0001 ***] [2024-05-30 11:52:48] [status_logger] string pointer is null
[lola][I] LAUNCH task # 1 (type EXCL) for 0 GlobalResAllocation-COL-03-CTLFireability-2024-00
[lola][I] time limit : 179 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 1 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-00
[lola][I] result : true
[lola][I] markings : 5998
[lola][I] fired transitions : 53632
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-00: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-03: EFAG 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-07: CONJ 0 0 0 0 2 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-12: CTL 1 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-14: CONJ 0 0 0 0 6 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 41 (type EXCL) for 40 GlobalResAllocation-COL-03-CTLFireability-2024-12
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 41 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-12
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 87557
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 32 (type EXCL) for 31 GlobalResAllocation-COL-03-CTLFireability-2024-09
[lola][I] time limit : 199 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 32 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-09
[lola][I] result : false
[lola][I] markings : 545
[lola][I] fired transitions : 1982
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 35 (type EXCL) for 34 GlobalResAllocation-COL-03-CTLFireability-2024-10
[lola][I] time limit : 211 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 35 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 5998
[lola][I] fired transitions : 46735
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 29 (type EXCL) for 28 GlobalResAllocation-COL-03-CTLFireability-2024-08
[lola][I] time limit : 224 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 29 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-08
[lola][I] result : false
[lola][I] markings : 6320
[lola][I] fired transitions : 123300
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 26 (type EXCL) for 21 GlobalResAllocation-COL-03-CTLFireability-2024-07
[lola][I] time limit : 239 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 26 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 2079
[lola][I] fired transitions : 29345
[lola][I] time used : 6
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 63 (type EXCL) for 46 GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] time limit : 256 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-00: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-08: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-12: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-03: EFAG 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-06: CTL 1 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-07: CONJ 0 1 0 0 3 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-14: CONJ 2 1 1 0 6 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 CTL EXCL 0/256 1/2000 GlobalResAllocation-COL-03-CTLFireability-2024-14 20 m, 4 m/sec, 60 t fired, .
[lola][.]
[lola][.] Time elapsed: 13 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 63 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] result : false
[lola][I] markings : 6320
[lola][I] fired transitions : 90679
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 16 (type EXCL) for 15 GlobalResAllocation-COL-03-CTLFireability-2024-05
[lola][I] time limit : 275 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 16 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 6319
[lola][I] fired transitions : 59467
[lola][I] time used : 8
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-00: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-08: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-12: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-03: EFAG 0 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-05: CTL 0 0 0 0 2 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-06: CTL 1 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-07: CONJ 0 1 0 0 3 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-11: CTL 1 0 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-14: CONJ 1 2 0 0 7 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 21 secs. Pages in use: 1
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] LAUNCH task # 66 (type EXCL) for 65 GlobalResAllocation-COL-03-CTLFireability-2024-15
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 73 (type EQUN) for 9 GlobalResAllocation-COL-03-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 75 (type EQUN) for 9 GlobalResAllocation-COL-03-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 66 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-15
[lola][I] result : true
[lola][I] markings : 935
[lola][I] fired transitions : 17863
[lola][I] time used : 3
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 61 (type EXCL) for 46 GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 61 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-14
[lola][I] result : false
[lola][I] markings : 6320
[lola][I] fired transitions : 127960
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type EXCL) for 37 GlobalResAllocation-COL-03-CTLFireability-2024-11
[lola][I] time limit : 446 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-11
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 195707
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 19 (type EXCL) for 18 GlobalResAllocation-COL-03-CTLFireability-2024-06
[lola][I] time limit : 510 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 19 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-06
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 124518
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 13 (type EXCL) for 12 GlobalResAllocation-COL-03-CTLFireability-2024-04
[lola][I] time limit : 595 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 13 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 13
[lola][I] fired transitions : 37
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 7 (type EXCL) for 6 GlobalResAllocation-COL-03-CTLFireability-2024-02
[lola][I] time limit : 714 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-00: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-04: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-06: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-08: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-09: CTL false CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-12: CTL true CTL model checker
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-14: CONJ false CONJ
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-15: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-02: CTL 0 0 1 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-03: EFAG 0 1 2 0 1 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-07: CONJ 0 1 0 0 3 0 0 0
[lola][.] GlobalResAllocation-COL-03-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 7 CTL EXCL 0/714 1/2000 GlobalResAllocation-COL-03-CTLFireability-2024-02 361 m, 72 m/sec, 2759 t fired, .
[lola][.] 73 EF STEQ 5/3579 0/5 GlobalResAllocation-COL-03-CTLFireability-2024-03 sara not yet started (preprocessing).
[lola][.] 75 EF STEQ 5/3579 0/5 GlobalResAllocation-COL-03-CTLFireability-2024-03 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 26 secs. Pages in use: 1
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] FINISHED task # 7 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-02
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 149335
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 4 (type EXCL) for 3 GlobalResAllocation-COL-03-CTLFireability-2024-01
[lola][I] time limit : 893 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 4 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-01
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 91388
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 70 (type EXCL) for 9 GlobalResAllocation-COL-03-CTLFireability-2024-03
[lola][I] time limit : 1191 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 70 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 93138
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 73 (type EQUN) for GlobalResAllocation-COL-03-CTLFireability-2024-03 (obsolete)
[lola][W] CANCELED task # 75 (type EQUN) for GlobalResAllocation-COL-03-CTLFireability-2024-03 (obsolete)
[lola][I] LAUNCH task # 24 (type EXCL) for 21 GlobalResAllocation-COL-03-CTLFireability-2024-07
[lola][I] time limit : 1786 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 24 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-07
[lola][I] result : true
[lola][I] markings : 6320
[lola][I] fired transitions : 90448
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 43 GlobalResAllocation-COL-03-CTLFireability-2024-13
[lola][I] time limit : 3571 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for GlobalResAllocation-COL-03-CTLFireability-2024-13
[lola][I] result : false
[lola][I] markings : 6320
[lola][I] fired transitions : 261872
[lola][I] time used : 1
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GlobalResAllocation-COL-03"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is GlobalResAllocation-COL-03, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r181-tall-171640605700626"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/GlobalResAllocation-COL-03.tgz
mv GlobalResAllocation-COL-03 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;