About the Execution of LoLA for GPPP-PT-C0010N0000000100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 11365.619 | 3600000.00 | 779750.00 | 10602.70 | ??T????TT?TFFTT? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r181-tall-171640605100386.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is GPPP-PT-C0010N0000000100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r181-tall-171640605100386
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 452K
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Apr 22 14:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.6K Apr 12 08:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 72K Apr 12 08:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 12 08:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 108K Apr 12 08:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:46 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:46 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 17 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1 May 18 16:42 large_marking
-rw-r--r-- 1 mcc users 21K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-00
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-01
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-02
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-03
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-04
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-05
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-06
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-07
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-08
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-09
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-10
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2024-11
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2023-12
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2023-13
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2023-14
FORMULA_NAME GPPP-PT-C0010N0000000100-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717055742232
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2023-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA GPPP-PT-C0010N0000000100-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 26 (type CNST) for 25 GPPP-PT-C0010N0000000100-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 26 (type CNST) for GPPP-PT-C0010N0000000100-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 38 (type CNST) for 37 GPPP-PT-C0010N0000000100-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 38 (type CNST) for GPPP-PT-C0010N0000000100-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 7 (type EXCL) for 6 GPPP-PT-C0010N0000000100-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 7 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 624
[[35mlola[0m][I] fired transitions : 1395
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 GPPP-PT-C0010N0000000100-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 53 GPPP-PT-C0010N0000000100-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 63 (type EQUN) for 43 GPPP-PT-C0010N0000000100-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 19 GPPP-PT-C0010N0000000100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1425
[[35mlola[0m][I] fired transitions : 3640
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 56 (type EXCL) for 43 GPPP-PT-C0010N0000000100-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 56 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 63 (type EQUN) for GPPP-PT-C0010N0000000100-CTLFireability-2023-13 (obsolete)
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 GPPP-PT-C0010N0000000100-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 624
[[35mlola[0m][I] fired transitions : 863
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 GPPP-PT-C0010N0000000100-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for GPPP-PT-C0010N0000000100-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 63 (type EQUN) for GPPP-PT-C0010N0000000100-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2023-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 85
[[35mlola[0m][I] fired transitions : 321
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 GPPP-PT-C0010N0000000100-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 6800
[[35mlola[0m][I] fired transitions : 23970
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 9 GPPP-PT-C0010N0000000100-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 400 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for GPPP-PT-C0010N0000000100-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 5/400 10/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 2352391 m, 470478 m/sec, 7682432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 10
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 10/400 19/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 4446318 m, 418785 m/sec, 15441320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 19
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 15/400 27/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 6318986 m, 374533 m/sec, 23162969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 20/400 36/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 8428656 m, 421934 m/sec, 30998046 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 25/400 44/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 10370031 m, 388275 m/sec, 38299980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 30/400 51/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 12032560 m, 332505 m/sec, 45369943 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 51
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 35/400 58/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 13749539 m, 343395 m/sec, 52201280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 40/400 65/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 15441730 m, 338438 m/sec, 58972585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 45/400 73/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 17157205 m, 343095 m/sec, 65560802 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 50/400 79/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 18675809 m, 303720 m/sec, 71854650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 55/400 87/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 20576862 m, 380210 m/sec, 79088148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 60/400 94/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 22189651 m, 322557 m/sec, 86196365 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 65/400 101/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 23913421 m, 344754 m/sec, 93430308 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 70/400 109/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 25814219 m, 380159 m/sec, 101024287 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 75/400 116/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 27434469 m, 324050 m/sec, 108206394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 80/400 123/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 29148744 m, 342855 m/sec, 115494806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 85/400 129/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 30661128 m, 302476 m/sec, 122488003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 129
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 90/400 137/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 32551557 m, 378085 m/sec, 129949886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 137
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 95/400 145/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 34347260 m, 359140 m/sec, 137099075 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 100/400 152/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 36113613 m, 353270 m/sec, 144167296 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 105/400 159/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 37859863 m, 349250 m/sec, 151172098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 159
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 110/400 166/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 39425841 m, 313195 m/sec, 157698727 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 115/400 172/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 40842137 m, 283259 m/sec, 164122052 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 120/400 178/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 42282785 m, 288129 m/sec, 170866247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 125/400 184/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 43824417 m, 308326 m/sec, 177692641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 130/400 191/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 45374591 m, 310034 m/sec, 184258508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 191
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 135/400 197/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 46861849 m, 297451 m/sec, 190758696 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 140/400 204/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 48391516 m, 305933 m/sec, 197397948 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 145/400 210/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 49821163 m, 285929 m/sec, 203826782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 150/400 216/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 51404778 m, 316723 m/sec, 210329234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 155/400 223/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 52989089 m, 316862 m/sec, 216949545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 160/400 230/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 54588711 m, 319924 m/sec, 223482408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 230
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 165/400 236/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 55996355 m, 281528 m/sec, 229418198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 170/400 241/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 57306344 m, 261997 m/sec, 235294320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 175/400 247/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 58657268 m, 270184 m/sec, 241290035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 180/400 253/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 60161556 m, 300857 m/sec, 247508984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 185/400 260/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 61868417 m, 341372 m/sec, 254090986 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 190/400 267/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 63589712 m, 344259 m/sec, 261471620 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 195/400 274/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 65215022 m, 325062 m/sec, 268664753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 274
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 200/400 281/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 66712632 m, 299522 m/sec, 275431380 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 281
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 205/400 286/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 68109693 m, 279412 m/sec, 281928134 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 286
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 210/400 292/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 69480075 m, 274076 m/sec, 288433020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 215/400 299/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 71205451 m, 345075 m/sec, 295428853 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 299
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 220/400 307/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 73077472 m, 374404 m/sec, 302936168 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 225/400 314/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 74664370 m, 317379 m/sec, 309975015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 230/400 321/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 76299972 m, 327120 m/sec, 317100453 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 321
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 235/400 327/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 77723294 m, 284664 m/sec, 323843647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 240/400 333/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 79171584 m, 289658 m/sec, 330516124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 245/400 340/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 80769609 m, 319605 m/sec, 337508969 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 250/400 346/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 82243084 m, 294695 m/sec, 344092542 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 346
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 255/400 352/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 83669995 m, 285382 m/sec, 350927526 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 260/400 359/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 85439349 m, 353870 m/sec, 358162456 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 265/400 366/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 87186274 m, 349385 m/sec, 365157987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 366
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 270/400 373/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 88804442 m, 323633 m/sec, 371899552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 373
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 275/400 380/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 90424741 m, 324059 m/sec, 378670414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 380
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 280/400 387/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 92024221 m, 319896 m/sec, 385361304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 285/400 394/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 93622439 m, 319643 m/sec, 392019734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 290/400 400/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 95253323 m, 326176 m/sec, 398809852 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 295/400 407/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 96877417 m, 324818 m/sec, 405498925 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 407
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 300/400 413/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 98310525 m, 286621 m/sec, 411575019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 305/400 418/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 99504754 m, 238845 m/sec, 417298072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 418
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 310/400 423/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 100654966 m, 230042 m/sec, 422885409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 423
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 315/400 429/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 102008100 m, 270626 m/sec, 429009010 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 429
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 320/400 434/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 103293064 m, 256992 m/sec, 435215831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 434
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 325/400 439/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 104440437 m, 229474 m/sec, 440876728 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 330/400 444/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 105716982 m, 255309 m/sec, 446951697 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 444
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 335/400 451/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 107211950 m, 298993 m/sec, 453450381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 451
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 340/400 457/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 108641702 m, 285950 m/sec, 459738418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 345/400 462/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 110049860 m, 281631 m/sec, 465940926 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 462
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 350/400 468/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 111444398 m, 278907 m/sec, 472166872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 468
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 355/400 473/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 112649529 m, 241026 m/sec, 477893488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 360/400 479/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 114040718 m, 278237 m/sec, 483945328 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 479
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 365/400 485/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 115403807 m, 272617 m/sec, 490322107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 485
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 370/400 490/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 116700816 m, 259401 m/sec, 496350379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 490
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 375/400 496/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 117998676 m, 259572 m/sec, 502276800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 380/400 502/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 119463273 m, 292919 m/sec, 508531774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 502
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 385/400 508/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 120869933 m, 281332 m/sec, 514634115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 508
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 390/400 514/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 122285678 m, 283149 m/sec, 520805977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 514
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 395/400 520/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 123725721 m, 288008 m/sec, 527023967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 520
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 14 CTL EXCL 400/400 525/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-03 125064205 m, 267696 m/sec, 533137767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 525
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 14 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 1 0 0 2 1 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 12 (type EXCL) for 9 GPPP-PT-C0010N0000000100-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 399 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 14 (type EXCL) for 9 GPPP-PT-C0010N0000000100-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 3195 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 12 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3349
[[35mlola[0m][I] fired transitions : 21068
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 14 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-05: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 19 GPPP-PT-C0010N0000000100-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 455 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 261
[[35mlola[0m][I] fired transitions : 307
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 57 (type EXCL) for 53 GPPP-PT-C0010N0000000100-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 531 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 57 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 GPPP-PT-C0010N0000000100-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 638 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 5/638 7/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 1572106 m, 314421 m/sec, 9709316 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 10/638 13/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 2889572 m, 263493 m/sec, 18434399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 15/638 18/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 4151399 m, 252365 m/sec, 26773416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 20/638 23/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 5399617 m, 249643 m/sec, 34891315 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 25/638 29/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 6687512 m, 257579 m/sec, 42977788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 17 CTL EXCL 30/638 34/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-04 8048196 m, 272136 m/sec, 51359908 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 8436215
[[35mlola[0m][I] fired transitions : 53576125
[[35mlola[0m][I] time used : 31
[[35mlola[0m][I] memory pages used : 36
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 GPPP-PT-C0010N0000000100-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 789 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 58753
[[35mlola[0m][I] fired transitions : 148310
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 23 (type EXCL) for 22 GPPP-PT-C0010N0000000100-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 1053 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 4/1053 4/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 925436 m, 185087 m/sec, 6706688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 9/1053 9/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 2061652 m, 227243 m/sec, 15107767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 14/1053 14/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 3091785 m, 206026 m/sec, 23108998 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 19/1053 18/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 4079837 m, 197610 m/sec, 30779465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 24/1053 22/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 5045595 m, 193151 m/sec, 38340055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 29/1053 26/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 6014040 m, 193689 m/sec, 45825533 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 34/1053 30/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 6966171 m, 190426 m/sec, 53183560 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 39/1053 34/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 7940116 m, 194789 m/sec, 60518702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 44/1053 38/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 8959993 m, 203975 m/sec, 67979860 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 49/1053 42/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 9968993 m, 201800 m/sec, 75321760 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 54/1053 47/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 11002201 m, 206641 m/sec, 82742930 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 23 CTL EXCL 59/1053 52/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-06 12151740 m, 229907 m/sec, 90701600 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 23 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 12342270
[[35mlola[0m][I] fired transitions : 91803325
[[35mlola[0m][I] time used : 60
[[35mlola[0m][I] memory pages used : 52
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 GPPP-PT-C0010N0000000100-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 1549 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 4/1549 8/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 1675346 m, 335069 m/sec, 7556597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 9/1549 10/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 2238930 m, 112716 m/sec, 16087997 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 14/1549 12/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 2773630 m, 106940 m/sec, 24481962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 19/1549 14/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 3318338 m, 108941 m/sec, 33017903 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 24/1549 16/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 3779264 m, 92185 m/sec, 41825255 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 29/1549 21/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 4896170 m, 223381 m/sec, 50151213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 34/1549 23/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 5363758 m, 93517 m/sec, 58191545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 39/1549 25/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 5812710 m, 89790 m/sec, 66044057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 44/1549 26/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 6267381 m, 90934 m/sec, 73970025 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 49/1549 28/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 6652468 m, 77017 m/sec, 82030949 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 54/1549 31/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 7442939 m, 158094 m/sec, 90346642 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 59/1549 34/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 8118324 m, 135077 m/sec, 98097301 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 64/1549 36/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 8546235 m, 85582 m/sec, 105810015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 69/1549 38/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 9027148 m, 96182 m/sec, 113616585 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 74/1549 39/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 9405811 m, 75732 m/sec, 121502121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 79/1549 43/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 10256604 m, 170158 m/sec, 129434748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 84/1549 45/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 10759086 m, 100496 m/sec, 136999528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 89/1549 47/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 11216270 m, 91436 m/sec, 144481320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 94/1549 48/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 11578539 m, 72453 m/sec, 151869292 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 99/1549 50/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 12048119 m, 93916 m/sec, 159816219 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 104/1549 54/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 12882228 m, 166821 m/sec, 167411235 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 109/1549 55/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 13330954 m, 89745 m/sec, 174821866 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 114/1549 57/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 13694656 m, 72740 m/sec, 182187077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 119/1549 59/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 14163646 m, 93798 m/sec, 190077198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 124/1549 62/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 14952013 m, 157673 m/sec, 197586672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 129/1549 64/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 15364854 m, 82568 m/sec, 204763548 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 134/1549 65/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 15762890 m, 79607 m/sec, 212411221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 139/1549 68/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 16511517 m, 149725 m/sec, 220133422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 144/1549 70/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 16918444 m, 81385 m/sec, 227545834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 149/1549 72/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 17358573 m, 88025 m/sec, 235330195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 154/1549 75/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 18031760 m, 134637 m/sec, 243058473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 159/1549 76/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 18451957 m, 84039 m/sec, 250442608 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 164/1549 79/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 19076014 m, 124811 m/sec, 258270730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 169/1549 81/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 19520131 m, 88823 m/sec, 265803662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 174/1549 83/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 20094108 m, 114795 m/sec, 273576340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 179/1549 85/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 20550152 m, 91208 m/sec, 281258302 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 184/1549 87/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 21117670 m, 113503 m/sec, 289131702 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 189/1549 90/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 21684712 m, 113408 m/sec, 297088604 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 194/1549 92/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 22242728 m, 111603 m/sec, 305016722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 199/1549 94/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 22796149 m, 110684 m/sec, 312988351 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 204/1549 97/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 23342308 m, 109231 m/sec, 320961291 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 209/1549 99/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 23891445 m, 109827 m/sec, 329080518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 214/1549 101/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 24437260 m, 109163 m/sec, 337210264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 219/1549 103/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 25026173 m, 117782 m/sec, 345403194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 224/1549 106/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 25604843 m, 115734 m/sec, 353715338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 229/1549 108/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 26200870 m, 119205 m/sec, 362135912 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 234/1549 111/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-00 26801138 m, 120053 m/sec, 370664662 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27056349
[[35mlola[0m][I] fired transitions : 378737335
[[35mlola[0m][I] time used : 239
[[35mlola[0m][I] memory pages used : 112
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 GPPP-PT-C0010N0000000100-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 2860 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 0/2860 1/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-09 87582 m, 17516 m/sec, 634924 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 740 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 5/2860 5/2000 GPPP-PT-C0010N0000000100-CTLFireability-2024-09 1155401 m, 213563 m/sec, 9312767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for GPPP-PT-C0010N0000000100-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1469068
[[35mlola[0m][I] fired transitions : 12125593
[[35mlola[0m][I] time used : 7
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 750 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 755 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 760 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 765 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 770 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 775 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 780 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 785 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 790 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 795 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 800 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 805 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 810 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 815 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 820 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 825 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 830 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 835 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 840 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 845 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 850 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 855 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 860 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 865 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 870 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 875 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 880 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 885 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 890 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 895 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 900 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 905 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 910 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 915 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 920 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 925 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 930 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 935 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 940 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 945 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 950 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 955 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 960 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 965 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 970 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 975 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 980 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 985 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 990 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 995 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1000 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1005 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1010 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1015 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1020 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1025 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1030 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1035 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1040 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1045 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1050 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1055 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1060 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1065 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1070 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1075 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1080 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1085 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1090 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1095 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1100 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1105 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1110 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1115 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1120 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1125 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1130 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1135 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1140 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1145 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1150 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1155 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1160 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1165 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1170 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1175 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1180 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1185 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1190 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1195 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1200 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1205 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1210 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1215 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1220 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1225 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1230 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1235 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1240 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1245 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1250 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1255 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1260 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1265 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1270 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1275 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1280 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1285 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1290 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1295 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1300 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1305 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1310 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1315 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1320 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1325 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1330 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1335 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1340 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1345 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1350 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1355 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1360 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1365 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1370 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1375 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1380 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1385 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1390 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1395 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1400 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1405 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1410 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1415 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1420 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1425 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1430 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1435 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1440 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1445 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1450 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1455 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1460 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1465 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1470 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1475 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1480 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1485 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1490 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1495 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1500 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1505 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1510 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1515 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1520 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1525 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1530 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1535 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1540 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1545 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1550 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1555 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1560 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1565 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1570 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1575 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1580 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1585 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1590 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1595 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1600 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1605 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1610 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1615 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1620 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1625 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1630 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1635 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1640 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1645 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1650 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1655 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1660 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1665 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1670 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1675 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1680 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1685 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1690 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1695 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1700 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1705 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1710 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1715 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1720 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1725 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1730 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1735 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1740 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1745 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1750 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1755 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1760 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1765 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1770 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1775 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1780 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1785 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1790 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1795 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1800 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1805 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1810 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1815 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1820 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1825 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1830 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1835 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1840 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1845 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1850 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1855 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1860 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1865 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1870 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1875 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1880 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1885 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1890 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1895 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1900 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1905 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1910 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1915 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1920 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1925 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1930 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1935 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1940 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1945 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1950 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1955 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1960 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1965 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1970 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1975 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1980 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1985 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-00: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-02: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-04: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-05: F true state space / EG[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-06: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-07: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-08: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2024-10: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-12: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-13: DISJ true state space /EXEF[0m
[[35mlola[0m][.] [1m[32mGPPP-PT-C0010N0000000100-CTLFireability-2023-14: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mGPPP-PT-C0010N0000000100-CTLFireability-2023-15: EU false state space /EU[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] GPPP-PT-C0010N0000000100-CTLFireability-2024-03: CONJ 0 0 0 0 3 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="GPPP-PT-C0010N0000000100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is GPPP-PT-C0010N0000000100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r181-tall-171640605100386"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/GPPP-PT-C0010N0000000100.tgz
mv GPPP-PT-C0010N0000000100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;