About the Execution of LoLA for FlexibleBarrier-PT-08a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.691 | 824835.00 | 764418.00 | 3108.50 | ???T????T??????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r181-tall-171640604400034.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FlexibleBarrier-PT-08a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r181-tall-171640604400034
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 37K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:45 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:45 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:45 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K Apr 22 14:45 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.9K Apr 13 08:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 65K Apr 13 08:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.9K Apr 13 08:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Apr 13 08:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:45 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:45 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 64K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-00
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-01
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-02
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-03
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-04
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-05
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-06
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-07
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-08
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-09
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-10
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2024-11
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2023-12
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2023-13
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2023-14
FORMULA_NAME FlexibleBarrier-PT-08a-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717011740063
FORMULA FlexibleBarrier-PT-08a-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-08a-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717012564898
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 FlexibleBarrier-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for FlexibleBarrier-PT-08a-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-08a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 6 FlexibleBarrier-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 6 FlexibleBarrier-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 67 (type FNDP) for 24 FlexibleBarrier-PT-08a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 74 (type EQUN) for 38 FlexibleBarrier-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 24 FlexibleBarrier-PT-08a-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type FNDP) for FlexibleBarrier-PT-08a-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-08 (obsolete)
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 38 FlexibleBarrier-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 79 (type EQUN) for 57 FlexibleBarrier-PT-08a-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 74 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 79 (type EQUN) for FlexibleBarrier-PT-08a-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/240 3/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 694884 m, 138976 m/sec, 4447658 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 3
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 10/240 6/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 1325767 m, 126176 m/sec, 8681189 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 15/240 9/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 1935661 m, 121978 m/sec, 12797400 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 20/240 11/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 2532824 m, 119432 m/sec, 16875410 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 25/240 14/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 3115304 m, 116496 m/sec, 20890122 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 14
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 30/240 16/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 3685069 m, 113953 m/sec, 24841482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 35/240 18/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 4249878 m, 112961 m/sec, 28758346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 40/240 21/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 4794322 m, 108888 m/sec, 32570950 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 45/240 23/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 5341916 m, 109518 m/sec, 36432837 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 50/240 25/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 5877993 m, 107215 m/sec, 40217124 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 25
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 55/240 27/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 6408283 m, 106058 m/sec, 43959619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 60/240 30/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 6931581 m, 104659 m/sec, 47674980 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 30
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 65/240 32/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 7452527 m, 104189 m/sec, 51388580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 32
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 70/240 34/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 7964281 m, 102350 m/sec, 55053444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 75/240 36/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 8478891 m, 102922 m/sec, 58732229 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 80/240 38/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 8983067 m, 100835 m/sec, 62364238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 85/240 40/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 9487670 m, 100920 m/sec, 66002421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 90/240 42/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 9983497 m, 99165 m/sec, 69594306 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 95/240 44/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 10474727 m, 98246 m/sec, 73155026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 100/240 46/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 10965256 m, 98105 m/sec, 76715767 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 46
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 105/240 48/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 11450151 m, 96979 m/sec, 80240920 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 110/240 50/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 11934583 m, 96886 m/sec, 83765561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 115/240 52/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 12414618 m, 96007 m/sec, 87277597 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 120/240 54/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 12889949 m, 95066 m/sec, 90764769 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 54
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 125/240 56/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 13367128 m, 95435 m/sec, 94263268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 130/240 58/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 13844184 m, 95411 m/sec, 97759493 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 135/240 60/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 14319078 m, 94978 m/sec, 101260961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 140/240 62/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 14795122 m, 95208 m/sec, 104772421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 145/240 64/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 15267666 m, 94508 m/sec, 108256615 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 150/240 66/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 15736447 m, 93756 m/sec, 111715031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 155/240 68/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 16206616 m, 94033 m/sec, 115187031 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 68
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 160/240 70/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 16674178 m, 93512 m/sec, 118638568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 165/240 72/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 17137981 m, 92760 m/sec, 122076333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 170/240 74/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 17599738 m, 92351 m/sec, 125500420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 74
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 175/240 76/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 18063105 m, 92673 m/sec, 128939377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 180/240 78/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 18522831 m, 91945 m/sec, 132357087 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 78
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 185/240 80/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 18982395 m, 91912 m/sec, 135779428 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 190/240 82/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 19440865 m, 91694 m/sec, 139191171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 82
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 195/240 84/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 19905343 m, 92895 m/sec, 142649022 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 84
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 200/240 86/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 20367136 m, 92358 m/sec, 146092482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 205/240 88/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 20827478 m, 92068 m/sec, 149532861 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 210/240 89/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 21285666 m, 91637 m/sec, 152953753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 215/240 91/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 21741736 m, 91214 m/sec, 156379867 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 220/240 93/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 22195864 m, 90825 m/sec, 159786956 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 93
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 225/240 95/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 22648346 m, 90496 m/sec, 163183463 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 230/240 97/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 23099763 m, 90283 m/sec, 166567994 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 235/240 99/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 23550153 m, 90078 m/sec, 169943916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 240/240 101/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-01 23998016 m, 89572 m/sec, 173324070 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 4 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2024-01 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 50 FlexibleBarrier-PT-08a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FlexibleBarrier-PT-08a-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 3355 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 55 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 92
[[35mlola[0m][I] fired transitions : 144
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 CTL EXCL 5/239 4/5 FlexibleBarrier-PT-08a-CTLFireability-2024-01 745631 m, -4650477 m/sec, 4786163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 4 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2024-01 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 50 FlexibleBarrier-PT-08a-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 FlexibleBarrier-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 278 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 143
[[35mlola[0m][I] fired transitions : 445
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 FlexibleBarrier-PT-08a-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 304 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 FlexibleBarrier-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 334 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 5/334 6/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 1273612 m, 254722 m/sec, 5072613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 10/334 10/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 2360576 m, 217392 m/sec, 9654085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 15/334 15/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 3376774 m, 203239 m/sec, 14018311 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 20/334 19/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 4351310 m, 194907 m/sec, 18233331 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 25/334 23/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 5295334 m, 188804 m/sec, 22357730 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 30/334 26/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 6164313 m, 173795 m/sec, 26200626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 35/334 30/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 7025875 m, 172312 m/sec, 30005546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 40/334 34/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 7885426 m, 171910 m/sec, 33824872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 45/334 37/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 8739852 m, 170885 m/sec, 37656383 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 50/334 41/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 9583218 m, 168673 m/sec, 41433182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 55/334 44/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 10413948 m, 166146 m/sec, 45178549 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 60/334 48/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 11237008 m, 164612 m/sec, 48893422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 65/334 51/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 12048043 m, 162207 m/sec, 52581037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 70/334 54/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 12855129 m, 161417 m/sec, 56248703 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 75/334 58/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 13660077 m, 160989 m/sec, 59905965 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 80/334 61/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 14455684 m, 159121 m/sec, 63538174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 85/334 64/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 15244788 m, 157820 m/sec, 67162676 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 90/334 68/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 16031856 m, 157413 m/sec, 70759049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 95/334 71/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 16810636 m, 155756 m/sec, 74337399 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 100/334 74/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 17581195 m, 154111 m/sec, 77884801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 105/334 77/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 18355935 m, 154948 m/sec, 81451992 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 110/334 80/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 19123837 m, 153580 m/sec, 84992667 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 115/334 84/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 19885323 m, 152297 m/sec, 88516483 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 120/334 87/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 20646129 m, 152161 m/sec, 92043220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 125/334 90/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 21401040 m, 150982 m/sec, 95541019 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 130/334 93/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 22149354 m, 149662 m/sec, 99010799 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 135/334 96/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 22902925 m, 150714 m/sec, 102498304 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 140/334 99/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 23652058 m, 149826 m/sec, 105979515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 145/334 103/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 24393636 m, 148315 m/sec, 109432927 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 150/334 106/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 25136929 m, 148658 m/sec, 112894148 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 155/334 109/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 25883550 m, 149324 m/sec, 116374897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 109
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 160/334 112/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 26629983 m, 149286 m/sec, 119853710 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 165/334 115/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 27372946 m, 148592 m/sec, 123319831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 170/334 118/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 28108468 m, 147104 m/sec, 126760324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 118
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 175/334 121/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 28843316 m, 146969 m/sec, 130198305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 180/334 124/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 29581422 m, 147621 m/sec, 133664644 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 185/334 127/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 30315086 m, 146732 m/sec, 137101851 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 190/334 130/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 31042927 m, 145568 m/sec, 140522974 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 195/334 133/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 31764571 m, 144328 m/sec, 143921370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 133
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 200/334 136/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 32494881 m, 146062 m/sec, 147344656 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 205/334 139/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 33220003 m, 145024 m/sec, 150748787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 210/334 142/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 33942209 m, 144441 m/sec, 154154187 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 142
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 215/334 145/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 34660672 m, 143692 m/sec, 157556470 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 220/334 148/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 35371835 m, 142232 m/sec, 160915895 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 225/334 151/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 36084454 m, 142523 m/sec, 164281201 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 230/334 154/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 36801067 m, 143322 m/sec, 167673337 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 235/334 157/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 37516399 m, 143066 m/sec, 171061140 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 240/334 160/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 38235083 m, 143736 m/sec, 174459509 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 245/334 163/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 38946977 m, 142378 m/sec, 177834290 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 163
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 250/334 166/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 39655720 m, 141748 m/sec, 181188423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 255/334 169/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 40366882 m, 142232 m/sec, 184548032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 260/334 172/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 41075173 m, 141658 m/sec, 187902421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 265/334 175/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 41778812 m, 140727 m/sec, 191238765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 270/334 178/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 42481330 m, 140503 m/sec, 194579876 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 178
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 275/334 181/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 43182473 m, 140228 m/sec, 197911588 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 181
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 280/334 184/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 43887832 m, 141071 m/sec, 201276816 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 285/334 187/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 44585826 m, 139598 m/sec, 204605999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 290/334 190/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 45286596 m, 140154 m/sec, 207938562 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 295/334 193/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 45985425 m, 139765 m/sec, 211266026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 300/334 196/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 46684259 m, 139766 m/sec, 214594216 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 196
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 305/334 198/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 47379641 m, 139076 m/sec, 217908202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 310/334 201/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 48074878 m, 139047 m/sec, 221228928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 201
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 315/334 204/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 48770671 m, 139158 m/sec, 224541370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 320/334 207/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 49460622 m, 137990 m/sec, 227843788 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 575 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 325/334 210/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 50153044 m, 138484 m/sec, 231153438 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 580 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 36 CTL EXCL 330/334 213/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-09 50847896 m, 138970 m/sec, 234468872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 585 secs. Pages in use: 213
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 36 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2024-09 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 590 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 FlexibleBarrier-PT-08a-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 334 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 36 (type EXCL) for 35 FlexibleBarrier-PT-08a-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 3010 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 5/334 5/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 1031201 m, 206240 m/sec, 4358442 t fired, .
[[35mlola[0m][.] 36 CTL EXCL 5/3010 5/5 FlexibleBarrier-PT-08a-CTLFireability-2024-09 1159025 m, -9937774 m/sec, 4610809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 595 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 36 (type EXCL) for FlexibleBarrier-PT-08a-CTLFireability-2024-09 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 10/334 9/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 1999924 m, 193744 m/sec, 8655479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 600 secs. Pages in use: 226
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 15/334 13/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 2897194 m, 179454 m/sec, 12715320 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 605 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 20/334 16/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 3767515 m, 174064 m/sec, 16674984 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 610 secs. Pages in use: 232
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 25/334 20/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 4611636 m, 168824 m/sec, 20584163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 615 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 30/334 23/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 5434098 m, 164492 m/sec, 24399708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 620 secs. Pages in use: 239
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 35/334 27/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 6253535 m, 163887 m/sec, 28223884 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 625 secs. Pages in use: 243
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 40/334 30/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 7070710 m, 163435 m/sec, 32055583 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 630 secs. Pages in use: 246
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 45/334 33/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 7873489 m, 160555 m/sec, 35853543 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 635 secs. Pages in use: 249
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 50/334 37/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 8669628 m, 159227 m/sec, 39631901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 640 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 55/334 40/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 9456600 m, 157394 m/sec, 43384888 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 645 secs. Pages in use: 256
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 60/334 43/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 10240554 m, 156790 m/sec, 47131221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 650 secs. Pages in use: 259
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 65/334 47/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 11013857 m, 154660 m/sec, 50828053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 655 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 70/334 50/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 11780857 m, 153400 m/sec, 54516502 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 660 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 75/334 53/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 12544693 m, 152767 m/sec, 58195931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 665 secs. Pages in use: 269
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 80/334 56/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 13303686 m, 151798 m/sec, 61855545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 670 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 85/334 59/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 14053751 m, 150013 m/sec, 65493800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 675 secs. Pages in use: 275
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 90/334 62/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 14800289 m, 149307 m/sec, 69113681 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 680 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 95/334 66/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 15540815 m, 148105 m/sec, 72727525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 685 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 100/334 69/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 16277407 m, 147318 m/sec, 76326953 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 690 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 105/334 72/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 17007778 m, 146074 m/sec, 79902085 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 695 secs. Pages in use: 288
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 110/334 75/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 17737373 m, 145919 m/sec, 83471550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 700 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 115/334 78/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 18463353 m, 145196 m/sec, 87019520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 705 secs. Pages in use: 294
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 120/334 81/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 19187259 m, 144781 m/sec, 90568051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 710 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 125/334 84/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 19905074 m, 143563 m/sec, 94109807 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 715 secs. Pages in use: 300
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 130/334 87/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 20617888 m, 142562 m/sec, 97631759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 720 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 135/334 90/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 21328586 m, 142139 m/sec, 101129215 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 725 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 140/334 93/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 22037120 m, 141706 m/sec, 104619883 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 730 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 145/334 96/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 22741156 m, 140807 m/sec, 108103237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 735 secs. Pages in use: 312
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 155/334 98/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 23341018 m, 119972 m/sec, 111058928 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 745 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 177/334 98/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 23342121 m, 220 m/sec, 111064520 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 767 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 202/334 98/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 23342315 m, 38 m/sec, 111065503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 792 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 221/334 98/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 23342401 m, 17 m/sec, 111065936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 813 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2024-08: DISJ true findpath[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFlexibleBarrier-PT-08a-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-08a-CTLFireability-2023-14: DISJ true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-01: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-02: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-10: AGEFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-08a-CTLFireability-2023-15: EU 0 1 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 19 CTL EXCL 230/334 98/2000 FlexibleBarrier-PT-08a-CTLFireability-2024-06 23348384 m, 1196 m/sec, 111094806 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 314
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-08a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FlexibleBarrier-PT-08a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r181-tall-171640604400034"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-08a.tgz
mv FlexibleBarrier-PT-08a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;