About the Execution of LoLA for FlexibleBarrier-PT-06a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1376.623 | 115708.00 | 116689.00 | 452.60 | TFFTTTFFTFTFFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r181-tall-171640604300017.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FlexibleBarrier-PT-06a, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r181-tall-171640604300017
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 7.8K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 50K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.6K Apr 13 08:40 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 87K Apr 13 08:40 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.1K Apr 13 08:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 81K Apr 13 08:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 41K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-00
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-01
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-02
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-03
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-04
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-05
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-06
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-07
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-08
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-09
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-10
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2024-11
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2023-12
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2023-13
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2023-14
FORMULA_NAME FlexibleBarrier-PT-06a-CTLCardinality-2023-15
=== Now, execution of the tool begins
BK_START 1717011573146
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2023-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2023-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FlexibleBarrier-PT-06a-CTLCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-00: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG false tscc_search[0m
[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2024-06: INITIAL false preprocessing[0m
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[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-08: CTL true CTL model checker[0m
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[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2023-12: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2023-13: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL false LTL model checker[0m
[[35mlola[0m] [1m[31mFlexibleBarrier-PT-06a-CTLCardinality-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 115 secs. Pages in use: 13
BK_STOP 1717011688854
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 FlexibleBarrier-PT-06a-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 149 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 23 (type CNST) for 22 FlexibleBarrier-PT-06a-CTLCardinality-2024-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 32 (type EXCL) for FlexibleBarrier-PT-06a-CTLCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] FINISHED task # 23 (type CNST) for FlexibleBarrier-PT-06a-CTLCardinality-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 FlexibleBarrier-PT-06a-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for FlexibleBarrier-PT-06a-CTLCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 26 (type CNST) for 25 FlexibleBarrier-PT-06a-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 5 (type EXCL) for 0 FlexibleBarrier-PT-06a-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type CNST) for FlexibleBarrier-PT-06a-CTLCardinality-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 14 (type CNST) for 13 FlexibleBarrier-PT-06a-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 7 FlexibleBarrier-PT-06a-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 7 FlexibleBarrier-PT-06a-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 14 (type CNST) for FlexibleBarrier-PT-06a-CTLCardinality-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for FlexibleBarrier-PT-06a-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for FlexibleBarrier-PT-06a-CTLCardinality-2024-01
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFlexibleBarrier-PT-06a-CTLCardinality-2024-03: INITIAL true preprocessing[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-00: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 5 CTL EXCL 5/299 4/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 864682 m, 172936 m/sec, 3988950 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-00: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 5 CTL EXCL 10/299 7/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 1644849 m, 156033 m/sec, 8057854 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-00: DISJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 5 CTL EXCL 15/299 10/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 2355283 m, 142086 m/sec, 12162884 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 5 CTL EXCL 20/299 13/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 2970565 m, 123056 m/sec, 16622788 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2023-14: LTL/CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 5 CTL EXCL 25/299 13/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 2980163 m, 1919 m/sec, 20857360 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 5 CTL EXCL 35/299 13/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 2985697 m, 354 m/sec, 29117344 t fired, .
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[[35mlola[0m][I] FINISHED task # 47 (type EXCL) for FlexibleBarrier-PT-06a-CTLCardinality-2023-14
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[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] fired transitions : 1889
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] result : false
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 23
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 3/712 3/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-08 675772 m, 135154 m/sec, 2780924 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 13/712 10/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-08 2387389 m, 158047 m/sec, 11466750 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 18/712 13/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-08 2972213 m, 116964 m/sec, 15966114 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 33/712 13/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-08 2985831 m, 329 m/sec, 28489683 t fired, .
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[[35mlola[0m][.] 20 CTL EXCL 3/881 5/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-05 1126156 m, 225231 m/sec, 3885253 t fired, .
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[[35mlola[0m][.] 20 CTL EXCL 8/881 10/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-05 2308186 m, 236406 m/sec, 8823701 t fired, .
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[[35mlola[0m][.] FlexibleBarrier-PT-06a-CTLCardinality-2024-01: EFAG 0 1 0 0 3 0 0 0
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2664663
[[35mlola[0m][I] fired transitions : 18396131
[[35mlola[0m][I] time used : 20
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[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 FlexibleBarrier-PT-06a-CTLCardinality-2024-02
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[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for FlexibleBarrier-PT-06a-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 15
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[[35mlola[0m][.] 3 CTL EXCL 3/1753 4/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 876079 m, 175215 m/sec, 3745802 t fired, .
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[[35mlola[0m][.] 3 CTL EXCL 8/1753 8/2000 FlexibleBarrier-PT-06a-CTLCardinality-2024-00 1863412 m, 197466 m/sec, 8408462 t fired, .
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[[35mlola[0m][I] result : true
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[[35mlola[0m][I] LAUNCH task # 53 (type EXCL) for 7 FlexibleBarrier-PT-06a-CTLCardinality-2024-01
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[[35mlola[0m][I] FINISHED task # 53 (type EXCL) for FlexibleBarrier-PT-06a-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FlexibleBarrier-PT-06a"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FlexibleBarrier-PT-06a, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r181-tall-171640604300017"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FlexibleBarrier-PT-06a.tgz
mv FlexibleBarrier-PT-06a execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;