About the Execution of 2023-gold for FamilyReunion-PT-L00050M0005C002P002G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4368.903 | 624388.00 | 834170.00 | 1849.20 | FTTTTFTTTFTTTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r175-smll-171636280400314.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool gold2023
Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-smll-171636280400314
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 103K Apr 11 20:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 634K Apr 11 20:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 375K Apr 11 20:35 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.3M Apr 11 20:35 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 52K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 226K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 86K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 245K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 233K Apr 11 21:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.5M Apr 11 21:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 818K Apr 11 21:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.9M Apr 11 21:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 41K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.7M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1716655936532
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=gold2023
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=FamilyReunion-PT-L00050M0005C002P002G001
Applying reductions before tool lola
Invoking reducer
Running Version 202304061127
[2024-05-25 16:52:19] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2024-05-25 16:52:19] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2024-05-25 16:52:20] [INFO ] Load time of PNML (sax parser for PT used): 553 ms
[2024-05-25 16:52:20] [INFO ] Transformed 12194 places.
[2024-05-25 16:52:20] [INFO ] Transformed 10560 transitions.
[2024-05-25 16:52:20] [INFO ] Parsed PT model containing 12194 places and 10560 transitions and 32238 arcs in 771 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 1461 ms.
Working with output stream class java.io.PrintStream
Reduce places removed 17 places and 0 transitions.
Incomplete random walk after 10000 steps, including 3 resets, run finished after 1160 ms. (steps per millisecond=8 ) properties (out of 16) seen :3
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 91 ms. (steps per millisecond=109 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 130 ms. (steps per millisecond=76 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 1451 ms. (steps per millisecond=6 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 909 ms. (steps per millisecond=11 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 1062 ms. (steps per millisecond=9 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 83 ms. (steps per millisecond=120 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 194 ms. (steps per millisecond=51 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=208 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 96 ms. (steps per millisecond=104 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 13) seen :0
Running SMT prover for 13 properties.
// Phase 1: matrix 10560 rows 12177 cols
[2024-05-25 16:52:29] [INFO ] Computed 2768 invariants in 1102 ms
[2024-05-25 16:52:40] [INFO ] [Real]Absence check using 149 positive place invariants in 611 ms returned sat
[2024-05-25 16:52:43] [INFO ] [Real]Absence check using 149 positive and 2619 generalized place invariants in 2223 ms returned sat
[2024-05-25 16:52:44] [INFO ] After 11927ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:11
[2024-05-25 16:52:50] [INFO ] [Nat]Absence check using 149 positive place invariants in 588 ms returned sat
[2024-05-25 16:52:52] [INFO ] [Nat]Absence check using 149 positive and 2619 generalized place invariants in 2313 ms returned sat
java.lang.RuntimeException: SMT solver raised an error when submitting script. Raised (error "Failed to assert expression: java.io.IOException: Stream close...
at fr.lip6.move.gal.structural.smt.SMTUtils.execAndCheckResult(SMTUtils.java:251)
at fr.lip6.move.gal.structural.smt.DeadlockTester.checkResults(DeadlockTester.java:800)
at fr.lip6.move.gal.structural.smt.DeadlockTester.verifyPossible(DeadlockTester.java:634)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMTIncremental(DeadlockTester.java:353)
at fr.lip6.move.gal.structural.smt.DeadlockTester.testUnreachableWithSMT(DeadlockTester.java:226)
at fr.lip6.move.gal.application.solver.ReachabilitySolver.applyReductions(ReachabilitySolver.java:96)
at fr.lip6.move.gal.application.Application.startNoEx(Application.java:944)
at fr.lip6.move.gal.application.Application.start(Application.java:182)
at fr.lip6.move.gal.itscl.application.Application.start(Application.java:45)
at org.eclipse.equinox.internal.app.EclipseAppHandle.run(EclipseAppHandle.java:203)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.runApplication(EclipseAppLauncher.java:136)
at org.eclipse.core.runtime.internal.adaptor.EclipseAppLauncher.start(EclipseAppLauncher.java:104)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:402)
at org.eclipse.core.runtime.adaptor.EclipseStarter.run(EclipseStarter.java:255)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:77)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:568)
at org.eclipse.equinox.launcher.Main.invokeFramework(Main.java:659)
at org.eclipse.equinox.launcher.Main.basicRun(Main.java:596)
at org.eclipse.equinox.launcher.Main.run(Main.java:1467)
at org.eclipse.equinox.launcher.Main.main(Main.java:1440)
[2024-05-25 16:53:09] [WARNING] SMT solver failed with error :SMT solver raised an error when submitting script.... while checking expressions.
[2024-05-25 16:53:09] [INFO ] After 25045ms SMT Verify possible using all constraints in natural domain returned unsat :2 sat :0 real:11
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 13 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 1 ms.
Support contains 3712 out of 12177 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 12177/12177 places, 10560/10560 transitions.
Graph (complete) has 18927 edges and 12177 vertex of which 12112 are kept as prefixes of interest. Removing 65 places using SCC suffix rule.60 ms
Discarding 65 places :
Also discarding 0 output transitions
Discarding 914 places :
Implicit places reduction removed 914 places
Drop transitions removed 1043 transitions
Trivial Post-agglo rules discarded 1043 transitions
Performed 1043 trivial Post agglomeration. Transition count delta: 1043
Iterating post reduction 0 with 1957 rules applied. Total rules applied 1958 place count 11198 transition count 9517
Reduce places removed 1043 places and 0 transitions.
Performed 856 Post agglomeration using F-continuation condition.Transition count delta: 856
Iterating post reduction 1 with 1899 rules applied. Total rules applied 3857 place count 10155 transition count 8661
Reduce places removed 856 places and 0 transitions.
Iterating post reduction 2 with 856 rules applied. Total rules applied 4713 place count 9299 transition count 8661
Performed 406 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 406 Pre rules applied. Total rules applied 4713 place count 9299 transition count 8255
Deduced a syphon composed of 406 places in 58 ms
Ensure Unique test removed 151 places
Reduce places removed 557 places and 0 transitions.
Iterating global reduction 3 with 963 rules applied. Total rules applied 5676 place count 8742 transition count 8255
Discarding 3 places :
Implicit places reduction removed 3 places
Performed 149 Post agglomeration using F-continuation condition.Transition count delta: 149
Iterating post reduction 3 with 152 rules applied. Total rules applied 5828 place count 8739 transition count 8106
Reduce places removed 149 places and 0 transitions.
Iterating post reduction 4 with 149 rules applied. Total rules applied 5977 place count 8590 transition count 8106
Discarding 756 places :
Symmetric choice reduction at 5 with 756 rule applications. Total rules 6733 place count 7834 transition count 7300
Iterating global reduction 5 with 756 rules applied. Total rules applied 7489 place count 7834 transition count 7300
Ensure Unique test removed 102 transitions
Reduce isomorphic transitions removed 102 transitions.
Discarding 50 places :
Implicit places reduction removed 50 places
Drop transitions removed 98 transitions
Trivial Post-agglo rules discarded 98 transitions
Performed 98 trivial Post agglomeration. Transition count delta: 98
Iterating post reduction 5 with 250 rules applied. Total rules applied 7739 place count 7784 transition count 7100
Reduce places removed 98 places and 0 transitions.
Iterating post reduction 6 with 98 rules applied. Total rules applied 7837 place count 7686 transition count 7100
Performed 51 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 7 with 51 Pre rules applied. Total rules applied 7837 place count 7686 transition count 7049
Deduced a syphon composed of 51 places in 15 ms
Ensure Unique test removed 49 places
Reduce places removed 100 places and 0 transitions.
Iterating global reduction 7 with 151 rules applied. Total rules applied 7988 place count 7586 transition count 7049
Discarding 2 places :
Symmetric choice reduction at 7 with 2 rule applications. Total rules 7990 place count 7584 transition count 6947
Iterating global reduction 7 with 2 rules applied. Total rules applied 7992 place count 7584 transition count 6947
Discarding 100 places :
Symmetric choice reduction at 7 with 100 rule applications. Total rules 8092 place count 7484 transition count 6847
Iterating global reduction 7 with 100 rules applied. Total rules applied 8192 place count 7484 transition count 6847
Performed 100 Post agglomeration using F-continuation condition.Transition count delta: 100
Deduced a syphon composed of 100 places in 9 ms
Ensure Unique test removed 47 places
Reduce places removed 147 places and 0 transitions.
Iterating global reduction 7 with 247 rules applied. Total rules applied 8439 place count 7337 transition count 6747
Free-agglomeration rule (complex) applied 196 times.
Iterating global reduction 7 with 196 rules applied. Total rules applied 8635 place count 7337 transition count 6551
Ensure Unique test removed 51 places
Reduce places removed 247 places and 0 transitions.
Iterating post reduction 7 with 247 rules applied. Total rules applied 8882 place count 7090 transition count 6551
Partial Post-agglomeration rule applied 4 times.
Drop transitions removed 4 transitions
Iterating global reduction 8 with 4 rules applied. Total rules applied 8886 place count 7090 transition count 6551
Applied a total of 8886 rules in 7138 ms. Remains 7090 /12177 variables (removed 5087) and now considering 6551/10560 (removed 4009) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 7141 ms. Remains : 7090/12177 places, 6551/10560 transitions.
Incomplete random walk after 10000 steps, including 5 resets, run finished after 500 ms. (steps per millisecond=20 ) properties (out of 7) seen :2
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 109 ms. (steps per millisecond=91 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 62 ms. (steps per millisecond=161 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
// Phase 1: matrix 6551 rows 7090 cols
[2024-05-25 16:53:18] [INFO ] Computed 1445 invariants in 295 ms
[2024-05-25 16:53:20] [INFO ] [Real]Absence check using 148 positive place invariants in 356 ms returned sat
[2024-05-25 16:53:21] [INFO ] [Real]Absence check using 148 positive and 1297 generalized place invariants in 932 ms returned sat
[2024-05-25 16:53:21] [INFO ] After 3633ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2024-05-25 16:53:23] [INFO ] [Nat]Absence check using 148 positive place invariants in 213 ms returned sat
[2024-05-25 16:53:24] [INFO ] [Nat]Absence check using 148 positive and 1297 generalized place invariants in 798 ms returned sat
[2024-05-25 16:53:46] [INFO ] After 20509ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :5
[2024-05-25 16:53:46] [INFO ] After 21264ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 5 ms.
[2024-05-25 16:53:46] [INFO ] After 25054ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12 TRUE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Finished Parikh walk after 756 steps, including 0 resets, run visited all 1 properties in 11 ms. (steps per millisecond=68 )
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15 FALSE TECHNIQUES TOPOLOGICAL PARIKH_WALK
Parikh walk visited 5 properties in 288 ms.
All properties solved without resorting to model-checking.
Total runtime 87278 ms.
starting LoLA
BK_INPUT FamilyReunion-PT-L00050M0005C002P002G001
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1716656560920
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202304061127.jar
+ VERSION=202304061127
+ echo 'Running Version 202304061127'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 50 (type SKEL/FNDP) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type SKEL/EQUN) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/SRCH) for 0 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: result : true
lola: markings : 1451
lola: fired transitions : 1450
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 50 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 51 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00 (obsolete)
lola: CANCELED task # 54 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00 (obsolete)
lola: FINISHED task # 50 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: result : unknown
lola: fired transitions : 1072
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 51 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 57 (type SKEL/FNDP) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type SKEL/EQUN) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type SKEL/SRCH) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type SKEL/SRCH) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: result : true
lola: markings : 803
lola: fired transitions : 802
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 58 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 60 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: FINISHED task # 57 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: result : unknown
lola: fired transitions : 162
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 58 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type SKEL/FNDP) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type SKEL/EQUN) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 68 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 69 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 68 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: result : false
lola: markings : 562
lola: fired transitions : 561
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 65 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 (obsolete)
lola: CANCELED task # 66 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 (obsolete)
lola: CANCELED task # 69 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 (obsolete)
lola: FINISHED task # 65 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: result : unknown
lola: fired transitions : 16135
lola: tried executions : 30
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 66 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01
lola: result : unknown
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type SKEL/FNDP) for 9 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SKEL/EQUN) for 9 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 76 (type SKEL/SRCH) for 9 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 9 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Rule S: 0 transitions removed,0 places removed
lola: FINISHED task # 76 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: result : false
lola: markings : 1888
lola: fired transitions : 1887
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 73 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 (obsolete)
lola: CANCELED task # 74 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 (obsolete)
lola: CANCELED task # 77 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 (obsolete)
lola: FINISHED task # 77 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: result : false
lola: markings : 2942
lola: fired transitions : 2943
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 73 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: result : unknown
lola: fired transitions : 5575
lola: tried executions : 4
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-74.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 74 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: planning for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03 stopped (result already fixed).
lola: planning for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01 stopped (result already fixed).
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 80 (type SKEL/FNDP) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type SKEL/SRCH) for 36 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 83 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12
lola: result : true
lola: markings : 5
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 80 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12 (obsolete)
lola: CANCELED task # 81 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12 (obsolete)
lola: CANCELED task # 84 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12 (obsolete)
lola: LAUNCH task # 88 (type SKEL/FNDP) for 12 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SKEL/EQUN) for 12 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 91 (type SKEL/SRCH) for 12 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SKEL/SRCH) for 12 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 91 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04
lola: result : false
lola: markings : 189
lola: fired transitions : 189
lola: time used : 0.000000
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lola: CANCELED task # 88 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04 (obsolete)
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: CANCELED task # 184 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-181.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-175.sara.
lola: planning for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04 stopped (result already fixed).
lola: planning for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06 stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06: AG true skeleton: state equation
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15: AG false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07: EF 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10: AG 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 190 (type EXCL) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 771 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 186 (type FNDP) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 187 (type EQUN) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 189 (type SRCH) for 6 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 186 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02
lola: result : true
lola: fired transitions : 374
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 187 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 189 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: CANCELED task # 190 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02 (obsolete)
lola: LAUNCH task # 197 (type EXCL) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
lola: time limit : 1028 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 193 (type FNDP) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 194 (type EQUN) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 196 (type SRCH) for 30 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 196 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10
lola: result : false
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 193 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10 (obsolete)
lola: CANCELED task # 194 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10 (obsolete)
lola: CANCELED task # 197 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10 (obsolete)
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-187.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-194.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06: AG true skeleton: state equation
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10: AG true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15: AG false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 518 secs. Pages in use: 3
# running tasks: 0 of 4 Visible: 16
lola: FINISHED task # 128 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06: AG true skeleton: state equation
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10: AG true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15: AG false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05: AG 0 0 0 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 204 (type EXCL) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: time limit : 1536 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 200 (type FNDP) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 201 (type EQUN) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 203 (type SRCH) for 15 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06: AG true skeleton: state equation
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10: AG true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15: AG false tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05: AG 0 1 4 0 3 0 0 2
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07: EF 0 0 0 0 3 0 0 2
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
200 EF FNDP 1/1536 0/5 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 526 t fired, 1 attempts, .
201 EF STEQ 1/3073 0/5 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 sara not yet started (preprocessing).
203 EF SRCH 1/3073 1/5 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 507 m, 101 m/sec, 506 t fired, .
204 EF EXCL 1/1536 1/32 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 196 m, 39 m/sec, 195 t fired, .
Time elapsed: 528 secs. Pages in use: 3
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lola: FINISHED task # 200 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: result : true
lola: fired transitions : 644
lola: tried executions : 1
lola: time used : 2.000000
lola: memory pages used : 0
lola: CANCELED task # 201 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 (obsolete)
lola: CANCELED task # 203 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 (obsolete)
lola: CANCELED task # 204 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05 (obsolete)
lola: FINISHED task # 201 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05
lola: result : unknown
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 210 (type EXCL) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
lola: time limit : 3068 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 206 (type FNDP) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 207 (type EQUN) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 209 (type SRCH) for 21 FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 209 (type SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07
lola: result : true
lola: markings : 97
lola: fired transitions : 96
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 206 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07 (obsolete)
lola: CANCELED task # 207 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07 (obsolete)
lola: CANCELED task # 210 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07 (obsolete)
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-00: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-01: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-02: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-03: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-04: AG true skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-05: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-06: AG true skeleton: state equation
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-07: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-08: EF true findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-09: AG false tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-10: AG true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-11: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-12: EF true tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-13: EF false skeleton: tandem / insertion
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-14: AG false findpath
FamilyReunion-PT-L00050M0005C002P002G001-ReachabilityCardinality-2024-15: AG false tandem / insertion
Time elapsed: 532 secs. Pages in use: 3
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00050M0005C002P002G001"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="gold2023"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool gold2023"
echo " Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-smll-171636280400314"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00050M0005C002P002G001.tgz
mv FamilyReunion-PT-L00050M0005C002P002G001 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;