About the Execution of LoLA for FamilyReunion-PT-L00100M0010C005P005G002
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16154.359 | 1968842.00 | 5577900.00 | 3026.70 | ???????T?F???T?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268200505.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-PT-L00100M0010C005P005G002, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268200505
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 37M
-rw-r--r-- 1 mcc users 461K Apr 11 21:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 2.8M Apr 11 21:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 660K Apr 11 21:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 2.3M Apr 11 21:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 149K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 584K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 407K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 1.1M Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 854K Apr 11 23:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 5.1M Apr 11 23:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 1.3M Apr 11 22:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 4.4M Apr 11 22:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 43K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 130K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 17M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14
FORMULA_NAME FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717212579761
FORMULA FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717214548603
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 66 (type SKEL/SRCH) for 3 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 66 LTL SRCH 4/2981 1/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 1134789 m, 226957 m/sec, 1598353 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 66 LTL SRCH 9/2981 1/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 2591157 m, 291273 m/sec, 3675666 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 66 LTL SRCH 14/2981 1/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 4034654 m, 288699 m/sec, 5732859 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] 66 LTL SRCH 19/2981 1/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 5410023 m, 275073 m/sec, 7707310 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] 66 LTL SRCH 24/2981 1/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 6768904 m, 271776 m/sec, 9644683 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 29/2981 2/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 8170456 m, 280310 m/sec, 11662711 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 34/2981 2/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 9515813 m, 269071 m/sec, 13604711 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 39/2981 2/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 10870248 m, 270887 m/sec, 15543505 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 44/2981 2/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12215614 m, 269073 m/sec, 17484803 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 49/2981 2/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 13537008 m, 264278 m/sec, 19374420 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 54/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 14865747 m, 265747 m/sec, 21314986 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 59/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 16317071 m, 290264 m/sec, 23389190 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 64/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 17642697 m, 265125 m/sec, 25295643 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 69/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 18884803 m, 248421 m/sec, 27107493 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 74/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 20196599 m, 262359 m/sec, 28982462 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 79/2981 3/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 21452978 m, 251275 m/sec, 30796986 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 84/2981 4/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 22651894 m, 239783 m/sec, 32566713 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 89/2981 4/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 24014460 m, 272513 m/sec, 34501009 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 94/2981 4/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 25287697 m, 254647 m/sec, 36325150 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 99/2981 4/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 26543343 m, 251129 m/sec, 38138699 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 104/2981 4/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 27768358 m, 245003 m/sec, 39952980 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 109/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 29160069 m, 278342 m/sec, 41952894 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 114/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 30577686 m, 283523 m/sec, 43987801 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 119/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 31911793 m, 266821 m/sec, 45912016 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 124/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 33229490 m, 263539 m/sec, 47810784 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 129/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 34463560 m, 246814 m/sec, 49591090 t fired, .
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[[35mlola[0m][.] 66 LTL SRCH 134/2981 5/5 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 35671141 m, 241516 m/sec, 51358950 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] LAUNCH task # 26 (type CNST) for 25 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 26 (type CNST) for FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-07
[[35mlola[0m][I] result : true
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][I] LAUNCH task # 67 (type SKEL/SRCH) for 31 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 67 (type SKEL/SRCH) for FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5782
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ false skeleton: LTL model checker[0m
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-09: CONJ false skeleton: LTL model checker[0m
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/FNDP) for 49 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/EQUN) for 49 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11
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[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 49 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11
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[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
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[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11 (obsolete)
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[[35mlola[0m][I] result : true
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 2 0 0 1
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 2 0 0 1
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 2 0 0 1
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-11: AG 0 0 0 0 2 0 0 1
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13: EG 0 0 2 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-14: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 78 EG EXCL 7/149 1/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-13 2020 m, 338 m/sec, 2019 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01: CONJ 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 83 LTL EXCL 0/151 1/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 74 m, 14 m/sec, 73 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 5/151 1/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 3931 m, 771 m/sec, 4362 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 10/151 1/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 5471 m, 308 m/sec, 7311 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 15/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 6754 m, 256 m/sec, 9699 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 20/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 8333 m, 315 m/sec, 12809 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 25/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 10887 m, 510 m/sec, 17899 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 30/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12178 m, 258 m/sec, 20725 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 35/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 13759 m, 316 m/sec, 24861 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 40/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 15342 m, 316 m/sec, 29162 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 45/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 18237 m, 579 m/sec, 36786 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 50/151 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 20350 m, 422 m/sec, 41526 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 55/151 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 22392 m, 408 m/sec, 46517 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 60/151 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 23354 m, 192 m/sec, 48959 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 65/151 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 24549 m, 239 m/sec, 52032 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 70/163 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 26245 m, 339 m/sec, 56737 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 75/163 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 30132 m, 777 m/sec, 67997 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 80/163 4/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 35256 m, 1024 m/sec, 77002 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 110/163 5/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 50962 m, 567 m/sec, 112020 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 115/163 5/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 53717 m, 551 m/sec, 118859 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 120/163 5/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 55915 m, 439 m/sec, 124785 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 125/163 5/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 58108 m, 438 m/sec, 131188 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 130/163 6/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 61492 m, 676 m/sec, 138551 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 135/163 6/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 62746 m, 250 m/sec, 140838 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 20/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 8079 m, 319 m/sec, 12289 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 25/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 10265 m, 437 m/sec, 17072 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 30/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 11513 m, 249 m/sec, 19266 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 35/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12409 m, 179 m/sec, 21295 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 40/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12992 m, 116 m/sec, 22998 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 45/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 13563 m, 114 m/sec, 24327 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 50/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 14221 m, 131 m/sec, 26124 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 55/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 14794 m, 114 m/sec, 27680 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 60/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 15363 m, 113 m/sec, 29217 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 65/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 15995 m, 126 m/sec, 30955 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 70/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 17210 m, 243 m/sec, 34796 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 80/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 19608 m, 192 m/sec, 39768 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 85/150 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 20667 m, 211 m/sec, 42251 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 90/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 21874 m, 241 m/sec, 44950 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 95/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 22829 m, 191 m/sec, 47731 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 100/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 23824 m, 199 m/sec, 49998 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 105/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 25288 m, 292 m/sec, 54073 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 110/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 26739 m, 290 m/sec, 58120 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 115/150 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 28403 m, 332 m/sec, 63036 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 130/150 4/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 35702 m, 305 m/sec, 77782 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 15/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 6406 m, 265 m/sec, 9007 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 20/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 7940 m, 306 m/sec, 12018 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 25/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 9749 m, 361 m/sec, 16160 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 30/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 11264 m, 303 m/sec, 18764 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 35/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12285 m, 204 m/sec, 20958 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 40/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 12967 m, 136 m/sec, 22931 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 45/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 13655 m, 137 m/sec, 24586 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 50/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 14448 m, 158 m/sec, 26748 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 55/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 15214 m, 153 m/sec, 28813 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 60/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 16018 m, 160 m/sec, 31014 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 65/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 17333 m, 263 m/sec, 35194 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 75/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 19452 m, 171 m/sec, 39442 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 80/138 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 20331 m, 175 m/sec, 41475 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 85/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 21439 m, 221 m/sec, 43883 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 90/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 22381 m, 188 m/sec, 46487 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 95/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 23251 m, 174 m/sec, 48750 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 100/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 24003 m, 150 m/sec, 50506 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 105/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 24876 m, 174 m/sec, 52942 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 110/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 25778 m, 180 m/sec, 55452 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 115/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 26571 m, 158 m/sec, 57640 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 120/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 27421 m, 170 m/sec, 60017 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 125/138 3/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 28277 m, 171 m/sec, 62683 t fired, .
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[[35mlola[0m][.] 83 LTL EXCL 25/127 2/2000 FamilyReunion-PT-L00100M0010C005P005G002-CTLCardinality-2024-01 11024 m, 463 m/sec, 18229 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00100M0010C005P005G002"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00100M0010C005P005G002, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268200505"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00100M0010C005P005G002.tgz
mv FamilyReunion-PT-L00100M0010C005P005G002 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;