About the Execution of LoLA for FamilyReunion-PT-L00050M0005C002P002G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 15076.684 | 3600000.00 | 4182775.00 | 13241.40 | [undef] | Time out reached |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268200500.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268200500
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 103K Apr 11 20:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 634K Apr 11 20:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 375K Apr 11 20:35 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.3M Apr 11 20:35 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 52K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 226K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 86K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 245K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 233K Apr 11 21:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.5M Apr 11 21:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 818K Apr 11 21:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.9M Apr 11 21:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 41K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.7M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-00
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-01
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-02
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-04
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-05
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-06
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-07
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-09
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-10
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-11
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-12
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-14
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717209002260
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-04: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-06: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-09: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-15: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 9 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 52 (type SKEL/SRCH) for 24 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-15: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL SRCH 2/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 38536 m, 7707 m/sec, 128771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 14 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-15: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 52 LTL SRCH 7/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 129851 m, 18263 m/sec, 485748 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 19 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08: LTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 52 LTL SRCH 12/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 204896 m, 15009 m/sec, 829337 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 17/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 277047 m, 14430 m/sec, 1156007 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 22/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 352000 m, 14990 m/sec, 1491984 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 27/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 431324 m, 15864 m/sec, 1858106 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 32/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 502747 m, 14284 m/sec, 2237628 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 37/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 592475 m, 17945 m/sec, 2634856 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 42/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 660196 m, 13544 m/sec, 2939503 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 47/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 727258 m, 13412 m/sec, 3238555 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 29/209 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 45077 m, 1250 m/sec, 154122 t fired, .
[[35mlola[0m][.] 52 LTL SRCH 52/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 797201 m, 13988 m/sec, 3544762 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 57/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 868037 m, 14167 m/sec, 3859077 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 62/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 944345 m, 15261 m/sec, 4191980 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 67/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 1042715 m, 19674 m/sec, 4615206 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 87/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 2279779 m, 59949 m/sec, 10929122 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 97/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 2845721 m, 50487 m/sec, 14022686 t fired, .
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[[35mlola[0m][.] 52 LTL SRCH 102/3588 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 3137756 m, 58407 m/sec, 15587208 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 144/209 8/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 449754 m, 3872 m/sec, 1759388 t fired, .
[[35mlola[0m][.] 52 LTL SRCH 167/3588 2/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 6963076 m, 49886 m/sec, 36756815 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 159/209 9/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 508139 m, 3842 m/sec, 1993374 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 179/209 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 582949 m, 3503 m/sec, 2313036 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 184/209 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 601026 m, 3615 m/sec, 2397734 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 189/209 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 617860 m, 3366 m/sec, 2488667 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 194/209 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 639247 m, 4277 m/sec, 2562023 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 199/209 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 660993 m, 4349 m/sec, 2631693 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 204/209 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 680419 m, 3885 m/sec, 2709737 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 5/209 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 21210 m, -136412 m/sec, 66819 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 10/209 1/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 41489 m, 4055 m/sec, 141819 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 15/209 2/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 61313 m, 3964 m/sec, 217923 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 20/209 2/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 80297 m, 3796 m/sec, 297541 t fired, .
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[[35mlola[0m][.] 40 LTL EXCL 25/209 2/5 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-13 100011 m, 3942 m/sec, 372450 t fired, .
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[[35mlola[0m][.] 25 LTL EXCL 20/273 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 83520 m, 3636 m/sec, 325468 t fired, .
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[[35mlola[0m][.] 25 LTL EXCL 25/273 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 101664 m, 3628 m/sec, 409630 t fired, .
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[[35mlola[0m][.] 25 LTL EXCL 30/273 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 118772 m, 3421 m/sec, 493941 t fired, .
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[[35mlola[0m][.] 25 LTL EXCL 35/273 4/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-08 137368 m, 3719 m/sec, 577659 t fired, .
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[[35mlola[0m][.] 10 LTL EXCL 265/381 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03 1205957 m, 4593 m/sec, 3951826 t fired, .
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[[35mlola[0m][.] 10 LTL EXCL 270/381 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03 1230087 m, 4826 m/sec, 4026380 t fired, .
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[[35mlola[0m][.] 10 LTL EXCL 275/381 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03 1253040 m, 4590 m/sec, 4101432 t fired, .
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[[35mlola[0m][.] 10 LTL EXCL 280/381 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-LTLFireability-03 1274011 m, 4194 m/sec, 4177943 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00050M0005C002P002G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268200500"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00050M0005C002P002G001.tgz
mv FamilyReunion-PT-L00050M0005C002P002G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;