About the Execution of LoLA for FamilyReunion-PT-L00050M0005C002P002G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.899 | 2267786.00 | 2570948.00 | 7547.20 | ????F?????T????F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268200498.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268200498
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 14M
-rw-r--r-- 1 mcc users 103K Apr 11 20:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 634K Apr 11 20:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 375K Apr 11 20:35 CTLFireability.txt
-rw-r--r-- 1 mcc users 1.3M Apr 11 20:35 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 52K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 226K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 86K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 245K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 233K Apr 11 21:44 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 1.5M Apr 11 21:44 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 818K Apr 11 21:25 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 2.9M Apr 11 21:25 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 41K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 4.7M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14
FORMULA_NAME FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717206197257
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717208465043
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/FNDP) for 12 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 75 (type SKEL/EQUN) for 12 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/SRCH) for 12 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 37
[[35mlola[0m][I] fired transitions : 36
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 74 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 75 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 75 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 13 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 80 (type SKEL/EQUN) for 31 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 31 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 80 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 (obsolete)
[[35mlola[0m][I] FINISHED task # 80 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 5 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 82 (type SKEL/FNDP) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 83 (type SKEL/EQUN) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 84 (type SKEL/SRCH) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 44
[[35mlola[0m][I] fired transitions : 43
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 82 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 83 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 82 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 83 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 87 (type SKEL/FNDP) for 69 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 88 (type SKEL/EQUN) for 69 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 89 (type SKEL/SRCH) for 69 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 89 (type SKEL/SRCH) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 135
[[35mlola[0m][I] fired transitions : 134
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 87 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][W] CANCELED task # 88 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][I] FINISHED task # 87 (type SKEL/FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 88 (type SKEL/EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 7 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 7 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 7 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[*** LOG ERROR #0001 ***] [2024-06-01 01:43:52] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 38 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 92 (type EXCL) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 197 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 90 (type FNDP) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 91 (type EQUN) for 54 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 90 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 91 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][W] CANCELED task # 92 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] FINISHED task # 91 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG 0 0 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 43 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 60 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12
[[35mlola[0m][I] time limit : 222 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 94 (type FNDP) for 12 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 95 (type EQUN) for 12 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 94 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 95 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 95 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 98 (type FNDP) for 69 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 99 (type EQUN) for 69 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 98 (type FNDP) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 99 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15 (obsolete)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 2/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 4993 m, 998 m/sec, 17462 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 7/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 13333 m, 1668 m/sec, 54976 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 12/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 20785 m, 1490 m/sec, 94265 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] FINISHED task # 99 (type EQUN) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 17/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 28350 m, 1513 m/sec, 133806 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 22/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 35658 m, 1461 m/sec, 173336 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 8 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 27/236 1/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 42780 m, 1424 m/sec, 213869 t fired, .
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[*** LOG ERROR #0002 ***] [2024-06-01 01:44:32] [status_logger] string pointer is null
[*** LOG ERROR #0004 ***] [2024-06-01 01:44:33] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-04: AG false findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-10: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-15: AG false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 61 CTL EXCL 32/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 58160 m, 3076 m/sec, 302242 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 61 CTL EXCL 37/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 75824 m, 3532 m/sec, 397948 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 42/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 90212 m, 2877 m/sec, 480157 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 47/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 103871 m, 2731 m/sec, 554459 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 52/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 114427 m, 2111 m/sec, 614176 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 57/236 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 125494 m, 2213 m/sec, 673206 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 63/236 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 143175 m, 3536 m/sec, 791704 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 68/236 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 177590 m, 6883 m/sec, 987911 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 73/236 4/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 208502 m, 6182 m/sec, 1188140 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 61 CTL EXCL 78/236 4/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 237009 m, 5701 m/sec, 1375460 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 83/236 5/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 265679 m, 5734 m/sec, 1564735 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 88/236 5/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 294266 m, 5717 m/sec, 1763546 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 93/236 5/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 323407 m, 5828 m/sec, 1941089 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 98/236 6/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 356135 m, 6545 m/sec, 2140217 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 103/236 6/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 386364 m, 6045 m/sec, 2339928 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 108/236 7/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 415475 m, 5822 m/sec, 2538307 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 113/236 7/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 441833 m, 5271 m/sec, 2722251 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 118/236 8/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 470812 m, 5795 m/sec, 2915989 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 123/236 8/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 500545 m, 5946 m/sec, 3110102 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 128/236 8/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 529024 m, 5695 m/sec, 3302021 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 133/236 9/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 555606 m, 5316 m/sec, 3489982 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 138/236 9/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 582336 m, 5346 m/sec, 3689772 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 143/236 9/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 612511 m, 6035 m/sec, 3887661 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 148/236 10/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 641328 m, 5763 m/sec, 4086377 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 153/236 10/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 669556 m, 5645 m/sec, 4283929 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 158/236 10/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 700030 m, 6094 m/sec, 4480855 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 163/236 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 727565 m, 5507 m/sec, 4679096 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 168/236 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 751095 m, 4706 m/sec, 4879624 t fired, .
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[[35mlola[0m][.] 61 CTL EXCL 173/236 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 779256 m, 5632 m/sec, 5078627 t fired, .
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[[35mlola[0m][.] 61 CTL EXCL 178/236 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 812109 m, 6570 m/sec, 5276664 t fired, .
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[[35mlola[0m][.] 61 CTL EXCL 183/236 13/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 842931 m, 6164 m/sec, 5475282 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 188/236 13/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 872553 m, 5924 m/sec, 5674227 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 193/236 14/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 902907 m, 6070 m/sec, 5871782 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 198/236 14/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 931951 m, 5808 m/sec, 6070205 t fired, .
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[[35mlola[0m][.] 61 CTL EXCL 203/236 14/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 961958 m, 6001 m/sec, 6267344 t fired, .
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[[35mlola[0m][.] 61 CTL EXCL 208/236 15/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 988516 m, 5311 m/sec, 6466070 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 228/236 16/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 1103123 m, 5545 m/sec, 7254447 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 233/236 16/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 1131518 m, 5679 m/sec, 7451929 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 66 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14
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[[35mlola[0m][I] LAUNCH task # 61 (type EXCL) for 60 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12
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[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-14
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[[35mlola[0m][I] time used : 1
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 4/236 1/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 35825 m, -219138 m/sec, 174231 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 9/236 2/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 71613 m, 7157 m/sec, 373192 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 14/236 2/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 105098 m, 6697 m/sec, 561101 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 19/236 3/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 136706 m, 6321 m/sec, 742734 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 24/236 3/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 167864 m, 6231 m/sec, 925086 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 29/236 4/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 198870 m, 6201 m/sec, 1123667 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 34/236 4/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 229117 m, 6049 m/sec, 1323063 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 61 CTL EXCL 39/236 5/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12 259408 m, 6058 m/sec, 1522045 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 64 CTL EXCL 15/250 5/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 58868 m, 3768 m/sec, 256184 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 64 CTL EXCL 45/250 10/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 163137 m, 3236 m/sec, 782029 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 64 CTL EXCL 50/250 11/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 180992 m, 3571 m/sec, 869612 t fired, .
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[[35mlola[0m][.] 64 CTL EXCL 55/250 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 199433 m, 3688 m/sec, 956523 t fired, .
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[[35mlola[0m][.] 64 CTL EXCL 60/250 13/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 216546 m, 3422 m/sec, 1043319 t fired, .
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[[35mlola[0m][.] 64 CTL EXCL 65/250 14/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 233775 m, 3445 m/sec, 1130193 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 64 CTL EXCL 85/250 17/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 299637 m, 3626 m/sec, 1478987 t fired, .
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[[35mlola[0m][.] 64 CTL EXCL 100/250 19/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 348903 m, 3351 m/sec, 1735304 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 64 CTL EXCL 160/250 28/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 539666 m, 3067 m/sec, 2787577 t fired, .
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[[35mlola[0m][.] 64 CTL EXCL 175/250 30/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 582472 m, 2830 m/sec, 3047212 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 64 CTL EXCL 9/231 3/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 37319 m, 3620 m/sec, 155824 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 58 CTL EXCL 20/250 6/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11 76547 m, 3735 m/sec, 329572 t fired, .
[[35mlola[0m][.] 64 CTL EXCL 19/231 5/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13 74355 m, 3667 m/sec, 329016 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 58 CTL EXCL 25/250 7/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11 94772 m, 3645 m/sec, 416597 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 58 CTL EXCL 30/250 8/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11 112180 m, 3481 m/sec, 503746 t fired, .
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[[35mlola[0m][.] 58 CTL EXCL 35/250 9/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11 129305 m, 3425 m/sec, 590945 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 58 CTL EXCL 250/250 44/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11 796751 m, 2531 m/sec, 4278542 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 2 0 0 11 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 1 0 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 1 0 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 50 CTL EXCL 5/272 3/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 26446 m, 5289 m/sec, 79391 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 50 CTL EXCL 45/272 12/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 192321 m, 4584 m/sec, 732583 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 50 CTL EXCL 120/272 25/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 481322 m, 3842 m/sec, 1977990 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 50 CTL EXCL 160/272 32/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 614607 m, 3184 m/sec, 2636772 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 1 0 12 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 5/272 2/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08 24946 m, 4989 m/sec, 74161 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 9/245 4/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 47680 m, 4488 m/sec, 160854 t fired, .
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[[35mlola[0m][.] 50 CTL EXCL 14/245 5/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09 70951 m, 4654 m/sec, 246364 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 110/272 24/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08 451070 m, 3528 m/sec, 1876506 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 12 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 29 CTL EXCL 265/272 53/2000 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08 987426 m, 3222 m/sec, 4566197 t fired, .
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 12 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 12 0 1 0
[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 29 CTL EXCL 4/2176 2/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08 22261 m, -196666 m/sec, 63888 t fired, .
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[[35mlola[0m][.] 29 CTL EXCL 14/241 5/5 FamilyReunion-PT-L00050M0005C002P002G001-CTLFireability-2024-08 64345 m, 4361 m/sec, 221400 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00050M0005C002P002G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00050M0005C002P002G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268200498"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00050M0005C002P002G001.tgz
mv FamilyReunion-PT-L00050M0005C002P002G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;