About the Execution of LoLA for FamilyReunion-PT-L00010M0001C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.527 | 1791292.00 | 1521101.00 | 10368.80 | ???????F????F??? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268100484.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268100484
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.8M
-rw-r--r-- 1 mcc users 20K Apr 11 20:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 151K Apr 11 20:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 26K Apr 11 20:15 CTLFireability.txt
-rw-r--r-- 1 mcc users 115K Apr 11 20:15 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 11K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 55K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 15K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 50K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 58K Apr 11 20:29 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 440K Apr 11 20:29 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 57K Apr 11 20:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 220K Apr 11 20:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.9K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 7.3K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 552K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-00
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-02
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-03
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-04
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-05
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-06
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-09
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-10
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-11
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-13
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-14
FORMULA_NAME FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717198558062
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717200349354
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/FNDP) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/EQUN) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 28 (type CNST) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07 (obsolete)
[[35mlola[0m][W] CANCELED task # 72 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07 (obsolete)
[[35mlola[0m][I] FINISHED task # 71 (type SKEL/EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01
[[35mlola[0m][I] time limit : 124 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 73 (type SKEL/SRCH) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type SKEL/SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/FNDP) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/EQUN) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12 (obsolete)
[[35mlola[0m][W] CANCELED task # 78 (type SRCH) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12 (obsolete)
[[35mlola[0m][I] LAUNCH task # 80 (type FNDP) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 25 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 84 (type FNDP) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 77 (type SKEL/EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 80 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 81 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07 (obsolete)
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 48 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type FNDP) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 85 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12 (obsolete)
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07
[[35mlola[0m][I] result : true
[*** LOG ERROR #0001 ***] [2024-05-31 23:35:59] [status_logger] string pointer is null
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 5/240 6/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01 567885 m, 113577 m/sec, 702586 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 10/240 13/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01 1315941 m, 149611 m/sec, 1662678 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 4 LTL EXCL 15/240 21/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01 2030619 m, 142935 m/sec, 2630961 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 21
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-07: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-12: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-01: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-04: CONJ 0 2 0 0 2 0 0 0
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[[35mlola[0m][.] 37 LTL EXCL 120/372 25/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08 2800305 m, 21528 m/sec, 14620070 t fired, .
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[[35mlola[0m][.] 37 LTL EXCL 200/372 38/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08 4405861 m, 16520 m/sec, 24230355 t fired, .
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[[35mlola[0m][.] 37 LTL EXCL 205/372 39/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08 4485439 m, 15915 m/sec, 24861245 t fired, .
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[[35mlola[0m][.] 37 LTL EXCL 210/372 40/2000 FamilyReunion-PT-L00010M0001C001P001G001-LTLFireability-08 4581408 m, 19193 m/sec, 25474927 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-PT-L00010M0001C001P001G001"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-PT-L00010M0001C001P001G001, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268100484"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-PT-L00010M0001C001P001G001.tgz
mv FamilyReunion-PT-L00010M0001C001P001G001 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;