About the Execution of LoLA for FamilyReunion-COL-L00100M0010C005P005G002
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.067 | 1891276.00 | 6938124.00 | 1893.30 | ??F?F??????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268000412.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268000412
=====================================================================
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preparation of the directory to be used:
/home/mcc/execution
total 600K
-rw-r--r-- 1 mcc users 7.6K Apr 11 21:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Apr 11 21:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Apr 11 21:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 11 21:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 23:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Apr 11 23:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.2K Apr 11 22:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 11 22:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 140K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-00
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-01
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-02
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-03
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-04
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-05
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-06
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-08
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-09
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-10
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-12
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-13
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717157355218
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717159246494
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] Places: 40706, Transitions: 36871
[[35mlola[0m][I] LAUNCH task # 68 (type SKEL/CNST) for 20 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 68 (type SKEL/CNST) for FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 69 (type SKEL/CNST) for 10 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 69 (type SKEL/CNST) for FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][W] findlow criterion violated for transition 64
[[35mlola[0m][W] findlow criterion violated for transition 63
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-02: CONJ false skeleton: preprocessing[0m
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-00: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][W] findlow criterion violated for transition 53
[[35mlola[0m][W] findlow criterion violated for transition 12
[[35mlola[0m][W] findlow criterion violated for transition 13
[[35mlola[0m][W] findlow criterion violated for transition 50
[[35mlola[0m][W] findlow criterion violated for transition 45
[[35mlola[0m][W] findlow criterion violated for transition 43
[[35mlola[0m][W] findlow criterion violated for transition 39
[[35mlola[0m][W] findlow criterion violated for transition 35
[[35mlola[0m][W] findlow criterion violated for transition 34
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-01: CONJ 0 0 0 0 2 0 0 0
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EG EXCL 48/179 3/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 12289 m, 251 m/sec, 68746 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 73/179 4/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 19282 m, 257 m/sec, 121812 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 78/179 5/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 20426 m, 228 m/sec, 129869 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 83/179 5/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 22113 m, 337 m/sec, 142031 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 88/179 5/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 23986 m, 374 m/sec, 156009 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 98/179 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 26975 m, 299 m/sec, 180542 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 103/179 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 28585 m, 322 m/sec, 193019 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 113/179 7/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 30986 m, 212 m/sec, 213027 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 118/179 7/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 32701 m, 343 m/sec, 228009 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 123/179 7/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 34311 m, 322 m/sec, 242807 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 128/179 8/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 35471 m, 232 m/sec, 251597 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 133/179 8/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 37908 m, 487 m/sec, 268596 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 138/179 9/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 39885 m, 395 m/sec, 283498 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 168/191 10/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 48144 m, 251 m/sec, 350552 t fired, .
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[[35mlola[0m][.] 71 EG EXCL 173/191 10/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-11 49268 m, 224 m/sec, 360552 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 110/191 12/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 59967 m, 857 m/sec, 105421 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 115/191 13/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 63120 m, 630 m/sec, 111013 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 120/191 14/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 66756 m, 727 m/sec, 117691 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 125/191 14/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 69798 m, 608 m/sec, 123245 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 150/191 18/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 85973 m, 578 m/sec, 152838 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 155/191 18/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 89449 m, 695 m/sec, 159145 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 160/191 19/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 92716 m, 653 m/sec, 165103 t fired, .
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[[35mlola[0m][.] 38 LTL EXCL 165/191 20/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-07 96082 m, 673 m/sec, 171285 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 70/191 3/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 50657 m, 820 m/sec, 133950 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 75/191 3/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 55471 m, 962 m/sec, 147092 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 80/191 4/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 59346 m, 775 m/sec, 157733 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 85/191 4/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 63165 m, 763 m/sec, 168273 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 110/191 4/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 82606 m, 926 m/sec, 221424 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 115/191 5/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 86509 m, 780 m/sec, 232133 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 120/191 5/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 91412 m, 980 m/sec, 245579 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 150/191 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 114510 m, 757 m/sec, 308914 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 155/191 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 118178 m, 733 m/sec, 319039 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 160/191 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 121830 m, 730 m/sec, 328952 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 165/191 6/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 125733 m, 780 m/sec, 339669 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 190/191 7/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 146398 m, 886 m/sec, 396283 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 35/191 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 31358 m, 916 m/sec, 81097 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 40/191 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 36060 m, 940 m/sec, 93994 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 45/191 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 41116 m, 1011 m/sec, 107894 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 50/191 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 47093 m, 1195 m/sec, 124194 t fired, .
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[[35mlola[0m][.] 63 LTL EXCL 55/191 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLFireability-14 54494 m, 1480 m/sec, 144428 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00100M0010C005P005G002"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268000412"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00100M0010C005P005G002.tgz
mv FamilyReunion-COL-L00100M0010C005P005G002 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;