About the Execution of LoLA for FamilyReunion-COL-L00100M0010C005P005G002
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.855 | 2141568.00 | 6839063.00 | 3192.10 | F??FT?F??F?????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636268000411.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636268000411
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 600K
-rw-r--r-- 1 mcc users 7.6K Apr 11 21:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Apr 11 21:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Apr 11 21:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 11 21:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 23:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 133K Apr 11 23:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.2K Apr 11 22:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Apr 11 22:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 140K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14
FORMULA_NAME FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15
=== Now, execution of the tool begins
BK_START 1717155897176
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717158038744
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 86 (type SKEL/FNDP) for 0 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 87 (type SKEL/EQUN) for 0 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 88 (type SKEL/SRCH) for 0 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] FINISHED task # 88 (type SKEL/SRCH) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 34 (type SKEL/CNST) for 30 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][W] CANCELED task # 86 (type FNDP) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00 (obsolete)
[[35mlola[0m][W] CANCELED task # 87 (type EQUN) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00 (obsolete)
[[35mlola[0m][I] Places: 40706, Transitions: 36871
[[35mlola[0m][I] FINISHED task # 34 (type SKEL/CNST) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 86 (type SKEL/FNDP) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 4 (type SKEL/CNST) for 0 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type SKEL/CNST) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 14 (type SKEL/CNST) for 10 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 14 (type SKEL/CNST) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 91 (type SKEL/FNDP) for 43 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 92 (type SKEL/EQUN) for 43 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 93 (type SKEL/SRCH) for 43 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 93 (type SKEL/SRCH) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 91 (type FNDP) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 92 (type EQUN) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09 (obsolete)
[[35mlola[0m][I] FINISHED task # 91 (type SKEL/FNDP) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][W] findlow criterion violated for transition 64
[[35mlola[0m][I] FINISHED task # 92 (type SKEL/EQUN) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 87 (type SKEL/EQUN) for FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][W] findlow criterion violated for transition 63
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated for transition 6
[[35mlola[0m][W] findlow criterion violated for transition 58
[[35mlola[0m][W] findlow criterion violated for transition 53
[[35mlola[0m][W] findlow criterion violated for transition 12
[[35mlola[0m][W] findlow criterion violated for transition 13
[[35mlola[0m][W] findlow criterion violated for transition 50
[[35mlola[0m][W] findlow criterion violated for transition 45
[[35mlola[0m][W] findlow criterion violated for transition 43
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][W] findlow criterion violated for transition 39
[[35mlola[0m][W] findlow criterion violated for transition 35
[[35mlola[0m][W] findlow criterion violated for transition 34
[[35mlola[0m][W] findlow criterion violated for transition 26
[[35mlola[0m][W] findlow criterion violated for transition 29
[[35mlola[0m][W] findlow criterion violated for transition 28
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-06: CONJ false skeleton: preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-00: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03: CONJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04: F 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-09: CONJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-10: LTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] LAUNCH task # 95 (type SKEL/SRCH) for 74 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-14
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[[35mlola[0m][.] 96 LTL SRCH 3/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 735818 m, 147163 m/sec, 1832263 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 8/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 1650747 m, 182985 m/sec, 4208400 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 18/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 3434522 m, 178503 m/sec, 8912552 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 23/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 4293852 m, 171866 m/sec, 11171965 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 28/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 5122317 m, 165693 m/sec, 13376298 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 33/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 5982048 m, 171946 m/sec, 15669001 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 38/3318 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 6834051 m, 170400 m/sec, 17940480 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 43/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 7674827 m, 168155 m/sec, 20183621 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 48/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 8488042 m, 162643 m/sec, 22403243 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 53/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 9328906 m, 168172 m/sec, 24637640 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 63/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 10969092 m, 159039 m/sec, 29064446 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 68/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 11805278 m, 167237 m/sec, 31279552 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 73/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 12682582 m, 175460 m/sec, 33640460 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 78/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 13467229 m, 156929 m/sec, 35759864 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 83/3318 2/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 14281156 m, 162785 m/sec, 37964414 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 88/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 15109633 m, 165695 m/sec, 40184558 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 93/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 15903187 m, 158710 m/sec, 42371814 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 98/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 16750658 m, 169494 m/sec, 44604690 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 103/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 17542220 m, 158312 m/sec, 46782194 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 108/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 18384328 m, 168421 m/sec, 49009948 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 113/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 19169735 m, 157081 m/sec, 51159457 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 118/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 20017913 m, 169635 m/sec, 53501196 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 123/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 20916454 m, 179708 m/sec, 55866660 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 128/3318 3/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 21739940 m, 164697 m/sec, 58132461 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 133/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 22581680 m, 168348 m/sec, 60436816 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 138/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 23468471 m, 177358 m/sec, 62784048 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 143/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 24291191 m, 164544 m/sec, 65051640 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 148/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 24708189 m, 83399 m/sec, 66204875 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 153/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 24844073 m, 27176 m/sec, 66580229 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 158/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 24978467 m, 26878 m/sec, 66953117 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 163/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 25114680 m, 27242 m/sec, 67331721 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 178/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 25582964 m, 28484 m/sec, 68508664 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 183/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 25721563 m, 27719 m/sec, 68885386 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 188/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 25857340 m, 27155 m/sec, 69255609 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 193/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 25988039 m, 26139 m/sec, 69613840 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 198/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26120496 m, 26491 m/sec, 69977734 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 203/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26256348 m, 27170 m/sec, 70350517 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 213/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26522144 m, 26026 m/sec, 71081838 t fired, .
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 96 LTL SRCH 218/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26658021 m, 27175 m/sec, 71456794 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 223/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26791834 m, 26762 m/sec, 71825914 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 228/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 26924317 m, 26496 m/sec, 72191865 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 233/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27053802 m, 25897 m/sec, 72550445 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 238/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27186771 m, 26593 m/sec, 72917735 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 243/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27318775 m, 26400 m/sec, 73283857 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 253/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27584370 m, 26470 m/sec, 74019035 t fired, .
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[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 96 LTL SRCH 258/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27722015 m, 27529 m/sec, 74401396 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 263/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 27864206 m, 28438 m/sec, 74794502 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 268/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28020003 m, 31159 m/sec, 75198181 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 273/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28186706 m, 33340 m/sec, 75590644 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 278/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28344756 m, 31610 m/sec, 76007026 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 283/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28489218 m, 28892 m/sec, 76398078 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 288/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28630329 m, 28222 m/sec, 76782170 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 298/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 28902533 m, 27122 m/sec, 77527318 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 303/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 29037963 m, 27086 m/sec, 77899065 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 308/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 29174956 m, 27398 m/sec, 78275719 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 318/3318 4/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 29440406 m, 26114 m/sec, 79007456 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 338/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 29972384 m, 26413 m/sec, 80477164 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 343/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 30104707 m, 26464 m/sec, 80842654 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 348/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 30241448 m, 27348 m/sec, 81221757 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 353/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 30375117 m, 26733 m/sec, 81592014 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 358/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 30510063 m, 26989 m/sec, 81965485 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 378/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31064680 m, 28943 m/sec, 83490102 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 383/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31232291 m, 33522 m/sec, 83884391 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 388/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31391569 m, 31855 m/sec, 84288528 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 393/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31532867 m, 28259 m/sec, 84669360 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 398/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31672953 m, 28017 m/sec, 85050182 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 403/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 31811012 m, 27611 m/sec, 85427538 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 413/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32087997 m, 27220 m/sec, 86186513 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 418/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32223839 m, 27168 m/sec, 86559636 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 423/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32357638 m, 26759 m/sec, 86928529 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 428/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32491774 m, 26827 m/sec, 87298623 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 433/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32628601 m, 27365 m/sec, 87676160 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 438/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 32765131 m, 27306 m/sec, 88052784 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 453/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33167357 m, 26628 m/sec, 89164817 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 458/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33300305 m, 26589 m/sec, 89532084 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 463/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33429116 m, 25762 m/sec, 89889229 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 468/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33562850 m, 26746 m/sec, 90260637 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 473/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33695497 m, 26529 m/sec, 90627132 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 478/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 33828591 m, 26618 m/sec, 90996428 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 493/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34238502 m, 27248 m/sec, 92135265 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 498/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34381441 m, 28587 m/sec, 92529723 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 503/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34548230 m, 33357 m/sec, 92921076 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 508/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34714031 m, 33160 m/sec, 93328651 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 513/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34835946 m, 24383 m/sec, 93656166 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 518/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 34961173 m, 25045 m/sec, 93995199 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 533/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35337425 m, 24886 m/sec, 95023329 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 538/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35465420 m, 25599 m/sec, 95375178 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 543/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35592667 m, 25449 m/sec, 95724422 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 548/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35729081 m, 27282 m/sec, 96100641 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 553/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35846004 m, 23384 m/sec, 96422605 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 558/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 35963775 m, 23554 m/sec, 96747222 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 573/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 36347111 m, 23220 m/sec, 97806234 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 578/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 36476714 m, 25920 m/sec, 98164148 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 583/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 36602615 m, 25180 m/sec, 98513263 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 588/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 36734709 m, 26418 m/sec, 98878741 t fired, .
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[[35mlola[0m][.] 96 LTL SRCH 593/3318 5/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05 36860017 m, 25061 m/sec, 99225659 t fired, .
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[[35mlola[0m][.] 20 LTL EXCL 101/111 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-03 2654 m, 9 m/sec, 2653 t fired, .
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[[35mlola[0m][.] 106 EG EXCL 1/117 0/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-04 --
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[[35mlola[0m][.] 66 LTL EXCL 4/132 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 1337 m, 267 m/sec, 1336 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 39/162 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 2227 m, 4 m/sec, 2226 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 64/162 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 2435 m, 6 m/sec, 2434 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 69/162 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 2606 m, 34 m/sec, 2605 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 74/162 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 3288 m, 136 m/sec, 3465 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 79/162 1/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 3845 m, 111 m/sec, 4365 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 84/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 4359 m, 102 m/sec, 5207 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 89/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 4980 m, 124 m/sec, 6233 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 94/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 5478 m, 99 m/sec, 7073 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 99/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 6186 m, 141 m/sec, 8242 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 104/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 6838 m, 130 m/sec, 9337 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 109/162 2/2000 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 7441 m, 120 m/sec, 10355 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 15/150 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 1814 m, 31 m/sec, 1813 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 20/162 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 1944 m, 26 m/sec, 1943 t fired, .
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[[35mlola[0m][.] 66 LTL EXCL 25/162 1/5 FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11 2079 m, 27 m/sec, 2078 t fired, .
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[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-02: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-05: LTL 0 0 0 0 0 0 1 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-11: CONJ 0 0 1 0 4 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00100M0010C005P005G002-LTLCardinality-13: LTL 0 0 0 0 1 0 0 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00100M0010C005P005G002"
export BK_EXAMINATION="LTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00100M0010C005P005G002, examination is LTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636268000411"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00100M0010C005P005G002.tgz
mv FamilyReunion-COL-L00100M0010C005P005G002 execution
cd execution
if [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "UpperBounds" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] || [ "LTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLCardinality" = "ReachabilityDeadlock" ] || [ "LTLCardinality" = "QuasiLiveness" ] || [ "LTLCardinality" = "StableMarking" ] || [ "LTLCardinality" = "Liveness" ] || [ "LTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;