fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r159-smll-171636267900402
Last Updated
July 7, 2024

About the Execution of LoLA for FamilyReunion-COL-L00050M0005C002P002G001

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
0.000 1919175.00 0.00 0.00 ????F???FT?????? normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267900402.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267900402
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 668K
-rw-r--r-- 1 mcc users 6.8K Apr 11 20:46 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Apr 11 20:46 CTLCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Apr 11 20:34 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Apr 11 20:34 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 21:43 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 144K Apr 11 21:43 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 16K Apr 11 21:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Apr 11 21:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 137K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14
FORMULA_NAME FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15

=== Now, execution of the tool begins

BK_START 1717151262044

FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717153181219

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains High-Level net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading HL formula in XML format (--xmlformula)
[lola][I] reading formula from CTLFireability.xml
[lola][I] NOTDEADLOCKFREE
[lola][I] LAUNCH task # 58 (type SKEL/FNDP) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 59 (type SKEL/EQUN) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 60 (type SKEL/SRCH) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 63 (type SKEL/FNDP) for 28 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 60 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 58 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04 (obsolete)
[lola][W] CANCELED task # 59 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04 (obsolete)
[lola][I] LAUNCH task # 64 (type SKEL/EQUN) for 28 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 65 (type SKEL/SRCH) for 28 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 58 (type SKEL/FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] FINISHED task # 65 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] result : true
[lola][I] markings : 2
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 63 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08 (obsolete)
[lola][W] CANCELED task # 64 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08 (obsolete)
[lola][I] FINISHED task # 63 (type SKEL/FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] Places: 12245, Transitions: 10560
[lola][W] findlow criterion violated for transition 59
[lola][I] FINISHED task # 59 (type SKEL/EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] result : true
[lola][I] FINISHED task # 64 (type SKEL/EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] result : true
[lola][W] findlow criterion violated for transition 64
[lola][W] findlow criterion violated for transition 63
[lola][W] findlow criterion violated for transition 4
[lola][W] findlow criterion violated for transition 5
[lola][W] findlow criterion violated for transition 6
[lola][W] findlow criterion violated for transition 58
[lola][W] findlow criterion violated for transition 53
[lola][W] findlow criterion violated for transition 12
[lola][W] findlow criterion violated for transition 13
[lola][W] findlow criterion violated for transition 50
[lola][W] findlow criterion violated for transition 45
[lola][W] findlow criterion violated for transition 43
[lola][W] findlow criterion violated for transition 39
[lola][W] findlow criterion violated for transition 35
[lola][W] findlow criterion violated for transition 34
[lola][W] findlow criterion violated for transition 26
[lola][W] findlow criterion violated for transition 29
[lola][W] findlow criterion violated for transition 28
[lola][W] findlow criterion violated for 19 clusters
[lola][I] Time for checking findlow: 5
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG 0 0 0 0 3 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 1 0 0 0 0 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 1
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 66 (type SKEL/SRCH) for 41 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 66 (type SKEL/SRCH) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Rule S: 0 transitions removed,51 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG 0 0 0 0 3 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG 0 0 0 0 3 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ 0 0 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
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[lola][I] LAUNCH task # 70 (type EXCL) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
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[lola][I] LAUNCH task # 68 (type FNDP) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
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[lola][I] LAUNCH task # 69 (type EQUN) for 12 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
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[lola][I] FINISHED task # 70 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
[lola][I] result : true
[lola][I] markings : 19
[lola][I] fired transitions : 18
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[lola][I] LAUNCH task # 73 (type EQUN) for 28 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 72 (type FNDP) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
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[lola][W] CANCELED task # 73 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08 (obsolete)
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[lola][I] FINISHED task # 69 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
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[lola][I] LAUNCH task # 36 (type EXCL) for 31 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09
[lola][I] time limit : 222 sec
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[lola][I] FINISHED task # 36 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09
[lola][I] result : true
[lola][I] markings : 1543
[lola][I] fired transitions : 1543
[lola][I] time used : 1
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[lola][I] LAUNCH task # 48 (type EXCL) for 47 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13
[lola][I] time limit : 254 sec
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 0 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 2/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 3618 m, 723 m/sec, 11777 t fired, .
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[lola][I] FINISHED task # 73 (type EQUN) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 7/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 10384 m, 1353 m/sec, 50032 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 12/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 25093 m, 2941 m/sec, 143608 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 17/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 35418 m, 2065 m/sec, 216593 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 22/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 45118 m, 1940 m/sec, 283832 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 27/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 53426 m, 1661 m/sec, 342840 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 32/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 60209 m, 1356 m/sec, 392696 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 37/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 74822 m, 2922 m/sec, 492451 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 42/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 93447 m, 3725 m/sec, 636729 t fired, .
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[lola][.] 48 CTL EXCL 47/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 112414 m, 3793 m/sec, 787891 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 52/254 1/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 132847 m, 4086 m/sec, 938640 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 57/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 152615 m, 3953 m/sec, 1090223 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 62/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 171622 m, 3801 m/sec, 1241989 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 67/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 192193 m, 4114 m/sec, 1393113 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 72/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 211915 m, 3944 m/sec, 1544719 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 77/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 230446 m, 3706 m/sec, 1692787 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 82/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 249471 m, 3805 m/sec, 1844259 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 87/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 267360 m, 3577 m/sec, 1996284 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
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[lola][.] 48 CTL EXCL 92/254 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 284354 m, 3398 m/sec, 2148841 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 97/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 301765 m, 3482 m/sec, 2301286 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 102/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 320210 m, 3689 m/sec, 2453178 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 107/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 336937 m, 3345 m/sec, 2605866 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 112/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 353914 m, 3395 m/sec, 2758651 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 117/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 374815 m, 4180 m/sec, 2909644 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 122/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 393951 m, 3827 m/sec, 3061418 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 48 CTL EXCL 127/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 412929 m, 3795 m/sec, 3213017 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 132/254 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 431915 m, 3797 m/sec, 3364434 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 137/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 449182 m, 3453 m/sec, 3516303 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 142/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 466146 m, 3392 m/sec, 3668422 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 147/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 484252 m, 3621 m/sec, 3820208 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 152/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 502053 m, 3560 m/sec, 3970232 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 157/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 518737 m, 3336 m/sec, 4121061 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 162/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 536056 m, 3463 m/sec, 4271493 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 167/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 556739 m, 4136 m/sec, 4420383 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 172/254 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 575389 m, 3730 m/sec, 4569586 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 177/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 593961 m, 3714 m/sec, 4719177 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 182/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 612455 m, 3698 m/sec, 4869116 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 187/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 629216 m, 3352 m/sec, 5020000 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 192/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 646348 m, 3426 m/sec, 5172623 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 197/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 664743 m, 3679 m/sec, 5324708 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 202/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 682389 m, 3529 m/sec, 5476719 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 207/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 699530 m, 3428 m/sec, 5629363 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 212/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 717221 m, 3538 m/sec, 5781731 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 217/254 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 735435 m, 3642 m/sec, 5933631 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 48 CTL EXCL 222/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 752307 m, 3374 m/sec, 6086343 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 48 CTL EXCL 227/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 768909 m, 3320 m/sec, 6239061 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 232/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 786055 m, 3429 m/sec, 6391494 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 237/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 801705 m, 3130 m/sec, 6544874 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 242/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 817271 m, 3113 m/sec, 6697978 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 247/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 832945 m, 3134 m/sec, 6850879 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 252/254 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 849563 m, 3323 m/sec, 7003750 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 4/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 24077 m, -165097 m/sec, 136650 t fired, .
[lola][.] 54 CTL EXCL 5/253 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 20949 m, 4189 m/sec, 70463 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 9/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 45587 m, 4302 m/sec, 286711 t fired, .
[lola][.] 54 CTL EXCL 10/235 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 39189 m, 3648 m/sec, 139980 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 14/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 67121 m, 4306 m/sec, 437228 t fired, .
[lola][.] 54 CTL EXCL 15/235 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 58792 m, 3920 m/sec, 213182 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 19/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 87808 m, 4137 m/sec, 588693 t fired, .
[lola][.] 54 CTL EXCL 20/235 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 74517 m, 3145 m/sec, 291367 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 24/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 106747 m, 3787 m/sec, 740710 t fired, .
[lola][.] 54 CTL EXCL 25/235 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 91082 m, 3313 m/sec, 368930 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 29/3300 1/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 126449 m, 3940 m/sec, 891453 t fired, .
[lola][.] 54 CTL EXCL 30/235 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 107801 m, 3343 m/sec, 442196 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 34/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 146918 m, 4093 m/sec, 1041886 t fired, .
[lola][.] 54 CTL EXCL 35/235 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 122762 m, 2992 m/sec, 516687 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 39/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 165815 m, 3779 m/sec, 1193532 t fired, .
[lola][.] 54 CTL EXCL 40/235 7/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 137379 m, 2923 m/sec, 586144 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 44/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 185563 m, 3949 m/sec, 1344546 t fired, .
[lola][.] 54 CTL EXCL 45/235 8/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 155098 m, 3543 m/sec, 663293 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 49/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 206103 m, 4108 m/sec, 1495755 t fired, .
[lola][.] 54 CTL EXCL 50/235 9/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 172042 m, 3388 m/sec, 741137 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 54/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 225085 m, 3796 m/sec, 1647879 t fired, .
[lola][.] 54 CTL EXCL 55/235 9/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 188888 m, 3369 m/sec, 818819 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 59/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 243822 m, 3747 m/sec, 1798169 t fired, .
[lola][.] 54 CTL EXCL 60/235 10/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 203085 m, 2839 m/sec, 893095 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 64/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 262163 m, 3668 m/sec, 1950027 t fired, .
[lola][.] 54 CTL EXCL 65/235 11/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 218953 m, 3173 m/sec, 966176 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 69/3300 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 278948 m, 3357 m/sec, 2102553 t fired, .
[lola][.] 54 CTL EXCL 70/235 11/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 234926 m, 3194 m/sec, 1042952 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 74/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 295730 m, 3356 m/sec, 2255163 t fired, .
[lola][.] 54 CTL EXCL 75/235 12/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 252115 m, 3437 m/sec, 1120207 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 79/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 314603 m, 3774 m/sec, 2406698 t fired, .
[lola][.] 54 CTL EXCL 80/235 13/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 270237 m, 3624 m/sec, 1196688 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 84/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 331885 m, 3456 m/sec, 2558976 t fired, .
[lola][.] 54 CTL EXCL 85/235 14/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 286658 m, 3284 m/sec, 1274406 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 48 CTL EXCL 89/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 348799 m, 3382 m/sec, 2711442 t fired, .
[lola][.] 54 CTL EXCL 90/235 14/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 302490 m, 3166 m/sec, 1352499 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 94/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 367677 m, 3775 m/sec, 2856821 t fired, .
[lola][.] 54 CTL EXCL 95/235 15/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 315833 m, 2668 m/sec, 1429320 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 99/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 386667 m, 3798 m/sec, 3000722 t fired, .
[lola][.] 54 CTL EXCL 100/235 15/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 330412 m, 2915 m/sec, 1504725 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 104/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 405426 m, 3751 m/sec, 3150211 t fired, .
[lola][.] 54 CTL EXCL 105/235 16/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 343193 m, 2556 m/sec, 1579080 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 109/3300 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 424434 m, 3801 m/sec, 3301550 t fired, .
[lola][.] 54 CTL EXCL 110/235 17/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 357419 m, 2845 m/sec, 1654278 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 114/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 442473 m, 3607 m/sec, 3453741 t fired, .
[lola][.] 54 CTL EXCL 115/235 17/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 371372 m, 2790 m/sec, 1724433 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 119/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 459375 m, 3380 m/sec, 3606589 t fired, .
[lola][.] 54 CTL EXCL 120/235 18/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 385821 m, 2889 m/sec, 1803357 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 124/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 476496 m, 3424 m/sec, 3759069 t fired, .
[lola][.] 54 CTL EXCL 125/235 19/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 397443 m, 2324 m/sec, 1872701 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
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[lola][.] 48 CTL EXCL 129/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 494778 m, 3656 m/sec, 3907945 t fired, .
[lola][.] 54 CTL EXCL 130/235 19/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 410916 m, 2694 m/sec, 1948489 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 48 CTL EXCL 134/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 510917 m, 3227 m/sec, 4053502 t fired, .
[lola][.] 54 CTL EXCL 135/235 20/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 425074 m, 2831 m/sec, 2024795 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 139/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 527227 m, 3262 m/sec, 4198975 t fired, .
[lola][.] 54 CTL EXCL 140/235 21/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 441556 m, 3296 m/sec, 2100489 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
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[lola][.] 48 CTL EXCL 144/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 545925 m, 3739 m/sec, 4341909 t fired, .
[lola][.] 54 CTL EXCL 145/235 21/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 457092 m, 3107 m/sec, 2177322 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
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[lola][.] 48 CTL EXCL 149/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 564738 m, 3762 m/sec, 4484800 t fired, .
[lola][.] 54 CTL EXCL 150/235 22/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 473517 m, 3285 m/sec, 2253518 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 154/3300 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 582733 m, 3599 m/sec, 4627781 t fired, .
[lola][.] 54 CTL EXCL 155/235 23/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 488866 m, 3069 m/sec, 2330032 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
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[lola][.] 48 CTL EXCL 159/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 601490 m, 3751 m/sec, 4777063 t fired, .
[lola][.] 54 CTL EXCL 160/235 24/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 502788 m, 2784 m/sec, 2405651 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 48 CTL EXCL 164/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 619567 m, 3615 m/sec, 4929445 t fired, .
[lola][.] 54 CTL EXCL 165/235 24/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 516063 m, 2655 m/sec, 2485916 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 169/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 636465 m, 3379 m/sec, 5082358 t fired, .
[lola][.] 54 CTL EXCL 170/235 25/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 530420 m, 2871 m/sec, 2565374 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 48 CTL EXCL 174/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 653578 m, 3422 m/sec, 5234809 t fired, .
[lola][.] 54 CTL EXCL 175/235 26/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 544790 m, 2874 m/sec, 2644617 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
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[lola][.] 48 CTL EXCL 179/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 672247 m, 3733 m/sec, 5386794 t fired, .
[lola][.] 54 CTL EXCL 180/235 27/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 560047 m, 3051 m/sec, 2723143 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 184/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 689143 m, 3379 m/sec, 5539741 t fired, .
[lola][.] 54 CTL EXCL 185/235 27/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 574608 m, 2912 m/sec, 2803115 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 189/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 706320 m, 3435 m/sec, 5692741 t fired, .
[lola][.] 54 CTL EXCL 190/235 28/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 588910 m, 2860 m/sec, 2883215 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 48 CTL EXCL 194/3300 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13 724842 m, 3704 m/sec, 5844666 t fired, .
[lola][.] 54 CTL EXCL 195/235 29/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 602909 m, 2799 m/sec, 2962734 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 54 CTL EXCL 200/235 29/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 615568 m, 2531 m/sec, 3043096 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 205/253 30/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 627455 m, 2377 m/sec, 3123973 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 210/253 30/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 640116 m, 2532 m/sec, 3204162 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 215/253 31/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 655921 m, 3161 m/sec, 3281834 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 220/253 32/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 671411 m, 3098 m/sec, 3359618 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 225/253 32/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 687467 m, 3211 m/sec, 3436883 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 230/253 33/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 704892 m, 3485 m/sec, 3513268 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 235/253 33/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 719785 m, 2978 m/sec, 3591247 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 240/253 34/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 733360 m, 2715 m/sec, 3670189 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 245/253 34/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 748588 m, 3045 m/sec, 3748110 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 54 CTL EXCL 250/253 35/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 765118 m, 3306 m/sec, 3825742 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
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[lola][.] 51 CTL EXCL 5/253 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 25540 m, 5108 m/sec, 76367 t fired, .
[lola][.] 54 CTL EXCL 4/3045 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 21063 m, -148811 m/sec, 71138 t fired, .
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[lola][.] 51 CTL EXCL 10/253 3/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 48029 m, 4497 m/sec, 157808 t fired, .
[lola][.] 54 CTL EXCL 9/234 3/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 40800 m, 3947 m/sec, 145423 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 51 CTL EXCL 15/253 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 68395 m, 4073 m/sec, 240016 t fired, .
[lola][.] 54 CTL EXCL 14/234 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 60235 m, 3887 m/sec, 219793 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 51 CTL EXCL 20/253 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 84487 m, 3218 m/sec, 322912 t fired, .
[lola][.] 54 CTL EXCL 19/234 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 75717 m, 3096 m/sec, 296701 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 51 CTL EXCL 25/253 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 105770 m, 4256 m/sec, 405087 t fired, .
[lola][.] 54 CTL EXCL 24/234 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 91604 m, 3177 m/sec, 371409 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 1 0 1 0 0 0
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[lola][.] 51 CTL EXCL 30/253 6/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 123491 m, 3544 m/sec, 492816 t fired, .
[lola][.] 54 CTL EXCL 29/234 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15 108828 m, 3444 m/sec, 447161 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 1 0 1 0 0 0
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[lola][.] 51 CTL EXCL 35/253 7/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 142813 m, 3864 m/sec, 579831 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 40/253 8/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 167186 m, 4874 m/sec, 664742 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 45/253 9/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 184226 m, 3408 m/sec, 752142 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 50/253 10/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 201690 m, 3492 m/sec, 839336 t fired, .
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[lola][.] 51 CTL EXCL 55/253 11/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 218993 m, 3460 m/sec, 926449 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 60/253 12/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 239488 m, 4099 m/sec, 1012749 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 65/253 13/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 261227 m, 4347 m/sec, 1098364 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 70/253 14/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 280433 m, 3841 m/sec, 1184186 t fired, .
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[lola][.] 51 CTL EXCL 75/253 15/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 303225 m, 4558 m/sec, 1269705 t fired, .
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[lola][.] 51 CTL EXCL 80/253 16/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 321780 m, 3711 m/sec, 1356945 t fired, .
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[lola][.] 51 CTL EXCL 85/253 17/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 339126 m, 3469 m/sec, 1444622 t fired, .
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[lola][.] 51 CTL EXCL 90/253 17/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 353416 m, 2858 m/sec, 1532765 t fired, .
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[lola][.] 51 CTL EXCL 100/253 19/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 386249 m, 3508 m/sec, 1707193 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 105/253 19/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 403060 m, 3362 m/sec, 1794091 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 110/253 20/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 420116 m, 3411 m/sec, 1881101 t fired, .
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[lola][.] 51 CTL EXCL 115/253 21/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 437454 m, 3467 m/sec, 1967762 t fired, .
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[lola][.] 51 CTL EXCL 120/253 22/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 457372 m, 3983 m/sec, 2053548 t fired, .
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[lola][.] 51 CTL EXCL 125/253 22/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 476010 m, 3727 m/sec, 2139899 t fired, .
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[lola][.] 51 CTL EXCL 130/253 23/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 496334 m, 4064 m/sec, 2225087 t fired, .
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[lola][.] 51 CTL EXCL 145/253 26/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 553600 m, 3976 m/sec, 2483053 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 150/253 27/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 572366 m, 3753 m/sec, 2569204 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 155/253 28/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 593687 m, 4264 m/sec, 2654190 t fired, .
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[lola][.] 51 CTL EXCL 160/253 28/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 610488 m, 3360 m/sec, 2740593 t fired, .
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[lola][.] 51 CTL EXCL 165/253 29/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 628987 m, 3699 m/sec, 2826159 t fired, .
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[lola][.] 51 CTL EXCL 170/253 30/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 650327 m, 4268 m/sec, 2910990 t fired, .
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[lola][.] 51 CTL EXCL 190/253 34/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 721627 m, 2884 m/sec, 3255696 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 196/253 35/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 737821 m, 3238 m/sec, 3342225 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 201/253 35/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 754776 m, 3391 m/sec, 3428821 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 206/253 36/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 771810 m, 3406 m/sec, 3515409 t fired, .
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[lola][.] 51 CTL EXCL 211/253 37/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 788962 m, 3430 m/sec, 3601890 t fired, .
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[lola][.] 51 CTL EXCL 216/253 38/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 809186 m, 4044 m/sec, 3687276 t fired, .
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[lola][.]
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[lola][.] 51 CTL EXCL 236/253 41/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 885042 m, 3441 m/sec, 4030944 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 51 CTL EXCL 241/253 42/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 906261 m, 4243 m/sec, 4116232 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 246/253 43/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 923539 m, 3455 m/sec, 4202462 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 51 CTL EXCL 251/253 44/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14 946466 m, 4585 m/sec, 4286948 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][I] LAUNCH task # 45 (type EXCL) for 44 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12
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[lola][I] LAUNCH task # 51 (type EXCL) for 50 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[lola][I] LAUNCH task # 42 (type EXCL) for 41 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 42 (type EXCL) for FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11
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[lola][I] LAUNCH task # 39 (type EXCL) for 38 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10
[lola][I] time limit : 307 sec
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[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 39 CTL EXCL 5/307 2/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 30155 m, 6031 m/sec, 85444 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[lola][.] 39 CTL EXCL 10/307 4/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 55620 m, 5093 m/sec, 174023 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 1 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 39 CTL EXCL 15/307 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 80570 m, 4990 m/sec, 262423 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[lola][.] 39 CTL EXCL 20/307 7/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 105477 m, 4981 m/sec, 350780 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 1 0
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 1 0
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[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 39 CTL EXCL 25/307 8/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 129731 m, 4850 m/sec, 439063 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06: CONJ 0 2 0 0 2 0 0 0
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[lola][.] 39 CTL EXCL 30/307 10/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 154420 m, 4937 m/sec, 527328 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 35/307 11/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 177349 m, 4585 m/sec, 615926 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 40/307 12/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 198556 m, 4241 m/sec, 704546 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 45/307 14/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 219924 m, 4273 m/sec, 792949 t fired, .
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[lola][.] 39 CTL EXCL 50/307 15/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 243309 m, 4677 m/sec, 880301 t fired, .
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[lola][.] 39 CTL EXCL 55/307 16/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 267248 m, 4787 m/sec, 968176 t fired, .
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[lola][.] 39 CTL EXCL 60/307 17/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 287569 m, 4064 m/sec, 1051815 t fired, .
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[lola][.] 39 CTL EXCL 65/307 19/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 308540 m, 4194 m/sec, 1136987 t fired, .
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[lola][.] 39 CTL EXCL 70/307 20/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 330196 m, 4331 m/sec, 1224840 t fired, .
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[lola][.] 39 CTL EXCL 85/307 24/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 396222 m, 4554 m/sec, 1489621 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 90/307 25/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 420355 m, 4826 m/sec, 1577573 t fired, .
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[lola][.] 39 CTL EXCL 95/307 26/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 442415 m, 4412 m/sec, 1666130 t fired, .
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[lola][.] 39 CTL EXCL 100/307 28/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 464488 m, 4414 m/sec, 1754260 t fired, .
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[lola][.] 39 CTL EXCL 105/307 29/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 485471 m, 4196 m/sec, 1842433 t fired, .
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[lola][.] 39 CTL EXCL 130/307 35/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 597858 m, 4306 m/sec, 2283787 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 135/307 37/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 618827 m, 4193 m/sec, 2370980 t fired, .
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[lola][.] 39 CTL EXCL 140/307 38/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 639909 m, 4216 m/sec, 2458651 t fired, .
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[lola][.] 39 CTL EXCL 145/307 39/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 661637 m, 4345 m/sec, 2546434 t fired, .
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[lola][.] 39 CTL EXCL 175/307 46/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 777295 m, 3690 m/sec, 3073922 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 180/307 47/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 798660 m, 4273 m/sec, 3161250 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 185/307 48/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 819076 m, 4083 m/sec, 3248549 t fired, .
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[lola][.] 39 CTL EXCL 190/307 49/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 837729 m, 3730 m/sec, 3336287 t fired, .
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[lola][.] 39 CTL EXCL 195/307 50/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 857034 m, 3861 m/sec, 3423723 t fired, .
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[lola][.] 39 CTL EXCL 220/307 56/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 960973 m, 4413 m/sec, 3861324 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 225/307 58/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 982719 m, 4349 m/sec, 3948415 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 39 CTL EXCL 230/307 59/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 1003557 m, 4167 m/sec, 4035675 t fired, .
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[lola][.] 39 CTL EXCL 235/307 60/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 1025509 m, 4390 m/sec, 4122861 t fired, .
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[lola][.] 39 CTL EXCL 240/307 61/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 1047312 m, 4360 m/sec, 4210004 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 26 CTL EXCL 5/306 7/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 60074 m, 12014 m/sec, 60972 t fired, .
[lola][.] 39 CTL EXCL 5/2454 2/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 24418 m, -255715 m/sec, 67628 t fired, .
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[lola][.] 26 CTL EXCL 10/306 13/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 134938 m, 14972 m/sec, 136693 t fired, .
[lola][.] 39 CTL EXCL 10/272 4/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 49480 m, 5012 m/sec, 151255 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 26 CTL EXCL 15/306 20/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 210145 m, 15041 m/sec, 212835 t fired, .
[lola][.] 39 CTL EXCL 15/272 5/5 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-10 73091 m, 4722 m/sec, 235112 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 26 CTL EXCL 20/306 27/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 286366 m, 15244 m/sec, 289813 t fired, .
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[lola][.] 26 CTL EXCL 25/306 35/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 363104 m, 15347 m/sec, 367614 t fired, .
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[lola][.] 26 CTL EXCL 30/306 42/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 439368 m, 15252 m/sec, 445557 t fired, .
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[lola][.] 26 CTL EXCL 45/306 48/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 523261 m, 2545 m/sec, 676745 t fired, .
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[lola][.] 26 CTL EXCL 60/306 50/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 560751 m, 2333 m/sec, 916269 t fired, .
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[lola][.] 26 CTL EXCL 90/306 53/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 631155 m, 2254 m/sec, 1410818 t fired, .
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[lola][.] 26 CTL EXCL 95/306 53/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 643384 m, 2445 m/sec, 1492395 t fired, .
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[lola][.] 26 CTL EXCL 105/306 55/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 671954 m, 2769 m/sec, 1658036 t fired, .
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[lola][.] 26 CTL EXCL 135/306 58/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 740749 m, 2143 m/sec, 2146160 t fired, .
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[lola][.] 26 CTL EXCL 140/306 59/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 753662 m, 2582 m/sec, 2227373 t fired, .
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[lola][.] 26 CTL EXCL 180/306 62/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 840133 m, 1810 m/sec, 2881307 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 26 CTL EXCL 185/306 63/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 851724 m, 2318 m/sec, 2963825 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
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[lola][.] 26 CTL EXCL 190/306 63/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 864082 m, 2471 m/sec, 3047099 t fired, .
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[lola][.] 26 CTL EXCL 195/306 64/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 874295 m, 2042 m/sec, 3129546 t fired, .
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[lola][.] 26 CTL EXCL 225/306 67/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-07 940865 m, 2183 m/sec, 3626494 t fired, .
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[lola][.] 23 CTL EXCL 5/306 5/2000 FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-06 72603 m, 14520 m/sec, 73227 t fired, .
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[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-04: AG false state space
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-08: AG false findpath
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-09: DISJ true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-11: CTL true CTL model checker
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-12: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] FamilyReunion-COL-L00050M0005C002P002G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00050M0005C002P002G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00050M0005C002P002G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267900402"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00050M0005C002P002G001.tgz
mv FamilyReunion-COL-L00050M0005C002P002G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;