About the Execution of LoLA for FamilyReunion-COL-L00020M0002C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.752 | 2567780.00 | 4391885.00 | 9923.70 | ????TT?????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267900394.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267900394
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 660K
-rw-r--r-- 1 mcc users 7.6K Apr 11 20:25 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Apr 11 20:25 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Apr 11 20:18 CTLFireability.txt
-rw-r--r-- 1 mcc users 43K Apr 11 20:18 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.2K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 11 20:42 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 134K Apr 11 20:42 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 17K Apr 11 20:36 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 114K Apr 11 20:36 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 135K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-00
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-01
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-06
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-07
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-08
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-09
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-10
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-12
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-13
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-14
FORMULA_NAME FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-15
=== Now, execution of the tool begins
BK_START 1717147402926
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717149970706
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 53 (type SKEL/FNDP) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 54 (type SKEL/EQUN) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 55 (type SKEL/SRCH) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type SKEL/FNDP) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type SKEL/FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 55 (type SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 58 (type SKEL/EQUN) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 59 (type SKEL/SRCH) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 59 (type SKEL/SRCH) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 2
[[35mlola[0m][I] fired transitions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 57 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 58 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] FINISHED task # 57 (type SKEL/FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] Places: 3292, Transitions: 2753
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][I] FINISHED task # 58 (type SKEL/EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 54 (type SKEL/EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][W] findlow criterion violated for transition 64
[[35mlola[0m][W] findlow criterion violated for transition 63
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][W] findlow criterion violated for transition 6
[[35mlola[0m][W] findlow criterion violated for transition 58
[[35mlola[0m][W] findlow criterion violated for transition 53
[[35mlola[0m][W] findlow criterion violated for transition 12
[[35mlola[0m][I] Rule S: 0 transitions removed,21 places removed
[[35mlola[0m][W] findlow criterion violated for transition 13
[[35mlola[0m][W] findlow criterion violated for transition 50
[[35mlola[0m][W] findlow criterion violated for transition 45
[[35mlola[0m][W] findlow criterion violated for transition 43
[[35mlola[0m][W] findlow criterion violated for transition 39
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 60 (type FNDP) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 61 (type EQUN) for 19 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 7
[[35mlola[0m][I] fired transitions : 6
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 60 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 61 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05 (obsolete)
[[35mlola[0m][I] FINISHED task # 60 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] findlow criterion violated for transition 35
[[35mlola[0m][W] findlow criterion violated for transition 34
[[35mlola[0m][I] FINISHED task # 61 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 63 (type FNDP) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 16 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 63 (type FNDP) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 64 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][W] CANCELED task # 65 (type EXCL) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04 (obsolete)
[[35mlola[0m][I] LAUNCH task # 38 (type EXCL) for 37 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 10 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][W] findlow criterion violated for transition 26
[[35mlola[0m][W] findlow criterion violated for transition 29
[[35mlola[0m][W] findlow criterion violated for transition 28
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-01: CONJ 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02: F 0 1 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-06: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11: CTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-15: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 3/224 1/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11 54615 m, 10923 m/sec, 187018 t fired, .
[[35mlola[0m][.] 70 EF STEQ 3/3597 0/5 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][W] findlow criterion violated for 19 clusters
[[35mlola[0m][I] Time for checking findlow: 7
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 38 CTL EXCL 8/239 2/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-11 180457 m, 25168 m/sec, 695288 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-04: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-05: EF true state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 14 CTL EXCL 5/316 3/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03 110564 m, 22112 m/sec, 289268 t fired, .
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[[35mlola[0m][.] 14 CTL EXCL 10/316 5/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03 214084 m, 20704 m/sec, 603023 t fired, .
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[[35mlola[0m][.] 14 CTL EXCL 20/316 9/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03 427136 m, 20670 m/sec, 1226704 t fired, .
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[[35mlola[0m][.] 14 CTL EXCL 25/316 11/2000 FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03 527133 m, 19999 m/sec, 1538899 t fired, .
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[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-10: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-01: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-02: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00020M0002C001P001G001-CTLFireability-2024-07: CTL 0 0 0 0 1 0 1 0
========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00020M0002C001P001G001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00020M0002C001P001G001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267900394"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00020M0002C001P001G001.tgz
mv FamilyReunion-COL-L00020M0002C001P001G001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;