About the Execution of LoLA for FamilyReunion-COL-L00010M0001C001P001G001
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.111 | 1351206.00 | 2235506.00 | 4281.90 | TTT?F????T?TFF?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267900385.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267900385
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 636K
-rw-r--r-- 1 mcc users 7.4K Apr 11 20:19 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K Apr 11 20:19 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Apr 11 20:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Apr 11 20:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 7.0K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 20:28 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 171K Apr 11 20:28 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.2K Apr 11 20:24 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 57K Apr 11 20:24 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K Apr 22 14:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 18 16:42 equiv_pt
-rw-r--r-- 1 mcc users 24 May 18 16:42 instance
-rw-r--r-- 1 mcc users 5 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 134K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-05
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-06
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-07
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-14
FORMULA_NAME FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717142565349
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717143916555
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains High-Level net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading HL formula in XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLCardinality.xml[0m
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] NOTDEADLOCKFREE
[[35mlola[0m][I] LAUNCH task # 70 (type SKEL/FNDP) for 6 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 71 (type SKEL/EQUN) for 6 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 72 (type SKEL/SRCH) for 6 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type SKEL/EQUN) for 28 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 72 (type SKEL/SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 12
[[35mlola[0m][I] fired transitions : 11
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 70 (type FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][W] CANCELED task # 71 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type SKEL/SRCH) for 28 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 70 (type SKEL/FNDP) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 2045
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 74 (type SKEL/SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 13
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08 (obsolete)
[[35mlola[0m][W] findlow criterion violated for transition 59
[[35mlola[0m][I] Places: 1486, Transitions: 1234
[[35mlola[0m][I] FINISHED task # 71 (type SKEL/EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 76 (type SKEL/EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][W] findlow criterion violated for transition 64
[[35mlola[0m][W] findlow criterion violated for transition 63
[[35mlola[0m][W] findlow criterion violated for transition 4
[[35mlola[0m][W] findlow criterion violated for transition 5
[[35mlola[0m][W] findlow criterion violated for transition 6
[[35mlola[0m][W] findlow criterion violated for transition 58
[[35mlola[0m][W] findlow criterion violated for transition 53
[[35mlola[0m][W] findlow criterion violated for transition 12
[[35mlola[0m][W] findlow criterion violated for transition 13
[[35mlola[0m][W] findlow criterion violated for transition 50
[[35mlola[0m][W] findlow criterion violated for transition 45
[[35mlola[0m][W] findlow criterion violated for transition 43
[[35mlola[0m][W] findlow criterion violated for transition 39
[[35mlola[0m][W] findlow criterion violated for transition 35
[[35mlola[0m][W] findlow criterion violated for transition 34
[[35mlola[0m][W] findlow criterion violated for transition 26
[[35mlola[0m][W] findlow criterion violated for transition 29
[[35mlola[0m][W] findlow criterion violated for transition 28
[[35mlola[0m][W] findlow criterion violated for 19 clusters
[[35mlola[0m][I] Time for checking findlow: 4
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02: AG true skeleton: state space[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03: CTL 1 0 0 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08: DISJ 1 0 0 0 4 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10: AGEF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12: EFEG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15: DISJ 1 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 78 (type SKEL/SRCH) for 28 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 79 (type SKEL/SRCH) for 61 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 77 (type SKEL/SRCH) for 9 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 78 (type SKEL/SRCH) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 198
[[35mlola[0m][I] fired transitions : 197
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 13 (type CNST) for 12 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 50 (type CNST) for 49 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 13 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 0 transitions removed,11 places removed
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 53 (type CNST) for 52 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 56 (type CNST) for 55 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 50 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 56 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 53 (type CNST) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 80 (type EXCL) for 46 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 83 (type EQUN) for 46 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-00: CTL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-01: CTL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-02: AG true skeleton: state space[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-04: CTL false preprocessing[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-09: CTL true preprocessing[0m
[[35mlola[0m][.] [1m[32mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-11: CTL true preprocessing[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-12: EFEG false preprocessing[0m
[[35mlola[0m][.] [1m[31mFamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-13: CTL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03: CTL 0 0 1 0 0 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-05: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08: DISJ 0 0 0 0 5 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10: AGEF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15: DISJ 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 77 CTL SRCH 2/3590 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 297628 m, 59525 m/sec, 1566878 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 2/3590 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 264974 m, 52994 m/sec, 1396463 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 0/276 1/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 --
[[35mlola[0m][.] 83 EF STEQ 0/1795 0/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 3
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[[35mlola[0m][I] FINISHED task # 83 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 88 (type EQUN) for 28 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
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[[35mlola[0m][I] FINISHED task # 88 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 46 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
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[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10
[[35mlola[0m][I] result : unknown
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[[35mlola[0m][.] 77 CTL SRCH 7/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 850388 m, 110552 m/sec, 5023633 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 7/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 647821 m, 76569 m/sec, 3725815 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 5/276 2/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 229642 m, 45928 m/sec, 1079740 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 12/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 1447658 m, 119454 m/sec, 8781096 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 12/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 1067369 m, 83909 m/sec, 6388493 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 10/276 4/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 440745 m, 42220 m/sec, 2197192 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 17/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 2006872 m, 111842 m/sec, 12453406 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 17/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 1472992 m, 81124 m/sec, 8942426 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 15/276 5/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 642777 m, 40406 m/sec, 3258675 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 22/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 2649740 m, 128573 m/sec, 16368119 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 22/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 1857825 m, 76966 m/sec, 11523932 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 20/276 6/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 847502 m, 40945 m/sec, 4348182 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 27/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 3218215 m, 113695 m/sec, 20049895 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 27/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 2319458 m, 92326 m/sec, 14385654 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 25/276 8/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 1052099 m, 40919 m/sec, 5470703 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 32/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 3792729 m, 114902 m/sec, 23844493 t fired, .
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[[35mlola[0m][.] 80 AGEF EXCL 30/276 9/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 1251916 m, 39963 m/sec, 6544662 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 37/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 4294095 m, 100273 m/sec, 27487442 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 37/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 3177593 m, 77623 m/sec, 19788594 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 35/276 11/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 1459227 m, 41462 m/sec, 7631362 t fired, .
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[[35mlola[0m][.] 79 CTL SRCH 42/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 3597543 m, 83990 m/sec, 22447709 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 40/276 12/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 1654445 m, 39043 m/sec, 8688280 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 47/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 5258050 m, 102262 m/sec, 34645526 t fired, .
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[[35mlola[0m][.] 80 AGEF EXCL 45/276 13/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 1865719 m, 42254 m/sec, 9782341 t fired, .
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[[35mlola[0m][.] 79 CTL SRCH 67/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 5300710 m, 72449 m/sec, 34959520 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 65/276 18/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 2627274 m, 37240 m/sec, 14130736 t fired, .
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[[35mlola[0m][.] 77 CTL SRCH 72/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-03 7731023 m, 99771 m/sec, 52508571 t fired, .
[[35mlola[0m][.] 79 CTL SRCH 72/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 5680887 m, 76035 m/sec, 37588037 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 70/276 19/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 2803163 m, 35177 m/sec, 15174778 t fired, .
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[[35mlola[0m][.] 79 CTL SRCH 77/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 5994288 m, 62680 m/sec, 39995196 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 75/276 21/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 2999787 m, 39324 m/sec, 16244045 t fired, .
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[[35mlola[0m][.] 80 AGEF EXCL 80/276 22/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 3197777 m, 39598 m/sec, 17293490 t fired, .
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[[35mlola[0m][.] 79 CTL SRCH 102/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 7690752 m, 69776 m/sec, 52214451 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 100/276 27/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 3927360 m, 34340 m/sec, 21611214 t fired, .
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[[35mlola[0m][.] 79 CTL SRCH 107/3592 1/5 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-15 8071888 m, 76227 m/sec, 54906928 t fired, .
[[35mlola[0m][.] 80 AGEF EXCL 105/276 28/2000 FamilyReunion-COL-L00010M0001C001P001G001-CTLCardinality-2024-10 4108177 m, 36163 m/sec, 22732570 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FamilyReunion-COL-L00010M0001C001P001G001"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FamilyReunion-COL-L00010M0001C001P001G001, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267900385"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FamilyReunion-COL-L00010M0001C001P001G001.tgz
mv FamilyReunion-COL-L00010M0001C001P001G001 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;