fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r159-smll-171636267800340
Last Updated
July 7, 2024

About the Execution of LoLA for FMS-PT-01000

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1756.300 16305.00 16575.00 119.90 FTFFFFFTTFTTFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267800340.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-01000, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267800340
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 552K
-rw-r--r-- 1 mcc users 5.7K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 58K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 70K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 22:09 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 155K Apr 11 22:09 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 11 22:09 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 109K Apr 11 22:09 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 16K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-01000-LTLFireability-00
FORMULA_NAME FMS-PT-01000-LTLFireability-01
FORMULA_NAME FMS-PT-01000-LTLFireability-02
FORMULA_NAME FMS-PT-01000-LTLFireability-03
FORMULA_NAME FMS-PT-01000-LTLFireability-04
FORMULA_NAME FMS-PT-01000-LTLFireability-05
FORMULA_NAME FMS-PT-01000-LTLFireability-06
FORMULA_NAME FMS-PT-01000-LTLFireability-07
FORMULA_NAME FMS-PT-01000-LTLFireability-08
FORMULA_NAME FMS-PT-01000-LTLFireability-09
FORMULA_NAME FMS-PT-01000-LTLFireability-10
FORMULA_NAME FMS-PT-01000-LTLFireability-11
FORMULA_NAME FMS-PT-01000-LTLFireability-12
FORMULA_NAME FMS-PT-01000-LTLFireability-13
FORMULA_NAME FMS-PT-01000-LTLFireability-14
FORMULA_NAME FMS-PT-01000-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717139981124

FORMULA FMS-PT-01000-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-01000-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[lola] FINAL RESULTS
[lola]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola] FMS-PT-01000-LTLFireability-00: CONJ false LTL model checker
[lola] FMS-PT-01000-LTLFireability-01: LTL true LTL model checker
[lola] FMS-PT-01000-LTLFireability-02: F false state space / EG
[lola] FMS-PT-01000-LTLFireability-03: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-04: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-05: CONJ false LTL model checker
[lola] FMS-PT-01000-LTLFireability-06: CONJ false LTL model checker
[lola] FMS-PT-01000-LTLFireability-07: LTL true LTL model checker
[lola] FMS-PT-01000-LTLFireability-08: LTL true LTL model checker
[lola] FMS-PT-01000-LTLFireability-09: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-10: LTL true LTL model checker
[lola] FMS-PT-01000-LTLFireability-11: LTL true LTL model checker
[lola] FMS-PT-01000-LTLFireability-12: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-13: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-14: LTL false LTL model checker
[lola] FMS-PT-01000-LTLFireability-15: LTL false LTL model checker
[lola]
[lola] Time elapsed: 16 secs. Pages in use: 47

BK_STOP 1717139997429

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 5 (type EXCL) for 0 FMS-PT-01000-LTLFireability-00
[lola][I] time limit : 112 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 5 (type EXCL) for FMS-PT-01000-LTLFireability-00
[lola][I] result : false
[lola][I] markings : 1003
[lola][I] fired transitions : 2003
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 65 (type EXCL) for 10 FMS-PT-01000-LTLFireability-02
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 68 (type EQUN) for 10 FMS-PT-01000-LTLFireability-02
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 65 (type EXCL) for FMS-PT-01000-LTLFireability-02
[lola][I] result : true
[lola][I] markings : 1
[lola][I] fired transitions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 68 (type EQUN) for FMS-PT-01000-LTLFireability-02 (obsolete)
[lola][I] LAUNCH task # 8 (type EXCL) for 7 FMS-PT-01000-LTLFireability-01
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 8 (type EXCL) for FMS-PT-01000-LTLFireability-01
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 17 (type EXCL) for 16 FMS-PT-01000-LTLFireability-04
[lola][I] time limit : 200 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 68 (type EQUN) for FMS-PT-01000-LTLFireability-02
[lola][I] result : true
[lola][I] FINISHED task # 17 (type EXCL) for FMS-PT-01000-LTLFireability-04
[lola][I] result : false
[lola][I] markings : 20037
[lola][I] fired transitions : 20037
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 59 (type EXCL) for 58 FMS-PT-01000-LTLFireability-14
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-01000-LTLFireability-00: CONJ false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-01: LTL true LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-02: F false state space / EG
[lola][.] FMS-PT-01000-LTLFireability-04: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-01000-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-05: CONJ 0 3 0 0 3 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 59 LTL EXCL 5/240 23/2000 FMS-PT-01000-LTLFireability-14 3364953 m, 672990 m/sec, 6165671 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 23
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 59 (type EXCL) for FMS-PT-01000-LTLFireability-14
[lola][I] result : false
[lola][I] markings : 4001005
[lola][I] fired transitions : 7331007
[lola][I] time used : 6
[lola][I] memory pages used : 27
[lola][I] LAUNCH task # 56 (type EXCL) for 55 FMS-PT-01000-LTLFireability-13
[lola][I] time limit : 256 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 56 (type EXCL) for FMS-PT-01000-LTLFireability-13
[lola][I] result : false
[lola][I] markings : 6000
[lola][I] fired transitions : 6000
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 53 (type EXCL) for 52 FMS-PT-01000-LTLFireability-12
[lola][I] time limit : 276 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-01000-LTLFireability-00: CONJ false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-01: LTL true LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-02: F false state space / EG
[lola][.] FMS-PT-01000-LTLFireability-04: LTL false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-13: LTL false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-14: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-01000-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-05: CONJ 0 3 0 0 3 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 LTL EXCL 4/276 20/2000 FMS-PT-01000-LTLFireability-12 2954039 m, 590807 m/sec, 5413118 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 27
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-01000-LTLFireability-00: CONJ false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-01: LTL true LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-02: F false state space / EG
[lola][.] FMS-PT-01000-LTLFireability-04: LTL false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-13: LTL false LTL model checker
[lola][.] FMS-PT-01000-LTLFireability-14: LTL false LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-01000-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-05: CONJ 0 3 0 0 3 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-06: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-12: LTL 0 0 1 0 1 0 0 0
[lola][.] FMS-PT-01000-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 53 LTL EXCL 9/276 42/2000 FMS-PT-01000-LTLFireability-12 6318700 m, 672932 m/sec, 11192929 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 42
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I] FINISHED task # 53 (type EXCL) for FMS-PT-01000-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 7015018
[lola][I] fired transitions : 12354014
[lola][I] time used : 10
[lola][I] memory pages used : 47
[lola][I] LAUNCH task # 41 (type EXCL) for 40 FMS-PT-01000-LTLFireability-08
[lola][I] time limit : 298 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 41 (type EXCL) for FMS-PT-01000-LTLFireability-08
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type EXCL) for 37 FMS-PT-01000-LTLFireability-07
[lola][I] time limit : 325 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type EXCL) for FMS-PT-01000-LTLFireability-07
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 35 (type EXCL) for 30 FMS-PT-01000-LTLFireability-06
[lola][I] time limit : 358 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 35 (type EXCL) for FMS-PT-01000-LTLFireability-06
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 19 FMS-PT-01000-LTLFireability-05
[lola][I] time limit : 448 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 28 (type EXCL) for FMS-PT-01000-LTLFireability-05
[lola][I] result : true
[lola][I] markings : 4
[lola][I] fired transitions : 3
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 22 (type EXCL) for 19 FMS-PT-01000-LTLFireability-05
[lola][I] time limit : 512 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 22 (type EXCL) for FMS-PT-01000-LTLFireability-05
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 14 (type EXCL) for 13 FMS-PT-01000-LTLFireability-03
[lola][I] time limit : 716 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 14 (type EXCL) for FMS-PT-01000-LTLFireability-03
[lola][I] result : false
[lola][I] markings : 7
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 62 (type EXCL) for 61 FMS-PT-01000-LTLFireability-15
[lola][I] time limit : 896 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 62 (type EXCL) for FMS-PT-01000-LTLFireability-15
[lola][I] result : false
[lola][I] markings : 1002
[lola][I] fired transitions : 1003
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 50 (type EXCL) for 49 FMS-PT-01000-LTLFireability-11
[lola][I] time limit : 1194 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 50 (type EXCL) for FMS-PT-01000-LTLFireability-11
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 44 (type EXCL) for 43 FMS-PT-01000-LTLFireability-09
[lola][I] time limit : 1792 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 44 (type EXCL) for FMS-PT-01000-LTLFireability-09
[lola][I] result : false
[lola][I] markings : 3003
[lola][I] fired transitions : 3004
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 47 (type EXCL) for 46 FMS-PT-01000-LTLFireability-10
[lola][I] time limit : 3584 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for FMS-PT-01000-LTLFireability-10
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] Portfolio finished: no open formulas

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-01000"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-01000, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267800340"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-01000.tgz
mv FMS-PT-01000 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;