About the Execution of LoLA for FMS-PT-00500
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.079 | 196424.00 | 196900.00 | 873.10 | F?F?F????FF????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267800332.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-00500, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267800332
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 11 22:17 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Apr 11 22:17 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Apr 11 22:16 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Apr 11 22:16 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 16K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00500-LTLFireability-00
FORMULA_NAME FMS-PT-00500-LTLFireability-01
FORMULA_NAME FMS-PT-00500-LTLFireability-02
FORMULA_NAME FMS-PT-00500-LTLFireability-03
FORMULA_NAME FMS-PT-00500-LTLFireability-04
FORMULA_NAME FMS-PT-00500-LTLFireability-05
FORMULA_NAME FMS-PT-00500-LTLFireability-06
FORMULA_NAME FMS-PT-00500-LTLFireability-07
FORMULA_NAME FMS-PT-00500-LTLFireability-08
FORMULA_NAME FMS-PT-00500-LTLFireability-09
FORMULA_NAME FMS-PT-00500-LTLFireability-10
FORMULA_NAME FMS-PT-00500-LTLFireability-11
FORMULA_NAME FMS-PT-00500-LTLFireability-12
FORMULA_NAME FMS-PT-00500-LTLFireability-13
FORMULA_NAME FMS-PT-00500-LTLFireability-14
FORMULA_NAME FMS-PT-00500-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717138836046
FORMULA FMS-PT-00500-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00500-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00500-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00500-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00500-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717139032470
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 3 (type CNST) for 0 FMS-PT-00500-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 45 (type CNST) for 42 FMS-PT-00500-LTLFireability-10
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 3 (type CNST) for FMS-PT-00500-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 45 (type CNST) for FMS-PT-00500-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 11 (type EXCL) for 10 FMS-PT-00500-LTLFireability-02
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 11 (type EXCL) for FMS-PT-00500-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 6
[[35mlola[0m][I] fired transitions : 7
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 17 (type EXCL) for 16 FMS-PT-00500-LTLFireability-04
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 17 (type EXCL) for FMS-PT-00500-LTLFireability-04
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 502
[[35mlola[0m][I] fired transitions : 1002
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 20 (type EXCL) for 19 FMS-PT-00500-LTLFireability-05
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[*** LOG ERROR #0001 ***] [2024-05-31 07:00:36] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 31 FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 31 FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 56 FMS-PT-00500-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for FMS-PT-00500-LTLFireability-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 78 (type FNDP) for 31 FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type FNDP) for FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 70 (type EQUN) for FMS-PT-00500-LTLFireability-09 (obsolete)
[[35mlola[0m][W] CANCELED task # 78 (type FNDP) for FMS-PT-00500-LTLFireability-09 (obsolete)
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 78 (type FNDP) for FMS-PT-00500-LTLFireability-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 5/327 22/2000 FMS-PT-00500-LTLFireability-05 3241060 m, 648212 m/sec, 5727627 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 10/327 42/2000 FMS-PT-00500-LTLFireability-05 6309791 m, 613746 m/sec, 11131096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 42
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 15/327 60/2000 FMS-PT-00500-LTLFireability-05 9105696 m, 559181 m/sec, 15983685 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 20/327 79/2000 FMS-PT-00500-LTLFireability-05 11966295 m, 572119 m/sec, 20939631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 25/327 97/2000 FMS-PT-00500-LTLFireability-05 14765391 m, 559819 m/sec, 25789160 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 30/327 113/2000 FMS-PT-00500-LTLFireability-05 17311921 m, 509306 m/sec, 30207647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 113
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 35/327 130/2000 FMS-PT-00500-LTLFireability-05 19897651 m, 517146 m/sec, 34690422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 40/327 145/2000 FMS-PT-00500-LTLFireability-05 22188731 m, 458216 m/sec, 38659416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 45/327 161/2000 FMS-PT-00500-LTLFireability-05 24692690 m, 500791 m/sec, 43002327 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 50/327 177/2000 FMS-PT-00500-LTLFireability-05 27064392 m, 474340 m/sec, 47109037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 55/327 192/2000 FMS-PT-00500-LTLFireability-05 29406887 m, 468499 m/sec, 51171832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 192
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 60/327 207/2000 FMS-PT-00500-LTLFireability-05 31719827 m, 462588 m/sec, 55171578 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 65/327 222/2000 FMS-PT-00500-LTLFireability-05 34118881 m, 479810 m/sec, 59327037 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 70/327 237/2000 FMS-PT-00500-LTLFireability-05 36426577 m, 461539 m/sec, 63321154 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 237
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 75/327 252/2000 FMS-PT-00500-LTLFireability-05 38737482 m, 462181 m/sec, 67333832 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 252
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 80/327 267/2000 FMS-PT-00500-LTLFireability-05 41034763 m, 459456 m/sec, 71309224 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 267
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 85/327 282/2000 FMS-PT-00500-LTLFireability-05 43309100 m, 454867 m/sec, 75259671 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 282
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 90/327 297/2000 FMS-PT-00500-LTLFireability-05 45592814 m, 456742 m/sec, 79218270 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 95/327 311/2000 FMS-PT-00500-LTLFireability-05 47835550 m, 448547 m/sec, 83100755 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 311
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 100/327 326/2000 FMS-PT-00500-LTLFireability-05 50126202 m, 458130 m/sec, 87062472 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 326
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 105/327 340/2000 FMS-PT-00500-LTLFireability-05 52320176 m, 438794 m/sec, 90866030 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 340
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 110/327 355/2000 FMS-PT-00500-LTLFireability-05 54524041 m, 440773 m/sec, 94680683 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 355
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 115/327 369/2000 FMS-PT-00500-LTLFireability-05 56692561 m, 433704 m/sec, 98450550 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 369
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 120/327 383/2000 FMS-PT-00500-LTLFireability-05 58942301 m, 449948 m/sec, 102336026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 383
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 125/327 397/2000 FMS-PT-00500-LTLFireability-05 61093059 m, 430151 m/sec, 106059241 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 397
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 130/327 412/2000 FMS-PT-00500-LTLFireability-05 63337803 m, 448948 m/sec, 109943237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 412
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 135/327 426/2000 FMS-PT-00500-LTLFireability-05 65434824 m, 419404 m/sec, 113581458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 140/327 440/2000 FMS-PT-00500-LTLFireability-05 67650934 m, 443222 m/sec, 117421370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 440
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 145/327 453/2000 FMS-PT-00500-LTLFireability-05 69747330 m, 419279 m/sec, 121064966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 150/327 468/2000 FMS-PT-00500-LTLFireability-05 71941774 m, 438888 m/sec, 124865057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 468
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 155/327 481/2000 FMS-PT-00500-LTLFireability-05 74052458 m, 422136 m/sec, 128507610 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 481
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 160/327 495/2000 FMS-PT-00500-LTLFireability-05 76214782 m, 432464 m/sec, 132267931 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 495
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 165/327 509/2000 FMS-PT-00500-LTLFireability-05 78308548 m, 418753 m/sec, 135876801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 509
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 170/327 523/2000 FMS-PT-00500-LTLFireability-05 80424143 m, 423119 m/sec, 139564095 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 523
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 175/327 536/2000 FMS-PT-00500-LTLFireability-05 82483918 m, 411955 m/sec, 143119163 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 180/327 550/2000 FMS-PT-00500-LTLFireability-05 84615459 m, 426308 m/sec, 146812208 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 550
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 185/327 563/2000 FMS-PT-00500-LTLFireability-05 86617134 m, 400335 m/sec, 150288436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 190/327 577/2000 FMS-PT-00500-LTLFireability-05 88724974 m, 421568 m/sec, 153940293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 577
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-00: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-02: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-04: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-09: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00500-LTLFireability-10: CONJ false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-05: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-12: F 0 1 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00500-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 20 LTL EXCL 195/327 581/2000 FMS-PT-00500-LTLFireability-05 89465652 m, 148135 m/sec, 155217167 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 581
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00500"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-00500, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267800332"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00500.tgz
mv FMS-PT-00500 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;