fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r159-smll-171636267800324
Last Updated
July 7, 2024

About the Execution of LoLA for FMS-PT-00200

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16187.384 262357.00 264415.00 1044.00 ???????F?F?FF??T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267800324.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-00200, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267800324
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 100K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.3K Apr 11 22:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 56K Apr 11 22:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Apr 11 22:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 11 22:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 17K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00200-LTLFireability-00
FORMULA_NAME FMS-PT-00200-LTLFireability-01
FORMULA_NAME FMS-PT-00200-LTLFireability-02
FORMULA_NAME FMS-PT-00200-LTLFireability-03
FORMULA_NAME FMS-PT-00200-LTLFireability-04
FORMULA_NAME FMS-PT-00200-LTLFireability-05
FORMULA_NAME FMS-PT-00200-LTLFireability-06
FORMULA_NAME FMS-PT-00200-LTLFireability-07
FORMULA_NAME FMS-PT-00200-LTLFireability-08
FORMULA_NAME FMS-PT-00200-LTLFireability-09
FORMULA_NAME FMS-PT-00200-LTLFireability-10
FORMULA_NAME FMS-PT-00200-LTLFireability-11
FORMULA_NAME FMS-PT-00200-LTLFireability-12
FORMULA_NAME FMS-PT-00200-LTLFireability-13
FORMULA_NAME FMS-PT-00200-LTLFireability-14
FORMULA_NAME FMS-PT-00200-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717137370052

FORMULA FMS-PT-00200-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00200-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00200-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00200-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00200-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717137632409

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from LTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I] LAUNCH task # 63 (type EXCL) for 25 FMS-PT-00200-LTLFireability-07
[lola][I] time limit : 144 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 61 (type FNDP) for 25 FMS-PT-00200-LTLFireability-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 62 (type EQUN) for 25 FMS-PT-00200-LTLFireability-07
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 63 (type EXCL) for FMS-PT-00200-LTLFireability-07
[lola][I] result : true
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 61 (type FNDP) for FMS-PT-00200-LTLFireability-07 (obsolete)
[lola][W] CANCELED task # 62 (type EQUN) for FMS-PT-00200-LTLFireability-07 (obsolete)
[lola][I] FINISHED task # 61 (type FNDP) for FMS-PT-00200-LTLFireability-07
[lola][I] result : true
[lola][I] tried executions : 1
[lola][I] time used : 0
[lola][I] memory pages used : 0
[lola][I] LAUNCH task # 46 (type EXCL) for 45 FMS-PT-00200-LTLFireability-11
[lola][I] time limit : 171 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 46 (type EXCL) for FMS-PT-00200-LTLFireability-11
[lola][I] result : false
[lola][I] markings : 201
[lola][I] fired transitions : 201
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 58 (type EXCL) for 57 FMS-PT-00200-LTLFireability-15
[lola][I] time limit : 189 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 58 (type EXCL) for FMS-PT-00200-LTLFireability-15
[lola][I] result : true
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 49 (type EXCL) for 48 FMS-PT-00200-LTLFireability-12
[lola][I] time limit : 225 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 49 (type EXCL) for FMS-PT-00200-LTLFireability-12
[lola][I] result : false
[lola][I] markings : 5
[lola][I] fired transitions : 5
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 38 (type CNST) for 31 FMS-PT-00200-LTLFireability-09
[lola][I] time limit : 0 sec
[lola][I] memory limit: 0 pages
[lola][I] LAUNCH task # 55 (type EXCL) for 54 FMS-PT-00200-LTLFireability-14
[lola][I] time limit : 240 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 38 (type CNST) for FMS-PT-00200-LTLFireability-09
[lola][I] result : false
[lola][I] LAUNCH task # 69 (type EQUN) for 9 FMS-PT-00200-LTLFireability-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 73 (type EQUN) for 3 FMS-PT-00200-LTLFireability-01
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 62 (type EQUN) for FMS-PT-00200-LTLFireability-07
[lola][I] result : true
[lola][I] FINISHED task # 73 (type EQUN) for FMS-PT-00200-LTLFireability-01
[lola][I] result : true
[lola][I] FINISHED task # 69 (type EQUN) for FMS-PT-00200-LTLFireability-03
[lola][I] result : true
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 5/300 18/2000 FMS-PT-00200-LTLFireability-14 2651847 m, 530369 m/sec, 5365364 t fired, .
[lola][.]
[lola][.] Time elapsed: 5 secs. Pages in use: 18
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 10/300 32/2000 FMS-PT-00200-LTLFireability-14 4861240 m, 441878 m/sec, 10405998 t fired, .
[lola][.]
[lola][.] Time elapsed: 10 secs. Pages in use: 32
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 15/300 47/2000 FMS-PT-00200-LTLFireability-14 7178209 m, 463393 m/sec, 15718322 t fired, .
[lola][.]
[lola][.] Time elapsed: 15 secs. Pages in use: 47
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 20/300 61/2000 FMS-PT-00200-LTLFireability-14 9279570 m, 420272 m/sec, 20663223 t fired, .
[lola][.]
[lola][.] Time elapsed: 20 secs. Pages in use: 61
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 25/300 75/2000 FMS-PT-00200-LTLFireability-14 11411591 m, 426404 m/sec, 25693588 t fired, .
[lola][.]
[lola][.] Time elapsed: 25 secs. Pages in use: 75
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 55 LTL EXCL 30/300 88/2000 FMS-PT-00200-LTLFireability-14 13403608 m, 398403 m/sec, 30442984 t fired, .
[lola][.]
[lola][.] Time elapsed: 30 secs. Pages in use: 88
[lola][.] # running tasks: 1 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] FMS-PT-00200-LTLFireability-07: AG false state space
[lola][.] FMS-PT-00200-LTLFireability-09: CONJ false preprocessing
[lola][.] FMS-PT-00200-LTLFireability-11: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-12: LTL false LTL model checker
[lola][.] FMS-PT-00200-LTLFireability-15: LTL true LTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] FMS-PT-00200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-01: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-03: F 0 1 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[lola][.] FMS-PT-00200-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
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[lola][.] 55 LTL EXCL 210/300 481/2000 FMS-PT-00200-LTLFireability-14 73993229 m, 323392 m/sec, 179983283 t fired, .
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[lola][.] FMS-PT-00200-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
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[lola][.]
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[lola][.] 55 LTL EXCL 215/300 490/2000 FMS-PT-00200-LTLFireability-14 75478394 m, 297033 m/sec, 183704256 t fired, .
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[lola][.] 55 LTL EXCL 220/300 500/2000 FMS-PT-00200-LTLFireability-14 76966686 m, 297658 m/sec, 187525013 t fired, .
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[lola][.] 55 LTL EXCL 225/300 510/2000 FMS-PT-00200-LTLFireability-14 78460663 m, 298795 m/sec, 191322502 t fired, .
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[lola][.] 55 LTL EXCL 230/300 520/2000 FMS-PT-00200-LTLFireability-14 79975254 m, 302918 m/sec, 195134541 t fired, .
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[lola][.] 55 LTL EXCL 235/300 529/2000 FMS-PT-00200-LTLFireability-14 81382839 m, 281517 m/sec, 198743827 t fired, .
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[lola][.] 55 LTL EXCL 240/300 538/2000 FMS-PT-00200-LTLFireability-14 82857317 m, 294895 m/sec, 202497064 t fired, .
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[lola][.] 55 LTL EXCL 245/300 548/2000 FMS-PT-00200-LTLFireability-14 84379725 m, 304481 m/sec, 206239605 t fired, .
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[lola][.] 55 LTL EXCL 250/300 558/2000 FMS-PT-00200-LTLFireability-14 85832411 m, 290537 m/sec, 209949029 t fired, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00200"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-00200, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267800324"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00200.tgz
mv FMS-PT-00200 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;