About the Execution of LoLA for FMS-PT-00200
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16208.300 | 450709.00 | 449971.00 | 2123.70 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267800322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-00200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267800322
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 8.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 100K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.3K Apr 11 22:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 56K Apr 11 22:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Apr 11 22:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 80K Apr 11 22:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 17K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-00
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-01
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-02
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-03
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-04
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-05
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-06
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-07
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-08
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-09
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-10
FORMULA_NAME FMS-PT-00200-CTLFireability-2024-11
FORMULA_NAME FMS-PT-00200-CTLFireability-2023-12
FORMULA_NAME FMS-PT-00200-CTLFireability-2023-13
FORMULA_NAME FMS-PT-00200-CTLFireability-2023-14
FORMULA_NAME FMS-PT-00200-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717136849116
BK_STOP 1717137299825
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 FMS-PT-00200-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 57 (type FNDP) for 9 FMS-PT-00200-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 9 FMS-PT-00200-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type FNDP) for FMS-PT-00200-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 58 (type EQUN) for FMS-PT-00200-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for FMS-PT-00200-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for FMS-PT-00200-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 62707
[[35mlola[0m][I] fired transitions : 68118
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 FMS-PT-00200-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for FMS-PT-00200-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 FMS-PT-00200-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for FMS-PT-00200-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 FMS-PT-00200-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for FMS-PT-00200-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 42 (type EXCL) for 41 FMS-PT-00200-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 42 (type EXCL) for FMS-PT-00200-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 4635
[[35mlola[0m][I] fired transitions : 5840
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 FMS-PT-00200-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 5/300 5/2000 FMS-PT-00200-CTLFireability-2024-10 951027 m, 190205 m/sec, 6058171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 5
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 10/300 8/2000 FMS-PT-00200-CTLFireability-2024-10 1882706 m, 186335 m/sec, 12023057 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 15/300 12/2000 FMS-PT-00200-CTLFireability-2024-10 2816491 m, 186757 m/sec, 18096987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 20/300 16/2000 FMS-PT-00200-CTLFireability-2024-10 3745393 m, 185780 m/sec, 24093172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 16
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 25/300 20/2000 FMS-PT-00200-CTLFireability-2024-10 4610446 m, 173010 m/sec, 29635132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 30/300 23/2000 FMS-PT-00200-CTLFireability-2024-10 5443869 m, 166684 m/sec, 35021317 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 35/300 27/2000 FMS-PT-00200-CTLFireability-2024-10 6311630 m, 173552 m/sec, 40662437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 27
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 40/300 31/2000 FMS-PT-00200-CTLFireability-2024-10 7139929 m, 165659 m/sec, 45945378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 45/300 34/2000 FMS-PT-00200-CTLFireability-2024-10 7985504 m, 169115 m/sec, 51440688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 50/300 38/2000 FMS-PT-00200-CTLFireability-2024-10 8853678 m, 173634 m/sec, 56939244 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 38
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 55/300 41/2000 FMS-PT-00200-CTLFireability-2024-10 9693905 m, 168045 m/sec, 62495990 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 60/300 45/2000 FMS-PT-00200-CTLFireability-2024-10 10558239 m, 172866 m/sec, 68043654 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 65/300 49/2000 FMS-PT-00200-CTLFireability-2024-10 11423499 m, 173052 m/sec, 73620414 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 70/300 52/2000 FMS-PT-00200-CTLFireability-2024-10 12237326 m, 162765 m/sec, 78922133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 52
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 75/300 56/2000 FMS-PT-00200-CTLFireability-2024-10 13092870 m, 171108 m/sec, 84410323 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 56
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 80/300 59/2000 FMS-PT-00200-CTLFireability-2024-10 13900963 m, 161618 m/sec, 89608230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 59
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 85/300 63/2000 FMS-PT-00200-CTLFireability-2024-10 14759365 m, 171680 m/sec, 95065521 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 63
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 90/300 66/2000 FMS-PT-00200-CTLFireability-2024-10 15566100 m, 161347 m/sec, 100391392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 66
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 95/300 69/2000 FMS-PT-00200-CTLFireability-2024-10 16377042 m, 162188 m/sec, 105647626 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 69
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 100/300 73/2000 FMS-PT-00200-CTLFireability-2024-10 17191607 m, 162913 m/sec, 110807571 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 105/300 76/2000 FMS-PT-00200-CTLFireability-2024-10 17967029 m, 155084 m/sec, 115884823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 110/300 79/2000 FMS-PT-00200-CTLFireability-2024-10 18798916 m, 166377 m/sec, 121280745 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 79
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 115/300 83/2000 FMS-PT-00200-CTLFireability-2024-10 19644745 m, 169165 m/sec, 126632787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 120/300 87/2000 FMS-PT-00200-CTLFireability-2024-10 20470144 m, 165079 m/sec, 131862197 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 87
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 125/300 90/2000 FMS-PT-00200-CTLFireability-2024-10 21354644 m, 176900 m/sec, 137675220 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 90
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 130/300 95/2000 FMS-PT-00200-CTLFireability-2024-10 22461774 m, 221426 m/sec, 144686310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 95
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 135/300 99/2000 FMS-PT-00200-CTLFireability-2024-10 23472157 m, 202076 m/sec, 151124309 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 140/300 104/2000 FMS-PT-00200-CTLFireability-2024-10 24505031 m, 206574 m/sec, 157737603 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 145/300 108/2000 FMS-PT-00200-CTLFireability-2024-10 25509871 m, 200968 m/sec, 164172392 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 150/300 112/2000 FMS-PT-00200-CTLFireability-2024-10 26520672 m, 202160 m/sec, 170644765 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 155/300 116/2000 FMS-PT-00200-CTLFireability-2024-10 27393102 m, 174486 m/sec, 176293611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 116
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 160/300 119/2000 FMS-PT-00200-CTLFireability-2024-10 28293225 m, 180024 m/sec, 182139818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 165/300 123/2000 FMS-PT-00200-CTLFireability-2024-10 29188467 m, 179048 m/sec, 187933798 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 123
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 170/300 127/2000 FMS-PT-00200-CTLFireability-2024-10 30118917 m, 186090 m/sec, 194010338 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 127
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 175/300 131/2000 FMS-PT-00200-CTLFireability-2024-10 30984579 m, 173132 m/sec, 199656561 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 180/300 135/2000 FMS-PT-00200-CTLFireability-2024-10 31982950 m, 199674 m/sec, 206101750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 185/300 139/2000 FMS-PT-00200-CTLFireability-2024-10 32965237 m, 196457 m/sec, 212380055 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 190/300 143/2000 FMS-PT-00200-CTLFireability-2024-10 33881218 m, 183196 m/sec, 218339131 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 143
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 195/300 147/2000 FMS-PT-00200-CTLFireability-2024-10 34790385 m, 181833 m/sec, 224257936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 147
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 200/300 151/2000 FMS-PT-00200-CTLFireability-2024-10 35713888 m, 184700 m/sec, 230279016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 205/300 154/2000 FMS-PT-00200-CTLFireability-2024-10 36545525 m, 166327 m/sec, 235762373 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 210/300 158/2000 FMS-PT-00200-CTLFireability-2024-10 37442451 m, 179385 m/sec, 241632759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 215/300 161/2000 FMS-PT-00200-CTLFireability-2024-10 38278078 m, 167125 m/sec, 247161035 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 220/300 165/2000 FMS-PT-00200-CTLFireability-2024-10 39175023 m, 179389 m/sec, 252981386 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 225/300 169/2000 FMS-PT-00200-CTLFireability-2024-10 40008193 m, 166634 m/sec, 258445552 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 169
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 230/300 172/2000 FMS-PT-00200-CTLFireability-2024-10 40862470 m, 170855 m/sec, 264112450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 172
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 235/300 176/2000 FMS-PT-00200-CTLFireability-2024-10 41720650 m, 171636 m/sec, 269793936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 240/300 180/2000 FMS-PT-00200-CTLFireability-2024-10 42634918 m, 182853 m/sec, 275763252 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 245/300 183/2000 FMS-PT-00200-CTLFireability-2024-10 43410353 m, 155087 m/sec, 280844121 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 250/300 187/2000 FMS-PT-00200-CTLFireability-2024-10 44271410 m, 172211 m/sec, 286554897 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 187
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 255/300 190/2000 FMS-PT-00200-CTLFireability-2024-10 45054570 m, 156632 m/sec, 291795422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 260/300 193/2000 FMS-PT-00200-CTLFireability-2024-10 45893912 m, 167868 m/sec, 297321445 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 265/300 197/2000 FMS-PT-00200-CTLFireability-2024-10 46692883 m, 159794 m/sec, 302629913 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 270/300 200/2000 FMS-PT-00200-CTLFireability-2024-10 47524613 m, 166346 m/sec, 308149068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 200
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 275/300 204/2000 FMS-PT-00200-CTLFireability-2024-10 48345255 m, 164128 m/sec, 313555199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 280/300 207/2000 FMS-PT-00200-CTLFireability-2024-10 49161744 m, 163297 m/sec, 318978347 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 285/300 210/2000 FMS-PT-00200-CTLFireability-2024-10 49953167 m, 158284 m/sec, 324230490 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 210
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 290/300 214/2000 FMS-PT-00200-CTLFireability-2024-10 50775081 m, 164382 m/sec, 329671900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 295/300 217/2000 FMS-PT-00200-CTLFireability-2024-10 51587949 m, 162573 m/sec, 334963377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 217
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 300/300 221/2000 FMS-PT-00200-CTLFireability-2024-10 52391619 m, 160734 m/sec, 340303749 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 39 (type EXCL) for FMS-PT-00200-CTLFireability-2024-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 224
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 FMS-PT-00200-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 38 FMS-PT-00200-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 3295 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for FMS-PT-00200-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1212
[[35mlola[0m][I] fired transitions : 1215
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 5/299 5/5 FMS-PT-00200-CTLFireability-2024-10 985784 m, -10281167 m/sec, 6256049 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 39 (type EXCL) for FMS-PT-00200-CTLFireability-2024-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 229
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 30 (type EXCL) for 25 FMS-PT-00200-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 328 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 30 (type EXCL) for FMS-PT-00200-CTLFireability-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 25 FMS-PT-00200-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 365 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 5/365 14/2000 FMS-PT-00200-CTLFireability-2024-07 3051849 m, 610369 m/sec, 6157089 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 238
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 10/365 27/2000 FMS-PT-00200-CTLFireability-2024-07 6100421 m, 609714 m/sec, 12311772 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 251
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 15/365 41/2000 FMS-PT-00200-CTLFireability-2024-07 9225336 m, 624983 m/sec, 18620649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 265
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 20/365 54/2000 FMS-PT-00200-CTLFireability-2024-07 12339804 m, 622893 m/sec, 24908202 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 25/365 68/2000 FMS-PT-00200-CTLFireability-2024-07 15500537 m, 632146 m/sec, 31289236 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 292
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 30/365 80/2000 FMS-PT-00200-CTLFireability-2024-07 18270481 m, 553988 m/sec, 37171053 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 304
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 35/365 92/2000 FMS-PT-00200-CTLFireability-2024-07 21069637 m, 559831 m/sec, 42799977 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 316
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 40/365 103/2000 FMS-PT-00200-CTLFireability-2024-07 23748432 m, 535759 m/sec, 48186484 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 327
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 45/365 114/2000 FMS-PT-00200-CTLFireability-2024-07 26406802 m, 531674 m/sec, 53532004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 338
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 50/365 125/2000 FMS-PT-00200-CTLFireability-2024-07 28923946 m, 503428 m/sec, 58593508 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 349
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 55/365 135/2000 FMS-PT-00200-CTLFireability-2024-07 31339239 m, 483058 m/sec, 63450207 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 359
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 60/365 147/2000 FMS-PT-00200-CTLFireability-2024-07 34068541 m, 545860 m/sec, 68938827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 65/365 158/2000 FMS-PT-00200-CTLFireability-2024-07 36738526 m, 533997 m/sec, 74307753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 70/365 169/2000 FMS-PT-00200-CTLFireability-2024-07 39398353 m, 531965 m/sec, 79656198 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 75/365 180/2000 FMS-PT-00200-CTLFireability-2024-07 42000456 m, 520420 m/sec, 84888601 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 404
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 80/365 191/2000 FMS-PT-00200-CTLFireability-2024-07 44530035 m, 505915 m/sec, 89974999 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 415
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 85/365 202/2000 FMS-PT-00200-CTLFireability-2024-07 47262554 m, 546503 m/sec, 95469646 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 90/365 214/2000 FMS-PT-00200-CTLFireability-2024-07 49947248 m, 536938 m/sec, 100868345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 438
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 95/365 225/2000 FMS-PT-00200-CTLFireability-2024-07 52664964 m, 543543 m/sec, 106333101 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 449
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 100/365 237/2000 FMS-PT-00200-CTLFireability-2024-07 55427538 m, 552514 m/sec, 111888173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 105/365 248/2000 FMS-PT-00200-CTLFireability-2024-07 57978540 m, 510200 m/sec, 117349987 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 110/365 255/2000 FMS-PT-00200-CTLFireability-2024-07 59576174 m, 319526 m/sec, 121840068 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 479
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 115/365 264/2000 FMS-PT-00200-CTLFireability-2024-07 61727278 m, 430220 m/sec, 126619418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 488
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 120/365 272/2000 FMS-PT-00200-CTLFireability-2024-07 63573871 m, 369318 m/sec, 131002506 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 496
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 125/365 279/2000 FMS-PT-00200-CTLFireability-2024-07 65190288 m, 323283 m/sec, 134980427 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 503
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2024-11: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-12: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00200-CTLFireability-2023-15: CTL true CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-03: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-07: CONJ 0 0 1 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00200-CTLFireability-2024-10: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 28 CTL EXCL 130/365 285/2000 FMS-PT-00200-CTLFireability-2024-07 66768883 m, 315719 m/sec, 138923335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 509
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 400 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-00200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267800322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00200.tgz
mv FMS-PT-00200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;