About the Execution of LoLA for FMS-PT-00050
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16209.212 | 578346.00 | 579348.00 | 1833.40 | ??TT???????????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267700306.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-00050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267700306
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 468K
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.4K Apr 11 22:19 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 84K Apr 11 22:19 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.5K Apr 11 22:19 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Apr 11 22:19 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 16K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-00
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-01
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-02
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-03
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-04
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-05
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-06
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-07
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-08
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-09
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-10
FORMULA_NAME FMS-PT-00050-CTLFireability-2024-11
FORMULA_NAME FMS-PT-00050-CTLFireability-2023-12
FORMULA_NAME FMS-PT-00050-CTLFireability-2023-13
FORMULA_NAME FMS-PT-00050-CTLFireability-2023-14
FORMULA_NAME FMS-PT-00050-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717135127392
FORMULA FMS-PT-00050-CTLFireability-2024-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00050-CTLFireability-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717135705738
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FMS-PT-00050-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type FNDP) for 6 FMS-PT-00050-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 6 FMS-PT-00050-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type FNDP) for 9 FMS-PT-00050-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for FMS-PT-00050-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][W] CANCELED task # 56 (type FNDP) for FMS-PT-00050-CTLFireability-2024-02 (obsolete)
[[35mlola[0m][I] LAUNCH task # 60 (type EQUN) for 9 FMS-PT-00050-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 57 (type FNDP) for FMS-PT-00050-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 60 (type EQUN) for FMS-PT-00050-CTLFireability-2024-03 (obsolete)
[[35mlola[0m][I] FINISHED task # 56 (type FNDP) for FMS-PT-00050-CTLFireability-2024-02
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] FINISHED task # 60 (type EQUN) for FMS-PT-00050-CTLFireability-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for FMS-PT-00050-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 19091
[[35mlola[0m][I] fired transitions : 68004
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 54 (type EXCL) for 53 FMS-PT-00050-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 54 (type EXCL) for FMS-PT-00050-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 17
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 50 FMS-PT-00050-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 51 (type EXCL) for FMS-PT-00050-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5317
[[35mlola[0m][I] fired transitions : 14372
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 48 (type EXCL) for 47 FMS-PT-00050-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 48 (type EXCL) for FMS-PT-00050-CTLFireability-2023-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 FMS-PT-00050-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 300 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 5/300 11/2000 FMS-PT-00050-CTLFireability-2023-12 2396083 m, 479216 m/sec, 3221349 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 11
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 10/300 20/2000 FMS-PT-00050-CTLFireability-2023-12 4549310 m, 430645 m/sec, 6489923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 20
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 15/300 28/2000 FMS-PT-00050-CTLFireability-2023-12 6554657 m, 401069 m/sec, 9684674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 28
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 20/300 36/2000 FMS-PT-00050-CTLFireability-2023-12 8349153 m, 358899 m/sec, 12640544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 36
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 25/300 43/2000 FMS-PT-00050-CTLFireability-2023-12 10142627 m, 358694 m/sec, 15561403 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 43
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 30/300 50/2000 FMS-PT-00050-CTLFireability-2023-12 11887050 m, 348884 m/sec, 18506966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 35/300 57/2000 FMS-PT-00050-CTLFireability-2023-12 13468440 m, 316278 m/sec, 21304032 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 40/300 64/2000 FMS-PT-00050-CTLFireability-2023-12 15057934 m, 317898 m/sec, 24057572 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 64
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 45/300 70/2000 FMS-PT-00050-CTLFireability-2023-12 16618664 m, 312146 m/sec, 26822033 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 70
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 50/300 77/2000 FMS-PT-00050-CTLFireability-2023-12 18190830 m, 314433 m/sec, 29632933 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 77
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 55/300 83/2000 FMS-PT-00050-CTLFireability-2023-12 19739526 m, 309739 m/sec, 32453880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 83
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 60/300 91/2000 FMS-PT-00050-CTLFireability-2023-12 21454146 m, 342924 m/sec, 35372873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 65/300 97/2000 FMS-PT-00050-CTLFireability-2023-12 23018464 m, 312863 m/sec, 38144817 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 97
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 70/300 104/2000 FMS-PT-00050-CTLFireability-2023-12 24565812 m, 309469 m/sec, 40913900 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 104
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 75/300 110/2000 FMS-PT-00050-CTLFireability-2023-12 26096359 m, 306109 m/sec, 43744804 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 80/300 117/2000 FMS-PT-00050-CTLFireability-2023-12 27790583 m, 338844 m/sec, 46728425 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 85/300 124/2000 FMS-PT-00050-CTLFireability-2023-12 29427562 m, 327395 m/sec, 49694076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 90/300 131/2000 FMS-PT-00050-CTLFireability-2023-12 31057022 m, 325892 m/sec, 52602324 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 131
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 95/300 138/2000 FMS-PT-00050-CTLFireability-2023-12 32666691 m, 321933 m/sec, 55515996 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 138
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 100/300 144/2000 FMS-PT-00050-CTLFireability-2023-12 34237154 m, 314092 m/sec, 58440611 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 105/300 151/2000 FMS-PT-00050-CTLFireability-2023-12 35839654 m, 320500 m/sec, 61322184 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 151
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 110/300 158/2000 FMS-PT-00050-CTLFireability-2023-12 37426520 m, 317373 m/sec, 64220566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 158
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 115/300 164/2000 FMS-PT-00050-CTLFireability-2023-12 38975021 m, 309700 m/sec, 67058043 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 164
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 120/300 171/2000 FMS-PT-00050-CTLFireability-2023-12 40552540 m, 315503 m/sec, 69947889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 125/300 177/2000 FMS-PT-00050-CTLFireability-2023-12 42120995 m, 313691 m/sec, 72824982 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 177
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 130/300 184/2000 FMS-PT-00050-CTLFireability-2023-12 43658578 m, 307516 m/sec, 75639962 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 135/300 190/2000 FMS-PT-00050-CTLFireability-2023-12 45176346 m, 303553 m/sec, 78456098 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 190
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 140/300 197/2000 FMS-PT-00050-CTLFireability-2023-12 46689189 m, 302568 m/sec, 81289793 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 197
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 145/300 203/2000 FMS-PT-00050-CTLFireability-2023-12 48196321 m, 301426 m/sec, 84080469 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 203
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 150/300 209/2000 FMS-PT-00050-CTLFireability-2023-12 49729059 m, 306547 m/sec, 86853605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 155/300 216/2000 FMS-PT-00050-CTLFireability-2023-12 51221864 m, 298561 m/sec, 89629877 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 160/300 222/2000 FMS-PT-00050-CTLFireability-2023-12 52709363 m, 297499 m/sec, 92446321 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 222
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 165/300 228/2000 FMS-PT-00050-CTLFireability-2023-12 54246745 m, 307476 m/sec, 95255036 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 170/300 235/2000 FMS-PT-00050-CTLFireability-2023-12 55751188 m, 300888 m/sec, 98058375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 235
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 175/300 241/2000 FMS-PT-00050-CTLFireability-2023-12 57238670 m, 297496 m/sec, 100819149 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 180/300 247/2000 FMS-PT-00050-CTLFireability-2023-12 58797983 m, 311862 m/sec, 103593991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 185/300 254/2000 FMS-PT-00050-CTLFireability-2023-12 60284210 m, 297245 m/sec, 106397346 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 254
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 190/300 260/2000 FMS-PT-00050-CTLFireability-2023-12 61751462 m, 293450 m/sec, 109125458 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 260
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 195/300 266/2000 FMS-PT-00050-CTLFireability-2023-12 63224722 m, 294652 m/sec, 111927142 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 200/300 272/2000 FMS-PT-00050-CTLFireability-2023-12 64704066 m, 295868 m/sec, 114699540 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 272
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 205/300 278/2000 FMS-PT-00050-CTLFireability-2023-12 66190680 m, 297322 m/sec, 117450519 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 210/300 284/2000 FMS-PT-00050-CTLFireability-2023-12 67647249 m, 291313 m/sec, 120220670 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 284
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 215/300 291/2000 FMS-PT-00050-CTLFireability-2023-12 69111410 m, 292832 m/sec, 122994486 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 291
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 220/300 297/2000 FMS-PT-00050-CTLFireability-2023-12 70595611 m, 296840 m/sec, 125747834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 297
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 225/300 303/2000 FMS-PT-00050-CTLFireability-2023-12 72053566 m, 291591 m/sec, 128468221 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 303
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 230/300 309/2000 FMS-PT-00050-CTLFireability-2023-12 73514372 m, 292161 m/sec, 131257717 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 309
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 235/300 315/2000 FMS-PT-00050-CTLFireability-2023-12 75024638 m, 302053 m/sec, 134078957 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 315
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 240/300 322/2000 FMS-PT-00050-CTLFireability-2023-12 76604065 m, 315885 m/sec, 136905775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 322
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 245/300 328/2000 FMS-PT-00050-CTLFireability-2023-12 78143284 m, 307843 m/sec, 139669097 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 250/300 335/2000 FMS-PT-00050-CTLFireability-2023-12 79618992 m, 295141 m/sec, 142368191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 335
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 255/300 341/2000 FMS-PT-00050-CTLFireability-2023-12 81086336 m, 293468 m/sec, 145080938 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 260/300 347/2000 FMS-PT-00050-CTLFireability-2023-12 82521776 m, 287088 m/sec, 147774310 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 265/300 352/2000 FMS-PT-00050-CTLFireability-2023-12 83827491 m, 261143 m/sec, 150265875 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 352
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 270/300 358/2000 FMS-PT-00050-CTLFireability-2023-12 85253656 m, 285233 m/sec, 152910006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 358
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 275/300 364/2000 FMS-PT-00050-CTLFireability-2023-12 86730812 m, 295431 m/sec, 155690203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 364
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 280/300 370/2000 FMS-PT-00050-CTLFireability-2023-12 88137303 m, 281298 m/sec, 158365688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 285/300 376/2000 FMS-PT-00050-CTLFireability-2023-12 89557959 m, 284131 m/sec, 161029904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 376
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 290/300 382/2000 FMS-PT-00050-CTLFireability-2023-12 90974460 m, 283300 m/sec, 163712086 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 382
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 295/300 388/2000 FMS-PT-00050-CTLFireability-2023-12 92425147 m, 290137 m/sec, 166368500 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 388
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 45 CTL EXCL 300/300 394/2000 FMS-PT-00050-CTLFireability-2023-12 93839087 m, 282788 m/sec, 169060076 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 394
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 45 (type EXCL) for FMS-PT-00050-CTLFireability-2023-12 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 33 (type EXCL) for 32 FMS-PT-00050-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 44 FMS-PT-00050-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 3295 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 33 (type EXCL) for FMS-PT-00050-CTLFireability-2024-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 401
[[35mlola[0m][I] fired transitions : 853
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] CANCELED task # 45 (type EXCL) for FMS-PT-00050-CTLFireability-2023-12 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 3 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 405
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 27 (type EXCL) for 18 FMS-PT-00050-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 329 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 27 (type EXCL) for FMS-PT-00050-CTLFireability-2024-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 FMS-PT-00050-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 411 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for FMS-PT-00050-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 614
[[35mlola[0m][I] fired transitions : 1179
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 FMS-PT-00050-CTLFireability-2024-04
[[35mlola[0m][I] time limit : 470 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for FMS-PT-00050-CTLFireability-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 564
[[35mlola[0m][I] fired transitions : 1129
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 FMS-PT-00050-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 548 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/548 11/2000 FMS-PT-00050-CTLFireability-2024-00 2499381 m, 499876 m/sec, 4011464 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 411
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/548 18/2000 FMS-PT-00050-CTLFireability-2024-00 4201871 m, 340498 m/sec, 7153574 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 418
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/548 26/2000 FMS-PT-00050-CTLFireability-2024-00 5970752 m, 353776 m/sec, 10537194 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 20/548 32/2000 FMS-PT-00050-CTLFireability-2024-00 7554090 m, 316667 m/sec, 13786513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 432
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 25/548 39/2000 FMS-PT-00050-CTLFireability-2024-00 9079082 m, 304998 m/sec, 17041511 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 439
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/548 45/2000 FMS-PT-00050-CTLFireability-2024-00 10677474 m, 319678 m/sec, 20467178 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 445
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 35/548 52/2000 FMS-PT-00050-CTLFireability-2024-00 12160928 m, 296690 m/sec, 23782298 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 452
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 40/548 58/2000 FMS-PT-00050-CTLFireability-2024-00 13649078 m, 297630 m/sec, 27037527 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 458
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 45/548 64/2000 FMS-PT-00050-CTLFireability-2024-00 15102208 m, 290626 m/sec, 30264434 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 464
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 50/548 70/2000 FMS-PT-00050-CTLFireability-2024-00 16583131 m, 296184 m/sec, 33435757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 470
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 55/548 76/2000 FMS-PT-00050-CTLFireability-2024-00 17990456 m, 281465 m/sec, 36691898 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 476
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 60/548 82/2000 FMS-PT-00050-CTLFireability-2024-00 19329057 m, 267720 m/sec, 39807951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 482
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 65/548 87/2000 FMS-PT-00050-CTLFireability-2024-00 20704881 m, 275164 m/sec, 42896336 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 487
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 70/548 93/2000 FMS-PT-00050-CTLFireability-2024-00 22015699 m, 262163 m/sec, 45945859 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 493
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 75/548 99/2000 FMS-PT-00050-CTLFireability-2024-00 23453022 m, 287464 m/sec, 49094589 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 80/548 105/2000 FMS-PT-00050-CTLFireability-2024-00 24945580 m, 298511 m/sec, 52340605 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 505
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 85/548 111/2000 FMS-PT-00050-CTLFireability-2024-00 26284904 m, 267864 m/sec, 55337259 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 511
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 90/548 116/2000 FMS-PT-00050-CTLFireability-2024-00 27615052 m, 266029 m/sec, 58329387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 95/548 122/2000 FMS-PT-00050-CTLFireability-2024-00 28894113 m, 255812 m/sec, 61313354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 405 secs. Pages in use: 522
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 100/548 127/2000 FMS-PT-00050-CTLFireability-2024-00 30158914 m, 252960 m/sec, 64360570 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 410 secs. Pages in use: 527
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 105/548 132/2000 FMS-PT-00050-CTLFireability-2024-00 31463303 m, 260877 m/sec, 67405684 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 415 secs. Pages in use: 532
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 110/548 138/2000 FMS-PT-00050-CTLFireability-2024-00 32829786 m, 273296 m/sec, 70433387 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 420 secs. Pages in use: 538
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 115/548 144/2000 FMS-PT-00050-CTLFireability-2024-00 34115484 m, 257139 m/sec, 73432169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 425 secs. Pages in use: 544
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 120/548 149/2000 FMS-PT-00050-CTLFireability-2024-00 35428459 m, 262595 m/sec, 76460580 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 430 secs. Pages in use: 549
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 125/548 154/2000 FMS-PT-00050-CTLFireability-2024-00 36704179 m, 255144 m/sec, 79457405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 435 secs. Pages in use: 554
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 130/548 160/2000 FMS-PT-00050-CTLFireability-2024-00 37998499 m, 258864 m/sec, 82456381 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 440 secs. Pages in use: 560
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 135/548 165/2000 FMS-PT-00050-CTLFireability-2024-00 39244655 m, 249231 m/sec, 85387826 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 445 secs. Pages in use: 565
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 140/548 170/2000 FMS-PT-00050-CTLFireability-2024-00 40483781 m, 247825 m/sec, 88337613 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 450 secs. Pages in use: 570
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 145/548 176/2000 FMS-PT-00050-CTLFireability-2024-00 41742254 m, 251694 m/sec, 91284494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 455 secs. Pages in use: 576
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 150/548 181/2000 FMS-PT-00050-CTLFireability-2024-00 42983472 m, 248243 m/sec, 94219192 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 460 secs. Pages in use: 581
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 155/548 186/2000 FMS-PT-00050-CTLFireability-2024-00 44254516 m, 254208 m/sec, 97198757 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 465 secs. Pages in use: 586
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 160/548 191/2000 FMS-PT-00050-CTLFireability-2024-00 45510297 m, 251156 m/sec, 100144528 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 470 secs. Pages in use: 591
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 165/548 197/2000 FMS-PT-00050-CTLFireability-2024-00 46753695 m, 248679 m/sec, 103012465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 475 secs. Pages in use: 597
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 170/548 202/2000 FMS-PT-00050-CTLFireability-2024-00 48059442 m, 261149 m/sec, 105921800 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 480 secs. Pages in use: 602
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 175/548 207/2000 FMS-PT-00050-CTLFireability-2024-00 49308675 m, 249846 m/sec, 108788507 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 485 secs. Pages in use: 607
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 180/548 212/2000 FMS-PT-00050-CTLFireability-2024-00 50555160 m, 249297 m/sec, 111650420 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 490 secs. Pages in use: 612
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 185/548 218/2000 FMS-PT-00050-CTLFireability-2024-00 51821458 m, 253259 m/sec, 114486120 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 495 secs. Pages in use: 618
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 190/548 223/2000 FMS-PT-00050-CTLFireability-2024-00 53021415 m, 239991 m/sec, 117263639 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 500 secs. Pages in use: 623
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 195/548 227/2000 FMS-PT-00050-CTLFireability-2024-00 54158100 m, 227337 m/sec, 119863226 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 505 secs. Pages in use: 627
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 200/548 233/2000 FMS-PT-00050-CTLFireability-2024-00 55364696 m, 241319 m/sec, 122727158 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 510 secs. Pages in use: 633
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 205/548 238/2000 FMS-PT-00050-CTLFireability-2024-00 56583004 m, 243661 m/sec, 125558712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 515 secs. Pages in use: 638
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 210/548 243/2000 FMS-PT-00050-CTLFireability-2024-00 57783380 m, 240075 m/sec, 128316105 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 520 secs. Pages in use: 643
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 215/548 248/2000 FMS-PT-00050-CTLFireability-2024-00 58987471 m, 240818 m/sec, 131150743 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 525 secs. Pages in use: 648
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 220/548 253/2000 FMS-PT-00050-CTLFireability-2024-00 60172964 m, 237098 m/sec, 133957006 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 530 secs. Pages in use: 653
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 225/548 258/2000 FMS-PT-00050-CTLFireability-2024-00 61364655 m, 238338 m/sec, 136758666 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 535 secs. Pages in use: 658
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 230/548 263/2000 FMS-PT-00050-CTLFireability-2024-00 62574345 m, 241938 m/sec, 139562073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 540 secs. Pages in use: 663
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 235/548 268/2000 FMS-PT-00050-CTLFireability-2024-00 63782998 m, 241730 m/sec, 142446448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 545 secs. Pages in use: 668
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 240/548 273/2000 FMS-PT-00050-CTLFireability-2024-00 65002840 m, 243968 m/sec, 145228369 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 550 secs. Pages in use: 673
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 245/548 278/2000 FMS-PT-00050-CTLFireability-2024-00 66186043 m, 236640 m/sec, 148037432 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 555 secs. Pages in use: 678
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 250/548 283/2000 FMS-PT-00050-CTLFireability-2024-00 67382196 m, 239230 m/sec, 150861889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 560 secs. Pages in use: 683
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 255/548 288/2000 FMS-PT-00050-CTLFireability-2024-00 68540577 m, 231676 m/sec, 153634715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 565 secs. Pages in use: 688
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 260/548 292/2000 FMS-PT-00050-CTLFireability-2024-00 69485472 m, 188979 m/sec, 155892281 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 570 secs. Pages in use: 692
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-02: EF true state equation[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-03: EF true findpath[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2024-08: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00050-CTLFireability-2023-13: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00050-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-06: DISJ 0 1 0 0 4 0 0 1
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00050-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 266/548 294/2000 FMS-PT-00050-CTLFireability-2024-00 70163279 m, 135561 m/sec, 157372874 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 577 secs. Pages in use: 694
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-00050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267700306"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00050.tgz
mv FMS-PT-00050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;