About the Execution of LoLA for FMS-PT-00005
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1176.563 | 158020.00 | 159881.00 | 558.80 | FTFFTTTFTFFTTFFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267700282.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is FMS-PT-00005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267700282
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 6.1K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:43 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Apr 22 14:43 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 11 21:59 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 156K Apr 11 21:59 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Apr 11 21:58 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 77K Apr 11 21:58 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 6 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 17K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-00
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-01
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-02
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-03
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-04
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-05
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-06
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-07
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-08
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-09
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-10
FORMULA_NAME FMS-PT-00005-CTLFireability-2024-11
FORMULA_NAME FMS-PT-00005-CTLFireability-2023-12
FORMULA_NAME FMS-PT-00005-CTLFireability-2023-13
FORMULA_NAME FMS-PT-00005-CTLFireability-2023-14
FORMULA_NAME FMS-PT-00005-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717132651091
FORMULA FMS-PT-00005-CTLFireability-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2023-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2023-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA FMS-PT-00005-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
[[35mlola[0m] [1mFINAL RESULTS[0m
[[35mlola[0m] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-00: EFAG false tscc_search[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-02: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-03: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-04: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-05: CTL true CTL model checker[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-06: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-09: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2024-10: CONJ false findpath[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2024-11: DISJ true CTL model checker[0m
[[35mlola[0m] [1m[32mFMS-PT-00005-CTLFireability-2023-12: AGEF true tscc_search[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2023-14: CONJ false LTL model checker[0m
[[35mlola[0m] [1m[31mFMS-PT-00005-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m]
[[35mlola[0m] Time elapsed: 158 secs. Pages in use: 12
BK_STOP 1717132809111
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 FMS-PT-00005-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 105 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 80 (type FNDP) for 28 FMS-PT-00005-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 28 FMS-PT-00005-CTLFireability-2024-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 80 (type FNDP) for FMS-PT-00005-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 81 (type EQUN) for FMS-PT-00005-CTLFireability-2024-08 (obsolete)
[[35mlola[0m][I] LAUNCH task # 84 (type FNDP) for 34 FMS-PT-00005-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 85 (type EQUN) for 34 FMS-PT-00005-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 84 (type FNDP) for FMS-PT-00005-CTLFireability-2024-10
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 85 (type EQUN) for FMS-PT-00005-CTLFireability-2024-10 (obsolete)
[[35mlola[0m][I] LAUNCH task # 92 (type EQUN) for 60 FMS-PT-00005-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 94 (type EQUN) for 60 FMS-PT-00005-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for FMS-PT-00005-CTLFireability-2024-08
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 101 (type EQUN) for 0 FMS-PT-00005-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 85 (type EQUN) for FMS-PT-00005-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 94 (type EQUN) for FMS-PT-00005-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 109 (type EQUN) for 66 FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 101 (type EQUN) for FMS-PT-00005-CTLFireability-2024-00
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 103 (type EQUN) for 0 FMS-PT-00005-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 92 (type EQUN) for FMS-PT-00005-CTLFireability-2023-12
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 103 (type EQUN) for FMS-PT-00005-CTLFireability-2024-00
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 109 (type EQUN) for FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for FMS-PT-00005-CTLFireability-2024-01
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 17840
[[35mlola[0m][I] fired transitions : 128802
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 88 (type EXCL) for 66 FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 88 (type EXCL) for FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 78 (type EXCL) for 77 FMS-PT-00005-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 78 (type EXCL) for FMS-PT-00005-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 40
[[35mlola[0m][I] fired transitions : 41
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 75 (type EXCL) for 66 FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 211 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 75 (type EXCL) for FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 4
[[35mlola[0m][I] fired transitions : 3
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 66 FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for FMS-PT-00005-CTLFireability-2023-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 5
[[35mlola[0m][I] fired transitions : 5
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 64 (type EXCL) for 63 FMS-PT-00005-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 240 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 64 (type EXCL) for FMS-PT-00005-CTLFireability-2023-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 43
[[35mlola[0m][I] fired transitions : 50
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 58 (type EXCL) for 45 FMS-PT-00005-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00005-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00005-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2024-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-14: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-06: DISJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-11: DISJ 0 3 1 0 4 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2023-12: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 58 CTL EXCL 5/257 4/2000 FMS-PT-00005-CTLFireability-2024-11 952907 m, 190581 m/sec, 4753074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00005-CTLFireability-2024-01: CTL true CTL model checker[0m
[[35mlola[0m][.] [1m[32mFMS-PT-00005-CTLFireability-2024-08: EF true findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2024-10: CONJ false findpath[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-13: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-14: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mFMS-PT-00005-CTLFireability-2023-15: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-00: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] FMS-PT-00005-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][I] Portfolio finished: no open formulas
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="FMS-PT-00005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is FMS-PT-00005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267700282"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/FMS-PT-00005.tgz
mv FMS-PT-00005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;