MCC'2024- Execution of r159-smll-171636267500170

About the Execution of LoLA for EisenbergMcGuire-PT-06

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.731	2371009.00	7044120.00	5728.70	??F????F???F???F	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267500170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is EisenbergMcGuire-PT-06, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267500170
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 69K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Apr 22 14:43 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Apr 22 14:43 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.0K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 18:18 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Apr 12 16:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 123K Apr 12 16:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 12K Apr 12 16:01 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 79K Apr 12 16:01 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Apr 22 14:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Apr 22 14:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 3 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 753K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-00
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-01
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-02
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-03
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-04
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-05
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-06
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-07
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-08
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-09
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-10
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2024-11
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2023-12
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2023-13
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2023-14
FORMULA_NAME EisenbergMcGuire-PT-06-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717075479076

FORMULA EisenbergMcGuire-PT-06-CTLFireability-2023-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA EisenbergMcGuire-PT-06-CTLFireability-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA EisenbergMcGuire-PT-06-CTLFireability-2024-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA EisenbergMcGuire-PT-06-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717077850085

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 46 (type CNST) for 45 EisenbergMcGuire-PT-06-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 46 (type CNST) for EisenbergMcGuire-PT-06-CTLFireability-2023-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 EisenbergMcGuire-PT-06-CTLFireability-2024-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for EisenbergMcGuire-PT-06-CTLFireability-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 EisenbergMcGuire-PT-06-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 33 EisenbergMcGuire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 34 (type CNST) for EisenbergMcGuire-PT-06-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for EisenbergMcGuire-PT-06-CTLFireability-2024-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 51 (type EXCL) for 30 EisenbergMcGuire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 49 (type FNDP) for 30 EisenbergMcGuire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 50 (type EQUN) for 30 EisenbergMcGuire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type FNDP) for 18 EisenbergMcGuire-PT-06-CTLFireability-2024-06
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type EQUN) for EisenbergMcGuire-PT-06-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 55 (type FNDP) for 39 EisenbergMcGuire-PT-06-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2023-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 4/3597 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1 attempts, .
[[35mlola[0m][.] 51 EF EXCL 4/299 1/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 177651 m, 35530 m/sec, 334367 t fired, .
[[35mlola[0m][.] 52 EF FNDP 4/1798 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 1 attempts, .
[[35mlola[0m][.] 55 EF FNDP 3/1798 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 1 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2023-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 49 EF FNDP 9/3594 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1 attempts, .
[[35mlola[0m][.] 51 EF EXCL 9/299 2/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 437151 m, 51900 m/sec, 829572 t fired, .
[[35mlola[0m][.] 52 EF FNDP 9/1795 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 1 attempts, .
[[35mlola[0m][.] 55 EF FNDP 8/1795 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 1 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 2
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-07: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2024-11: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mEisenbergMcGuire-PT-06-CTLFireability-2023-15: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
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[[35mlola[0m][.] 51 EF EXCL 14/299 4/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 697300 m, 52029 m/sec, 1331629 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 13/1790 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 1 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 19/299 5/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 968453 m, 54230 m/sec, 1867288 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 18/1785 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 2 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 24/3579 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 2 attempts, .
[[35mlola[0m][.] 51 EF EXCL 24/299 6/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1239941 m, 54297 m/sec, 2486395 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 23/1780 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 2 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 29/299 7/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1488459 m, 49703 m/sec, 3129760 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 28/1775 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 2 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 34/299 8/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1736312 m, 49570 m/sec, 3815806 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 33/1770 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 3 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 39/299 9/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1973262 m, 47390 m/sec, 4496462 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 38/1765 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 3 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 44/299 10/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 2190663 m, 43480 m/sec, 5174599 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 43/1760 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 3 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 49/299 11/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 2424504 m, 46768 m/sec, 5849795 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 48/1755 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 4 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 54/299 12/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 2650451 m, 45189 m/sec, 6562809 t fired, .
[[35mlola[0m][.] 52 EF FNDP 54/1750 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 4 attempts, .
[[35mlola[0m][.] 55 EF FNDP 53/1750 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 4 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 59/299 13/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 2861194 m, 42148 m/sec, 7282673 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 58/1745 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 4 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 64/299 14/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 3074904 m, 42742 m/sec, 8019505 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 69/299 15/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 3302481 m, 45515 m/sec, 8721392 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 74/299 15/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 3524563 m, 44416 m/sec, 9440177 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 79/299 16/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 3742749 m, 43637 m/sec, 10144171 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 84/299 17/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 3963918 m, 44233 m/sec, 10853118 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 89/299 18/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 4183778 m, 43972 m/sec, 11556642 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 94/299 19/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 4405754 m, 44395 m/sec, 12248755 t fired, .
[[35mlola[0m][.] 52 EF FNDP 94/1710 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 7 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 99/299 20/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 4621645 m, 43178 m/sec, 12939154 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 104/299 21/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 4840063 m, 43683 m/sec, 13634036 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 109/299 22/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 5061823 m, 44352 m/sec, 14321556 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 114/299 23/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 5280473 m, 43730 m/sec, 15018491 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 119/299 24/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 5492284 m, 42362 m/sec, 15728797 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 129/299 25/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 5912900 m, 41306 m/sec, 17113216 t fired, .
[[35mlola[0m][.] 52 EF FNDP 129/1675 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 9 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 134/299 26/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 6124502 m, 42320 m/sec, 17804251 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 139/299 27/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 6337340 m, 42567 m/sec, 18507407 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 144/299 28/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 6556147 m, 43761 m/sec, 19205350 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 164/299 32/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 7419161 m, 43283 m/sec, 21978110 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 169/299 32/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 7630124 m, 42192 m/sec, 22676599 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 168/1635 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 11 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 174/299 33/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 7841535 m, 42282 m/sec, 23356349 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 179/299 34/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 8057367 m, 43166 m/sec, 24019254 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 184/299 35/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 8271804 m, 42887 m/sec, 24701814 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 189/299 36/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 8476363 m, 40911 m/sec, 25397596 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 194/299 37/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 8692540 m, 43235 m/sec, 26079527 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 204/299 39/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 9116656 m, 43913 m/sec, 27438389 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 209/299 40/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 9343351 m, 45339 m/sec, 28110922 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 214/299 40/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 9552988 m, 41927 m/sec, 28801395 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 244/299 46/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 10821063 m, 44188 m/sec, 32877051 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 249/299 47/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 11036120 m, 43011 m/sec, 33576344 t fired, .
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[[35mlola[0m][.] 55 EF FNDP 248/1555 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 16 attempts, .
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[[35mlola[0m][.] 51 EF EXCL 254/299 47/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 11252103 m, 43196 m/sec, 34255152 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 259/299 48/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 11468196 m, 43218 m/sec, 34918657 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 264/299 49/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 11690559 m, 44472 m/sec, 35589058 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 269/299 50/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 11897199 m, 41328 m/sec, 36286606 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 274/299 51/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 12113001 m, 43160 m/sec, 36976582 t fired, .
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[[35mlola[0m][.] 51 EF EXCL 279/299 52/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 12317329 m, 40865 m/sec, 37678917 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 284/3319 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 17 attempts, .
[[35mlola[0m][.] 51 EF EXCL 284/299 53/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 12528512 m, 42236 m/sec, 38358817 t fired, .
[[35mlola[0m][.] 52 EF FNDP 284/1520 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 18 attempts, .
[[35mlola[0m][.] 55 EF FNDP 283/1520 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 18 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 289/3314 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 18 attempts, .
[[35mlola[0m][.] 51 EF EXCL 289/299 54/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 12734572 m, 41212 m/sec, 39037429 t fired, .
[[35mlola[0m][.] 52 EF FNDP 289/1515 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 19 attempts, .
[[35mlola[0m][.] 55 EF FNDP 288/1515 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 18 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 294/3309 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 18 attempts, .
[[35mlola[0m][.] 51 EF EXCL 294/299 54/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 12942949 m, 41675 m/sec, 39701573 t fired, .
[[35mlola[0m][.] 52 EF FNDP 294/1510 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 19 attempts, .
[[35mlola[0m][.] 55 EF FNDP 293/1510 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 18 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 51 EF EXCL 299/299 55/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-10 13161356 m, 43681 m/sec, 40381012 t fired, .
[[35mlola[0m][.] 52 EF FNDP 299/1505 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 19 attempts, .
[[35mlola[0m][.] 55 EF FNDP 298/1505 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 18 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 52 EF FNDP 309/1495 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 20 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 15/299 6/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 961202 m, 59299 m/sec, 6699507 t fired, .
[[35mlola[0m][.] 49 EF FNDP 319/3284 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 19 attempts, .
[[35mlola[0m][.] 52 EF FNDP 319/1485 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 20 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 25/299 9/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 1531957 m, 56401 m/sec, 11004518 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 55/299 19/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 3147211 m, 52083 m/sec, 23429954 t fired, .
[[35mlola[0m][.] 49 EF FNDP 359/3244 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 22 attempts, .
[[35mlola[0m][.] 52 EF FNDP 359/1445 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 23 attempts, .
[[35mlola[0m][.] 55 EF FNDP 358/1445 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 22 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 60/299 20/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 3391387 m, 48835 m/sec, 25352069 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 65/299 21/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 3614085 m, 44539 m/sec, 27062449 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 70/299 23/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 3869044 m, 50991 m/sec, 29059746 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 130/299 40/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 6865624 m, 49409 m/sec, 52552646 t fired, .
[[35mlola[0m][.] 49 EF FNDP 434/3169 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 26 attempts, .
[[35mlola[0m][.] 52 EF FNDP 434/1370 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 27 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 439/3164 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 26 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 140/299 43/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 7360251 m, 48876 m/sec, 56468616 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 170/299 51/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 8819330 m, 48674 m/sec, 68223356 t fired, .
[[35mlola[0m][.] 49 EF FNDP 474/3129 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 28 attempts, .
[[35mlola[0m][.] 52 EF FNDP 474/1330 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 30 attempts, .
[[35mlola[0m][.] 55 EF FNDP 473/1330 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 29 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 175/299 52/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 9059196 m, 47973 m/sec, 70135412 t fired, .
[[35mlola[0m][.] 49 EF FNDP 479/3124 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 29 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
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[[35mlola[0m][.] 43 CTL EXCL 205/299 60/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 10491322 m, 47062 m/sec, 81632365 t fired, .
[[35mlola[0m][.] 49 EF FNDP 509/3094 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 30 attempts, .
[[35mlola[0m][.] 52 EF FNDP 509/1295 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 32 attempts, .
[[35mlola[0m][.] 55 EF FNDP 508/1295 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 31 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 43 CTL EXCL 245/299 71/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-14 12382564 m, 46940 m/sec, 96688243 t fired, .
[[35mlola[0m][.] 49 EF FNDP 549/3054 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 33 attempts, .
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[[35mlola[0m][.] 55 EF FNDP 548/1255 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 33 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 589/3014 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 35 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 37 CTL EXCL 5/299 5/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-12 801171 m, 160234 m/sec, 1824321 t fired, .
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[[35mlola[0m][.] 52 EF FNDP 609/1195 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 38 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 37 CTL EXCL 20/299 17/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-12 2766353 m, 125187 m/sec, 6944819 t fired, .
[[35mlola[0m][.] 49 EF FNDP 624/2979 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 37 attempts, .
[[35mlola[0m][.] 52 EF FNDP 624/1180 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 39 attempts, .
[[35mlola[0m][.] 55 EF FNDP 623/1180 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 38 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 1 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 37 CTL EXCL 60/299 45/2000 EisenbergMcGuire-PT-06-CTLFireability-2023-12 7419821 m, 115026 m/sec, 19989935 t fired, .
[[35mlola[0m][.] 49 EF FNDP 664/2939 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 39 attempts, .
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[[35mlola[0m][.] 55 EF FNDP 663/1140 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 40 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 889/2714 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 52 attempts, .
[[35mlola[0m][.] 52 EF FNDP 889/915 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-06 55 attempts, .
[[35mlola[0m][.] 55 EF FNDP 888/915 0/5 EisenbergMcGuire-PT-06-CTLFireability-2023-13 54 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 20/299 12/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 1845799 m, 84917 m/sec, 8184335 t fired, .
[[35mlola[0m][.] 49 EF FNDP 924/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 54 attempts, .
[[35mlola[0m][.] 51 EF EXCL 10/268 3/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 547793 m, 54807 m/sec, 1040859 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 25 CTL EXCL 25/299 14/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 2264873 m, 83814 m/sec, 10127132 t fired, .
[[35mlola[0m][.] 49 EF FNDP 929/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 55 attempts, .
[[35mlola[0m][.] 51 EF EXCL 15/268 4/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 819103 m, 54262 m/sec, 1564834 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 2 0 2 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 30/299 17/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 2671631 m, 81351 m/sec, 12040215 t fired, .
[[35mlola[0m][.] 49 EF FNDP 934/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 55 attempts, .
[[35mlola[0m][.] 51 EF EXCL 20/268 5/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 1097972 m, 55773 m/sec, 2154878 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 25 CTL EXCL 35/299 19/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 3076119 m, 80897 m/sec, 13945997 t fired, .
[[35mlola[0m][.] 49 EF FNDP 939/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 55 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 40/299 21/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 3475390 m, 79854 m/sec, 15841071 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 60/299 31/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 5075342 m, 80035 m/sec, 23528031 t fired, .
[[35mlola[0m][.] 49 EF FNDP 964/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 57 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 75/299 38/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 6295398 m, 84247 m/sec, 29392023 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 25 CTL EXCL 105/299 52/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 8588815 m, 75686 m/sec, 40576207 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 145/299 70/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 11637862 m, 79116 m/sec, 55584004 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1049/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 62 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 150/299 72/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 12063903 m, 85208 m/sec, 57599949 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1054/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 62 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 155/299 74/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 12493589 m, 85937 m/sec, 59607126 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1059/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 63 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 160/299 77/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 12887010 m, 78684 m/sec, 61522757 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1064/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 63 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 165/299 79/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 13299064 m, 82410 m/sec, 63493063 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1069/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 63 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 170/299 81/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 13706605 m, 81508 m/sec, 65494493 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 175/299 84/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 14111919 m, 81062 m/sec, 67490092 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 185/299 89/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 14950173 m, 85584 m/sec, 71521003 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1089/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 65 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 1134/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 67 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 25 CTL EXCL 270/299 128/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-08 21866621 m, 77976 m/sec, 104794486 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1174/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 70 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 49 EF FNDP 1184/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 70 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-05: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 16 CTL EXCL 10/299 9/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-05 1422679 m, 136749 m/sec, 3392295 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1214/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 72 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 16 CTL EXCL 30/299 24/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-05 3892805 m, 117220 m/sec, 10048965 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-14: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] 16 CTL EXCL 50/299 38/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-05 6203977 m, 121491 m/sec, 16530567 t fired, .
[[35mlola[0m][.] 49 EF FNDP 1254/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 75 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] 49 EF FNDP 1464/3598 0/5 EisenbergMcGuire-PT-06-CTLFireability-2024-10 87 attempts, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
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[[35mlola[0m][.] 13 CTL EXCL 40/299 31/2000 EisenbergMcGuire-PT-06-CTLFireability-2024-04 5125695 m, 113089 m/sec, 13511487 t fired, .
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-06: EF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-13: EF 0 1 0 0 3 0 0 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2024-10: AG 0 0 1 0 2 0 1 0
[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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[[35mlola[0m][.] EisenbergMcGuire-PT-06-CTLFireability-2023-12: CTL 0 0 0 0 1 0 1 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="EisenbergMcGuire-PT-06"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is EisenbergMcGuire-PT-06, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267500170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/EisenbergMcGuire-PT-06.tgz
mv EisenbergMcGuire-PT-06 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;