About the Execution of LoLA for ERK-PT-100000
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16207.275 | 180260.00 | 174689.00 | 927.50 | ???????????F???? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r159-smll-171636267200068.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is ERK-PT-100000, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r159-smll-171636267200068
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 436K
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 45K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 19 15:49 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Apr 22 14:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Apr 22 14:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.8K Apr 11 21:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 78K Apr 11 21:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 11 21:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 110K Apr 11 21:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Apr 22 14:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Apr 22 14:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 7 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 6.7K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ERK-PT-100000-LTLFireability-00
FORMULA_NAME ERK-PT-100000-LTLFireability-01
FORMULA_NAME ERK-PT-100000-LTLFireability-02
FORMULA_NAME ERK-PT-100000-LTLFireability-03
FORMULA_NAME ERK-PT-100000-LTLFireability-04
FORMULA_NAME ERK-PT-100000-LTLFireability-05
FORMULA_NAME ERK-PT-100000-LTLFireability-06
FORMULA_NAME ERK-PT-100000-LTLFireability-07
FORMULA_NAME ERK-PT-100000-LTLFireability-08
FORMULA_NAME ERK-PT-100000-LTLFireability-09
FORMULA_NAME ERK-PT-100000-LTLFireability-10
FORMULA_NAME ERK-PT-100000-LTLFireability-11
FORMULA_NAME ERK-PT-100000-LTLFireability-12
FORMULA_NAME ERK-PT-100000-LTLFireability-13
FORMULA_NAME ERK-PT-100000-LTLFireability-14
FORMULA_NAME ERK-PT-100000-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717017201013
FORMULA ERK-PT-100000-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717017381273
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 19 (type EXCL) for 18 ERK-PT-100000-LTLFireability-06
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 37 ERK-PT-100000-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 37 ERK-PT-100000-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 53 (type FNDP) for ERK-PT-100000-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 54 (type EQUN) for ERK-PT-100000-LTLFireability-11 (obsolete)
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for ERK-PT-100000-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 19 (type EXCL) for ERK-PT-100000-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 800003
[[35mlola[0m][I] fired transitions : 1000004
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 49 ERK-PT-100000-LTLFireability-15
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for ERK-PT-100000-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 200023
[[35mlola[0m][I] fired transitions : 200028
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 44 (type EXCL) for 43 ERK-PT-100000-LTLFireability-13
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 44 (type EXCL) for ERK-PT-100000-LTLFireability-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 41 (type EXCL) for 40 ERK-PT-100000-LTLFireability-12
[[35mlola[0m][I] time limit : 276 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 41 (type EXCL) for ERK-PT-100000-LTLFireability-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 400008
[[35mlola[0m][I] fired transitions : 400009
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 35 (type EXCL) for 34 ERK-PT-100000-LTLFireability-10
[[35mlola[0m][I] time limit : 299 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 35 (type EXCL) for ERK-PT-100000-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 200011
[[35mlola[0m][I] fired transitions : 200012
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 29 (type EXCL) for 28 ERK-PT-100000-LTLFireability-08
[[35mlola[0m][I] time limit : 327 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 29 (type EXCL) for ERK-PT-100000-LTLFireability-08
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 900025
[[35mlola[0m][I] fired transitions : 1000033
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 6
[[35mlola[0m][I] LAUNCH task # 26 (type EXCL) for 21 ERK-PT-100000-LTLFireability-07
[[35mlola[0m][I] time limit : 359 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 26 (type EXCL) for ERK-PT-100000-LTLFireability-07
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 200005
[[35mlola[0m][I] fired transitions : 200005
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 16 (type EXCL) for 15 ERK-PT-100000-LTLFireability-05
[[35mlola[0m][I] time limit : 449 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 16 (type EXCL) for ERK-PT-100000-LTLFireability-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 1000002
[[35mlola[0m][I] fired transitions : 1100000
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 7
[[35mlola[0m][I] LAUNCH task # 13 (type EXCL) for 12 ERK-PT-100000-LTLFireability-04
[[35mlola[0m][I] time limit : 513 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 13 (type EXCL) for ERK-PT-100000-LTLFireability-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 3
[[35mlola[0m][I] fired transitions : 2
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 ERK-PT-100000-LTLFireability-03
[[35mlola[0m][I] time limit : 599 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 10 (type EXCL) for ERK-PT-100000-LTLFireability-03
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 11
[[35mlola[0m][I] fired transitions : 12
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 4 (type EXCL) for 3 ERK-PT-100000-LTLFireability-01
[[35mlola[0m][I] time limit : 719 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 4 (type EXCL) for ERK-PT-100000-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 200003
[[35mlola[0m][I] fired transitions : 200003
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 2
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 ERK-PT-100000-LTLFireability-00
[[35mlola[0m][I] time limit : 899 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 1 (type EXCL) for ERK-PT-100000-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 300003
[[35mlola[0m][I] fired transitions : 300004
[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 3
[[35mlola[0m][I] LAUNCH task # 47 (type EXCL) for 46 ERK-PT-100000-LTLFireability-14
[[35mlola[0m][I] time limit : 1198 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 0/1198 1/2000 ERK-PT-100000-LTLFireability-14 130849 m, 26169 m/sec, 130848 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 7
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 5/1198 24/2000 ERK-PT-100000-LTLFireability-14 3564453 m, 686720 m/sec, 5198649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 24
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 10/1198 41/2000 ERK-PT-100000-LTLFireability-14 6079812 m, 503071 m/sec, 10834565 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 41
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 15/1198 57/2000 ERK-PT-100000-LTLFireability-14 8504265 m, 484890 m/sec, 16283372 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 57
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 20/1198 72/2000 ERK-PT-100000-LTLFireability-14 10810608 m, 461268 m/sec, 21495923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 72
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 25/1198 88/2000 ERK-PT-100000-LTLFireability-14 13144647 m, 466807 m/sec, 26749325 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 30/1198 103/2000 ERK-PT-100000-LTLFireability-14 15381330 m, 447336 m/sec, 31741171 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 35/1198 119/2000 ERK-PT-100000-LTLFireability-14 17840625 m, 491859 m/sec, 37289582 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 119
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 40/1198 135/2000 ERK-PT-100000-LTLFireability-14 20257285 m, 483332 m/sec, 42731444 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 45/1198 152/2000 ERK-PT-100000-LTLFireability-14 22737518 m, 496046 m/sec, 48332272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 152
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 50/1198 168/2000 ERK-PT-100000-LTLFireability-14 25103477 m, 473191 m/sec, 53647452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 168
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 55/1198 183/2000 ERK-PT-100000-LTLFireability-14 27441276 m, 467559 m/sec, 58892265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 183
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 60/1198 199/2000 ERK-PT-100000-LTLFireability-14 29758782 m, 463501 m/sec, 64089967 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 65/1198 216/2000 ERK-PT-100000-LTLFireability-14 32285805 m, 505404 m/sec, 69804332 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 70/1198 231/2000 ERK-PT-100000-LTLFireability-14 34626465 m, 468132 m/sec, 75056408 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 231
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 75/1198 247/2000 ERK-PT-100000-LTLFireability-14 36978354 m, 470377 m/sec, 80336593 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 247
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 80/1198 262/2000 ERK-PT-100000-LTLFireability-14 39229448 m, 450218 m/sec, 85429271 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 262
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 85/1198 278/2000 ERK-PT-100000-LTLFireability-14 41606046 m, 475319 m/sec, 90781872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 278
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 90/1198 293/2000 ERK-PT-100000-LTLFireability-14 43919647 m, 462720 m/sec, 95991329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 95/1198 310/2000 ERK-PT-100000-LTLFireability-14 46422383 m, 500547 m/sec, 101613243 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 100/1198 325/2000 ERK-PT-100000-LTLFireability-14 48699597 m, 455442 m/sec, 106742441 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 325
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 105/1198 341/2000 ERK-PT-100000-LTLFireability-14 51066240 m, 473328 m/sec, 112059720 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 341
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 110/1198 356/2000 ERK-PT-100000-LTLFireability-14 53273540 m, 441460 m/sec, 117013467 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 356
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 115/1198 370/2000 ERK-PT-100000-LTLFireability-14 55415830 m, 428458 m/sec, 121835020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 370
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 120/1198 385/2000 ERK-PT-100000-LTLFireability-14 57642262 m, 445286 m/sec, 126849404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 385
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 125/1198 400/2000 ERK-PT-100000-LTLFireability-14 59825199 m, 436587 m/sec, 131759890 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 130/1198 414/2000 ERK-PT-100000-LTLFireability-14 61952762 m, 425512 m/sec, 136568775 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 414
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 135/1198 428/2000 ERK-PT-100000-LTLFireability-14 64101126 m, 429672 m/sec, 141364724 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 428
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 140/1198 442/2000 ERK-PT-100000-LTLFireability-14 66200289 m, 419832 m/sec, 146099934 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 442
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 145/1198 456/2000 ERK-PT-100000-LTLFireability-14 68342013 m, 428344 m/sec, 150944693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 456
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 150/1198 472/2000 ERK-PT-100000-LTLFireability-14 70627467 m, 457090 m/sec, 156069624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 472
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 155/1198 488/2000 ERK-PT-100000-LTLFireability-14 73024584 m, 479423 m/sec, 161463419 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 488
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 160/1198 503/2000 ERK-PT-100000-LTLFireability-14 75262277 m, 447538 m/sec, 166482195 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 503
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-00: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-01: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-03: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-04: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-05: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-07: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-08: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-10: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-11: AG false findpath[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-12: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[32mERK-PT-100000-LTLFireability-13: LTL true LTL model checker[0m
[[35mlola[0m][.] [1m[31mERK-PT-100000-LTLFireability-15: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] ERK-PT-100000-LTLFireability-14: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 47 LTL EXCL 173/1198 516/2000 ERK-PT-100000-LTLFireability-14 77199294 m, 387403 m/sec, 170855283 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 178 secs. Pages in use: 516
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ERK-PT-100000"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is ERK-PT-100000, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r159-smll-171636267200068"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ERK-PT-100000.tgz
mv ERK-PT-100000 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;