MCC'2024- Execution of r137-tall-171631134700634

About the Execution of LoLA for DoubleLock-PT-p3s2

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.960	299190.00	901328.00	2234.90	?????T??????????	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134700634.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p3s2, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134700634
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 764K
-rw-r--r-- 1 mcc users 6.6K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 73K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.7K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.0K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 82K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 94K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 330K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-00
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-01
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-02
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-03
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-04
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-05
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-06
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-07
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-08
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-09
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-10
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2024-11
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2023-12
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2023-13
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2023-14
FORMULA_NAME DoubleLock-PT-p3s2-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717063062285

FORMULA DoubleLock-PT-p3s2-CTLFireability-2024-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717063361475

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 32 transitions removed,20 places removed
[[35mlola[0m][I] LAUNCH task # 16 (type CNST) for 15 DoubleLock-PT-p3s2-CTLFireability-2024-05
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 16 (type CNST) for DoubleLock-PT-p3s2-CTLFireability-2024-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p3s2-CTLFireability-2024-00
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 48 (type FNDP) for 21 DoubleLock-PT-p3s2-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type EQUN) for 21 DoubleLock-PT-p3s2-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s2-CTLFireability-2024-05: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 5/239 9/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 1748207 m, 349641 m/sec, 1888782 t fired, .
[[35mlola[0m][.] 48 EF FNDP 5/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 4256 attempts, .
[[35mlola[0m][.] 49 EF STEQ 5/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 sara not yet started (preprocessing).
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 10/239 19/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 3677503 m, 385859 m/sec, 3973217 t fired, .
[[35mlola[0m][.] 48 EF FNDP 10/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 9273 attempts, .
[[35mlola[0m][.] 49 EF STEQ 10/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 15/239 28/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 5441704 m, 352840 m/sec, 5879281 t fired, .
[[35mlola[0m][.] 48 EF FNDP 15/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 14489 attempts, .
[[35mlola[0m][.] 49 EF STEQ 15/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 CTL EXCL 20/239 38/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 7378757 m, 387410 m/sec, 7972096 t fired, .
[[35mlola[0m][.] 48 EF FNDP 20/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 19615 attempts, .
[[35mlola[0m][.] 49 EF STEQ 20/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 1 CTL EXCL 25/239 47/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 9328797 m, 390008 m/sec, 10078944 t fired, .
[[35mlola[0m][.] 48 EF FNDP 25/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 25125 attempts, .
[[35mlola[0m][.] 49 EF STEQ 25/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-00: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-07: EF 0 1 2 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 CTL EXCL 30/239 57/2000 DoubleLock-PT-p3s2-CTLFireability-2024-00 11155290 m, 365298 m/sec, 12052309 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 70/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 74058 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 110/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 118147 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 195/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 209297 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 215/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 230444 attempts, .
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[[35mlola[0m][.] 46 CTL EXCL 5/239 8/2000 DoubleLock-PT-p3s2-CTLFireability-2023-15 1470497 m, 294099 m/sec, 1588743 t fired, .
[[35mlola[0m][.] 48 EF FNDP 245/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 261878 attempts, .
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[[35mlola[0m][.] 46 CTL EXCL 10/239 18/2000 DoubleLock-PT-p3s2-CTLFireability-2023-15 3475394 m, 400979 m/sec, 3754858 t fired, .
[[35mlola[0m][.] 48 EF FNDP 250/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 267049 attempts, .
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[[35mlola[0m][.] 46 CTL EXCL 15/239 28/2000 DoubleLock-PT-p3s2-CTLFireability-2023-15 5433788 m, 391678 m/sec, 5870732 t fired, .
[[35mlola[0m][.] 48 EF FNDP 255/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 272241 attempts, .
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[[35mlola[0m][.] 46 CTL EXCL 20/239 38/2000 DoubleLock-PT-p3s2-CTLFireability-2023-15 7390317 m, 391305 m/sec, 7984589 t fired, .
[[35mlola[0m][.] 48 EF FNDP 260/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 277463 attempts, .
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[[35mlola[0m][.] 46 CTL EXCL 25/239 48/2000 DoubleLock-PT-p3s2-CTLFireability-2023-15 9354267 m, 392790 m/sec, 10106466 t fired, .
[[35mlola[0m][.] 48 EF FNDP 265/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 282657 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p3s2-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 270/3593 0/5 DoubleLock-PT-p3s2-CTLFireability-2024-07 287882 attempts, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p3s2"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p3s2, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134700634"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p3s2.tgz
mv DoubleLock-PT-p3s2 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;