About the Execution of LoLA for DoubleLock-PT-p3s1
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.436 | 405711.00 | 416070.00 | 1380.30 | ???????????????T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134700626.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p3s1, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134700626
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K Apr 22 14:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Apr 22 14:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 1.9K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 15K Apr 12 13:18 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 172K Apr 12 13:18 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:17 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 105K Apr 12 13:17 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 39K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-00
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-01
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-02
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-03
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-04
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-05
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-06
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-07
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-08
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-09
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-10
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2024-11
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2023-12
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2023-13
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2023-14
FORMULA_NAME DoubleLock-PT-p3s1-CTLFireability-2023-15
=== Now, execution of the tool begins
BK_START 1717062132163
FORMULA DoubleLock-PT-p3s1-CTLFireability-2023-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717062537874
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 4 transitions removed,6 places removed
[[35mlola[0m][I] LAUNCH task # 50 (type CNST) for 49 DoubleLock-PT-p3s1-CTLFireability-2023-15
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 50 (type CNST) for DoubleLock-PT-p3s1-CTLFireability-2023-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 DoubleLock-PT-p3s1-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 150 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 56 (type EQUN) for 21 DoubleLock-PT-p3s1-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 58 (type EQUN) for 21 DoubleLock-PT-p3s1-CTLFireability-2024-07
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 62 (type EQUN) for 36 DoubleLock-PT-p3s1-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 58 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 43 DoubleLock-PT-p3s1-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 62 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 36 DoubleLock-PT-p3s1-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 56 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2024-07
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 43 DoubleLock-PT-p3s1-CTLFireability-2023-13
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 64 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2023-12
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 68 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 70 (type EQUN) for DoubleLock-PT-p3s1-CTLFireability-2023-13
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 5/225 6/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 1420296 m, 284059 m/sec, 6250279 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 6
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 10/225 12/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 2767034 m, 269347 m/sec, 12176818 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 12
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 15/225 18/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 4097774 m, 266148 m/sec, 18033011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 18
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 20/225 23/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 5394580 m, 259361 m/sec, 23739879 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 25/225 29/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 6683284 m, 257740 m/sec, 29411176 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 29
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 30/225 34/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 7971951 m, 257733 m/sec, 35082165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 34
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 35/225 39/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 9240470 m, 253703 m/sec, 40664534 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 39
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 40/225 44/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 10492012 m, 250308 m/sec, 46172248 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 45/225 50/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 11755137 m, 252625 m/sec, 51730880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 50
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 50/225 55/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 12996265 m, 248225 m/sec, 57192738 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 55
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 55/225 60/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 14234011 m, 247549 m/sec, 62639700 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 60
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 60/225 65/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 15466952 m, 246588 m/sec, 68065513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 65
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 65/225 71/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 16697090 m, 246027 m/sec, 73479054 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 70/225 76/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 17910281 m, 242638 m/sec, 78817894 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 75/225 81/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 19103820 m, 238707 m/sec, 84070329 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 81
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 80/225 86/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 20294697 m, 238175 m/sec, 89311048 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 85/225 91/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 21503872 m, 241835 m/sec, 94632258 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 91
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 90/225 96/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 22704568 m, 240139 m/sec, 99916193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 96
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 95/225 101/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 23890103 m, 237107 m/sec, 105133449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 101
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 100/225 106/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 25079450 m, 237869 m/sec, 110367375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 106
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 105/225 111/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 26259222 m, 235954 m/sec, 115559280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 110/225 115/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 27419325 m, 232020 m/sec, 120664478 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 115
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 115/225 121/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 28623575 m, 240850 m/sec, 125964045 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 120/225 126/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 29824956 m, 240276 m/sec, 131250991 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 125/225 130/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 31006417 m, 236292 m/sec, 136450234 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 130/225 136/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 32202145 m, 239145 m/sec, 141712299 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 135/225 140/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 33374830 m, 234537 m/sec, 146872976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 140
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 140/225 145/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 34531789 m, 231391 m/sec, 151964395 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 145
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 145/225 150/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 35703618 m, 234365 m/sec, 157121334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 150
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 150/225 155/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 36852180 m, 229712 m/sec, 162175759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 155
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 155/225 160/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 38004244 m, 230412 m/sec, 167245688 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 160
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 160/225 165/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 39176764 m, 234504 m/sec, 172405598 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 165
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 165/225 170/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 40340986 m, 232844 m/sec, 177529050 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 170
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 170/225 174/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 41501004 m, 232003 m/sec, 182633916 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 175/225 179/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 42687047 m, 237208 m/sec, 187853344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 179
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 180/225 184/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 43860047 m, 234600 m/sec, 193015388 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 185/225 189/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 45029857 m, 233962 m/sec, 198163378 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 190/225 194/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 46196131 m, 233254 m/sec, 203295839 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 194
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 195/225 199/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 47352084 m, 231190 m/sec, 208382834 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 200/225 204/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 48516872 m, 232957 m/sec, 213508732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 204
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 205/225 209/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 49671115 m, 230848 m/sec, 218588247 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 209
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 210/225 214/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 50828011 m, 231379 m/sec, 223679404 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 214
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 215/225 218/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 51985502 m, 231498 m/sec, 228773211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 218
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 220/225 223/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 53144501 m, 231799 m/sec, 233873619 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 10 CTL EXCL 225/225 228/2000 DoubleLock-PT-p3s1-CTLFireability-2024-03 54291637 m, 229427 m/sec, 238921838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 228
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 10 (type EXCL) for DoubleLock-PT-p3s1-CTLFireability-2024-03 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 2 0 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 39 (type EXCL) for 36 DoubleLock-PT-p3s1-CTLFireability-2023-12
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 10 (type EXCL) for 9 DoubleLock-PT-p3s1-CTLFireability-2024-03
[[35mlola[0m][I] time limit : 3370 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 10 (type EXCL) for DoubleLock-PT-p3s1-CTLFireability-2024-03 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 5/224 15/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 3609264 m, 721852 m/sec, 4484230 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 10/224 30/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 7201200 m, 718387 m/sec, 8946940 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 15/224 45/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 10724221 m, 704604 m/sec, 13324026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 20/224 59/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 14231624 m, 701480 m/sec, 17681708 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 25/224 73/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 17702100 m, 694095 m/sec, 21993513 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 30/224 87/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 21146028 m, 688785 m/sec, 26272333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 35/224 101/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 24571838 m, 685162 m/sec, 30528641 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 40/224 115/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 27986932 m, 683018 m/sec, 34771636 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 45/224 129/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 31389738 m, 680561 m/sec, 38999366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 50/224 143/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 34778584 m, 677769 m/sec, 43209750 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 55/224 157/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 38179985 m, 680280 m/sec, 47435734 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 60/224 171/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 41549052 m, 673813 m/sec, 51621544 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 65/224 185/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 44922308 m, 674651 m/sec, 55812558 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 70/224 199/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 48267659 m, 669070 m/sec, 59968904 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 300 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 75/224 212/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 51587691 m, 664006 m/sec, 64093792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 305 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 80/224 226/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 54948997 m, 672261 m/sec, 68269960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 310 secs. Pages in use: 233
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 85/224 240/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 58263214 m, 662843 m/sec, 72387624 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 315 secs. Pages in use: 240
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 90/224 253/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 61549136 m, 657184 m/sec, 76470133 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 320 secs. Pages in use: 253
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 95/224 266/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 64808634 m, 651899 m/sec, 80519812 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 325 secs. Pages in use: 266
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 100/224 280/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 68076876 m, 653648 m/sec, 84580355 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 330 secs. Pages in use: 280
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 105/224 293/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 71361436 m, 656912 m/sec, 88661173 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 335 secs. Pages in use: 293
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 110/224 307/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 74620344 m, 651781 m/sec, 92710119 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 340 secs. Pages in use: 307
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 115/224 320/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 77870968 m, 650124 m/sec, 96748773 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 345 secs. Pages in use: 320
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 120/224 333/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 81145040 m, 654814 m/sec, 100816559 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 350 secs. Pages in use: 333
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 125/224 347/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 84399946 m, 650981 m/sec, 104860532 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 355 secs. Pages in use: 347
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 130/224 360/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 87670323 m, 654075 m/sec, 108923729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 360 secs. Pages in use: 360
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 135/224 374/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 90895243 m, 644984 m/sec, 112930448 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 365 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 140/224 387/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 94121851 m, 645321 m/sec, 116939264 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 370 secs. Pages in use: 387
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 145/224 400/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 97339034 m, 643436 m/sec, 120936370 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 375 secs. Pages in use: 400
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 150/224 413/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 100562368 m, 644666 m/sec, 124941117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 380 secs. Pages in use: 413
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 155/224 426/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 103775317 m, 642589 m/sec, 128932964 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 385 secs. Pages in use: 426
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 160/224 440/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 107034873 m, 651911 m/sec, 132982715 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 390 secs. Pages in use: 440
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 165/224 453/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 110276465 m, 648318 m/sec, 137010147 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 395 secs. Pages in use: 453
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p3s1-CTLFireability-2023-15: INITIAL true preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-03: CTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-07: EFAG 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-10: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-12: DISJ 0 1 1 0 4 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-13: AGEF 0 1 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p3s1-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 39 CTL EXCL 170/224 466/2000 DoubleLock-PT-p3s1-CTLFireability-2023-12 113522237 m, 649154 m/sec, 141042774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 400 secs. Pages in use: 466
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 409 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p3s1"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p3s1, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134700626"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p3s1.tgz
mv DoubleLock-PT-p3s1 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;