MCC'2024- Execution of r137-tall-171631134600620

About the Execution of LoLA for DoubleLock-PT-p2s2

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16205.920	309511.00	896636.00	1948.20	??????F???????F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600620.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p2s2, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600620
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.2M
-rw-r--r-- 1 mcc users 8.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 100K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.9K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 55K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.2K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.7K Apr 12 13:10 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 76K Apr 12 13:10 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.0K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 813K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-00
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-01
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-02
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-03
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-04
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-05
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-06
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-07
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-08
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-09
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-10
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-11
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-12
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-13
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-14
FORMULA_NAME DoubleLock-PT-p2s2-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717061812143

FORMULA DoubleLock-PT-p2s2-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s2-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717062121654

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 29 (type CNST) for 26 DoubleLock-PT-p2s2-LTLFireability-06
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 29 (type CNST) for DoubleLock-PT-p2s2-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 64 transitions removed,36 places removed
[*** LOG ERROR #0001 ***] [2024-05-30 09:36:52] [status_logger] string pointer is null
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p2s2-LTLFireability-11
[[35mlola[0m][I] time limit : 199 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 54 DoubleLock-PT-p2s2-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 54 DoubleLock-PT-p2s2-LTLFireability-14
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 69 (type FNDP) for 19 DoubleLock-PT-p2s2-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for DoubleLock-PT-p2s2-LTLFireability-14
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for DoubleLock-PT-p2s2-LTLFireability-14 (obsolete)
[[35mlola[0m][I] LAUNCH task # 70 (type EQUN) for 19 DoubleLock-PT-p2s2-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for DoubleLock-PT-p2s2-LTLFireability-14
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 3/224 9/2000 DoubleLock-PT-p2s2-LTLFireability-11 1037945 m, 207589 m/sec, 1167675 t fired, .
[[35mlola[0m][.] 69 EF FNDP 3/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 846 attempts, .
[[35mlola[0m][.] 70 EF STEQ 3/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 9
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 8/224 22/2000 DoubleLock-PT-p2s2-LTLFireability-11 2597289 m, 311868 m/sec, 2921937 t fired, .
[[35mlola[0m][.] 69 EF FNDP 8/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 2186 attempts, .
[[35mlola[0m][.] 70 EF STEQ 8/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 13/224 35/2000 DoubleLock-PT-p2s2-LTLFireability-11 4139717 m, 308485 m/sec, 4657168 t fired, .
[[35mlola[0m][.] 69 EF FNDP 13/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 3587 attempts, .
[[35mlola[0m][.] 70 EF STEQ 13/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 18/224 48/2000 DoubleLock-PT-p2s2-LTLFireability-11 5682931 m, 308642 m/sec, 6393284 t fired, .
[[35mlola[0m][.] 69 EF FNDP 18/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 5032 attempts, .
[[35mlola[0m][.] 70 EF STEQ 18/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 48
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 23/224 61/2000 DoubleLock-PT-p2s2-LTLFireability-11 7214479 m, 306309 m/sec, 8116275 t fired, .
[[35mlola[0m][.] 69 EF FNDP 23/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 6488 attempts, .
[[35mlola[0m][.] 70 EF STEQ 23/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 61
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 28/224 73/2000 DoubleLock-PT-p2s2-LTLFireability-11 8746257 m, 306355 m/sec, 9839527 t fired, .
[[35mlola[0m][.] 69 EF FNDP 28/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 7987 attempts, .
[[35mlola[0m][.] 70 EF STEQ 28/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 73
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 33/224 86/2000 DoubleLock-PT-p2s2-LTLFireability-11 10284366 m, 307621 m/sec, 11569898 t fired, .
[[35mlola[0m][.] 69 EF FNDP 33/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 9505 attempts, .
[[35mlola[0m][.] 70 EF STEQ 33/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 86
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 38/224 99/2000 DoubleLock-PT-p2s2-LTLFireability-11 11813212 m, 305769 m/sec, 13289850 t fired, .
[[35mlola[0m][.] 69 EF FNDP 38/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 11057 attempts, .
[[35mlola[0m][.] 70 EF STEQ 38/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 99
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 43/224 111/2000 DoubleLock-PT-p2s2-LTLFireability-11 13296438 m, 296645 m/sec, 14958480 t fired, .
[[35mlola[0m][.] 69 EF FNDP 43/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 12562 attempts, .
[[35mlola[0m][.] 70 EF STEQ 43/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 111
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 48/224 124/2000 DoubleLock-PT-p2s2-LTLFireability-11 14776993 m, 296111 m/sec, 16624105 t fired, .
[[35mlola[0m][.] 69 EF FNDP 48/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 14083 attempts, .
[[35mlola[0m][.] 70 EF STEQ 48/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 124
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 53/224 136/2000 DoubleLock-PT-p2s2-LTLFireability-11 16277469 m, 300095 m/sec, 18312139 t fired, .
[[35mlola[0m][.] 69 EF FNDP 53/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 15637 attempts, .
[[35mlola[0m][.] 70 EF STEQ 53/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 136
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 58/224 149/2000 DoubleLock-PT-p2s2-LTLFireability-11 17783924 m, 301291 m/sec, 20006902 t fired, .
[[35mlola[0m][.] 69 EF FNDP 58/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 17198 attempts, .
[[35mlola[0m][.] 70 EF STEQ 58/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 149
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 63/224 161/2000 DoubleLock-PT-p2s2-LTLFireability-11 19288302 m, 300875 m/sec, 21699326 t fired, .
[[35mlola[0m][.] 69 EF FNDP 63/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 18752 attempts, .
[[35mlola[0m][.] 70 EF STEQ 63/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 161
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 68/224 174/2000 DoubleLock-PT-p2s2-LTLFireability-11 20782245 m, 298788 m/sec, 23380013 t fired, .
[[35mlola[0m][.] 69 EF FNDP 68/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 20336 attempts, .
[[35mlola[0m][.] 70 EF STEQ 68/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 174
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 73/224 186/2000 DoubleLock-PT-p2s2-LTLFireability-11 22287348 m, 301020 m/sec, 25073254 t fired, .
[[35mlola[0m][.] 69 EF FNDP 73/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 21903 attempts, .
[[35mlola[0m][.] 70 EF STEQ 73/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 186
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 78/224 199/2000 DoubleLock-PT-p2s2-LTLFireability-11 23771842 m, 296898 m/sec, 26743310 t fired, .
[[35mlola[0m][.] 69 EF FNDP 78/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 23460 attempts, .
[[35mlola[0m][.] 70 EF STEQ 78/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 199
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 83/224 211/2000 DoubleLock-PT-p2s2-LTLFireability-11 25246848 m, 295001 m/sec, 28402692 t fired, .
[[35mlola[0m][.] 69 EF FNDP 83/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 25047 attempts, .
[[35mlola[0m][.] 70 EF STEQ 83/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 211
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 88/224 223/2000 DoubleLock-PT-p2s2-LTLFireability-11 26720656 m, 294761 m/sec, 30060726 t fired, .
[[35mlola[0m][.] 69 EF FNDP 88/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 26601 attempts, .
[[35mlola[0m][.] 70 EF STEQ 88/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 223
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 93/224 236/2000 DoubleLock-PT-p2s2-LTLFireability-11 28217351 m, 299339 m/sec, 31744506 t fired, .
[[35mlola[0m][.] 69 EF FNDP 93/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 28171 attempts, .
[[35mlola[0m][.] 70 EF STEQ 93/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 236
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 98/224 248/2000 DoubleLock-PT-p2s2-LTLFireability-11 29695126 m, 295555 m/sec, 33407004 t fired, .
[[35mlola[0m][.] 69 EF FNDP 98/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 29747 attempts, .
[[35mlola[0m][.] 70 EF STEQ 98/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 248
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 103/224 261/2000 DoubleLock-PT-p2s2-LTLFireability-11 31165849 m, 294144 m/sec, 35061566 t fired, .
[[35mlola[0m][.] 69 EF FNDP 103/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 31311 attempts, .
[[35mlola[0m][.] 70 EF STEQ 103/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 261
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 108/224 273/2000 DoubleLock-PT-p2s2-LTLFireability-11 32632447 m, 293319 m/sec, 36711490 t fired, .
[[35mlola[0m][.] 69 EF FNDP 108/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 32866 attempts, .
[[35mlola[0m][.] 70 EF STEQ 108/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 273
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 113/224 285/2000 DoubleLock-PT-p2s2-LTLFireability-11 34098215 m, 293153 m/sec, 38360478 t fired, .
[[35mlola[0m][.] 69 EF FNDP 113/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 34410 attempts, .
[[35mlola[0m][.] 70 EF STEQ 113/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 118/224 298/2000 DoubleLock-PT-p2s2-LTLFireability-11 35599712 m, 300299 m/sec, 40049662 t fired, .
[[35mlola[0m][.] 69 EF FNDP 118/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 35998 attempts, .
[[35mlola[0m][.] 70 EF STEQ 118/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 298
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 123/224 310/2000 DoubleLock-PT-p2s2-LTLFireability-11 37119826 m, 304022 m/sec, 41759792 t fired, .
[[35mlola[0m][.] 69 EF FNDP 123/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 37601 attempts, .
[[35mlola[0m][.] 70 EF STEQ 123/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 310
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 128/224 323/2000 DoubleLock-PT-p2s2-LTLFireability-11 38640375 m, 304109 m/sec, 43470409 t fired, .
[[35mlola[0m][.] 69 EF FNDP 128/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 39222 attempts, .
[[35mlola[0m][.] 70 EF STEQ 128/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 323
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 133/224 336/2000 DoubleLock-PT-p2s2-LTLFireability-11 40156643 m, 303253 m/sec, 45176211 t fired, .
[[35mlola[0m][.] 69 EF FNDP 133/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 40813 attempts, .
[[35mlola[0m][.] 70 EF STEQ 133/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 336
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 138/224 348/2000 DoubleLock-PT-p2s2-LTLFireability-11 41666009 m, 301873 m/sec, 46874246 t fired, .
[[35mlola[0m][.] 69 EF FNDP 138/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 42423 attempts, .
[[35mlola[0m][.] 70 EF STEQ 138/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 348
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 143/224 361/2000 DoubleLock-PT-p2s2-LTLFireability-11 43183884 m, 303575 m/sec, 48581856 t fired, .
[[35mlola[0m][.] 69 EF FNDP 143/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 44016 attempts, .
[[35mlola[0m][.] 70 EF STEQ 143/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 361
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 148/224 374/2000 DoubleLock-PT-p2s2-LTLFireability-11 44699423 m, 303107 m/sec, 50286836 t fired, .
[[35mlola[0m][.] 69 EF FNDP 148/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 45623 attempts, .
[[35mlola[0m][.] 70 EF STEQ 148/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 374
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 153/224 386/2000 DoubleLock-PT-p2s2-LTLFireability-11 46186070 m, 297329 m/sec, 51959316 t fired, .
[[35mlola[0m][.] 69 EF FNDP 153/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 47208 attempts, .
[[35mlola[0m][.] 70 EF STEQ 153/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 386
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 158/224 398/2000 DoubleLock-PT-p2s2-LTLFireability-11 47675138 m, 297813 m/sec, 53634517 t fired, .
[[35mlola[0m][.] 69 EF FNDP 158/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 48778 attempts, .
[[35mlola[0m][.] 70 EF STEQ 158/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 398
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 163/224 411/2000 DoubleLock-PT-p2s2-LTLFireability-11 49163132 m, 297598 m/sec, 55308510 t fired, .
[[35mlola[0m][.] 69 EF FNDP 163/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 50362 attempts, .
[[35mlola[0m][.] 70 EF STEQ 163/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 411
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 168/224 423/2000 DoubleLock-PT-p2s2-LTLFireability-11 50648069 m, 296987 m/sec, 56979064 t fired, .
[[35mlola[0m][.] 69 EF FNDP 168/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 51928 attempts, .
[[35mlola[0m][.] 70 EF STEQ 168/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 170 secs. Pages in use: 423
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 173/224 436/2000 DoubleLock-PT-p2s2-LTLFireability-11 52160250 m, 302436 m/sec, 58680267 t fired, .
[[35mlola[0m][.] 69 EF FNDP 173/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 53499 attempts, .
[[35mlola[0m][.] 70 EF STEQ 173/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 175 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 178/224 448/2000 DoubleLock-PT-p2s2-LTLFireability-11 53672300 m, 302410 m/sec, 60381323 t fired, .
[[35mlola[0m][.] 69 EF FNDP 178/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 55087 attempts, .
[[35mlola[0m][.] 70 EF STEQ 178/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 180 secs. Pages in use: 448
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 183/224 461/2000 DoubleLock-PT-p2s2-LTLFireability-11 55175520 m, 300644 m/sec, 62072447 t fired, .
[[35mlola[0m][.] 69 EF FNDP 183/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 56655 attempts, .
[[35mlola[0m][.] 70 EF STEQ 183/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 185 secs. Pages in use: 461
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 188/224 473/2000 DoubleLock-PT-p2s2-LTLFireability-11 56677661 m, 300428 m/sec, 63762355 t fired, .
[[35mlola[0m][.] 69 EF FNDP 188/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 58247 attempts, .
[[35mlola[0m][.] 70 EF STEQ 188/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 190 secs. Pages in use: 473
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 193/224 486/2000 DoubleLock-PT-p2s2-LTLFireability-11 58180860 m, 300639 m/sec, 65453454 t fired, .
[[35mlola[0m][.] 69 EF FNDP 193/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 59835 attempts, .
[[35mlola[0m][.] 70 EF STEQ 193/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 195 secs. Pages in use: 486
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 198/224 499/2000 DoubleLock-PT-p2s2-LTLFireability-11 59688412 m, 301510 m/sec, 67149449 t fired, .
[[35mlola[0m][.] 69 EF FNDP 198/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 61420 attempts, .
[[35mlola[0m][.] 70 EF STEQ 198/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 200 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 203/224 511/2000 DoubleLock-PT-p2s2-LTLFireability-11 61196336 m, 301584 m/sec, 68845866 t fired, .
[[35mlola[0m][.] 69 EF FNDP 203/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 62996 attempts, .
[[35mlola[0m][.] 70 EF STEQ 203/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 205 secs. Pages in use: 511
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 208/224 524/2000 DoubleLock-PT-p2s2-LTLFireability-11 62697509 m, 300234 m/sec, 70534684 t fired, .
[[35mlola[0m][.] 69 EF FNDP 208/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 64589 attempts, .
[[35mlola[0m][.] 70 EF STEQ 208/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 210 secs. Pages in use: 524
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 213/224 536/2000 DoubleLock-PT-p2s2-LTLFireability-11 64200266 m, 300551 m/sec, 72225286 t fired, .
[[35mlola[0m][.] 69 EF FNDP 213/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 66158 attempts, .
[[35mlola[0m][.] 70 EF STEQ 213/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 215 secs. Pages in use: 536
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 218/224 549/2000 DoubleLock-PT-p2s2-LTLFireability-11 65703731 m, 300693 m/sec, 73916685 t fired, .
[[35mlola[0m][.] 69 EF FNDP 218/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 67746 attempts, .
[[35mlola[0m][.] 70 EF STEQ 218/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 220 secs. Pages in use: 549
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 223/224 561/2000 DoubleLock-PT-p2s2-LTLFireability-11 67195214 m, 298296 m/sec, 75594601 t fired, .
[[35mlola[0m][.] 69 EF FNDP 223/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 69312 attempts, .
[[35mlola[0m][.] 70 EF STEQ 223/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 225 secs. Pages in use: 561
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 46 (type EXCL) for DoubleLock-PT-p2s2-LTLFireability-11 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 69 EF FNDP 228/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 70893 attempts, .
[[35mlola[0m][.] 70 EF STEQ 228/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 230 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 62 (type EXCL) for 61 DoubleLock-PT-p2s2-LTLFireability-15
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p2s2-LTLFireability-11
[[35mlola[0m][I] time limit : 3370 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] CANCELED task # 46 (type EXCL) for DoubleLock-PT-p2s2-LTLFireability-11 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 5/224 14/2000 DoubleLock-PT-p2s2-LTLFireability-15 1629058 m, 325811 m/sec, 1737654 t fired, .
[[35mlola[0m][.] 69 EF FNDP 233/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 72416 attempts, .
[[35mlola[0m][.] 70 EF STEQ 233/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 235 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 10/224 27/2000 DoubleLock-PT-p2s2-LTLFireability-15 3186647 m, 311517 m/sec, 3399082 t fired, .
[[35mlola[0m][.] 69 EF FNDP 238/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 73900 attempts, .
[[35mlola[0m][.] 70 EF STEQ 238/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 240 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 15/224 41/2000 DoubleLock-PT-p2s2-LTLFireability-15 4742065 m, 311083 m/sec, 5058196 t fired, .
[[35mlola[0m][.] 69 EF FNDP 243/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 75354 attempts, .
[[35mlola[0m][.] 70 EF STEQ 243/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 245 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 20/224 54/2000 DoubleLock-PT-p2s2-LTLFireability-15 6319626 m, 315512 m/sec, 6740928 t fired, .
[[35mlola[0m][.] 69 EF FNDP 248/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 76870 attempts, .
[[35mlola[0m][.] 70 EF STEQ 248/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 250 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 25/224 68/2000 DoubleLock-PT-p2s2-LTLFireability-15 7937064 m, 323487 m/sec, 8466195 t fired, .
[[35mlola[0m][.] 69 EF FNDP 253/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 78410 attempts, .
[[35mlola[0m][.] 70 EF STEQ 253/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 255 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 30/224 81/2000 DoubleLock-PT-p2s2-LTLFireability-15 9510482 m, 314683 m/sec, 10144507 t fired, .
[[35mlola[0m][.] 69 EF FNDP 258/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 79920 attempts, .
[[35mlola[0m][.] 70 EF STEQ 258/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 260 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 35/224 94/2000 DoubleLock-PT-p2s2-LTLFireability-15 11049280 m, 307759 m/sec, 11785892 t fired, .
[[35mlola[0m][.] 69 EF FNDP 263/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 81427 attempts, .
[[35mlola[0m][.] 70 EF STEQ 263/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 265 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 40/224 107/2000 DoubleLock-PT-p2s2-LTLFireability-15 12634701 m, 317084 m/sec, 13477008 t fired, .
[[35mlola[0m][.] 69 EF FNDP 268/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 82955 attempts, .
[[35mlola[0m][.] 70 EF STEQ 268/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 270 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 45/224 121/2000 DoubleLock-PT-p2s2-LTLFireability-15 14232981 m, 319656 m/sec, 15181839 t fired, .
[[35mlola[0m][.] 69 EF FNDP 273/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 84491 attempts, .
[[35mlola[0m][.] 70 EF STEQ 273/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 275 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 50/224 134/2000 DoubleLock-PT-p2s2-LTLFireability-15 15820334 m, 317470 m/sec, 16875015 t fired, .
[[35mlola[0m][.] 69 EF FNDP 278/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 86032 attempts, .
[[35mlola[0m][.] 70 EF STEQ 278/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 280 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 55/224 148/2000 DoubleLock-PT-p2s2-LTLFireability-15 17428117 m, 321556 m/sec, 18589984 t fired, .
[[35mlola[0m][.] 69 EF FNDP 283/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 87574 attempts, .
[[35mlola[0m][.] 70 EF STEQ 283/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 285 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 60/224 162/2000 DoubleLock-PT-p2s2-LTLFireability-15 19027726 m, 319921 m/sec, 20296233 t fired, .
[[35mlola[0m][.] 69 EF FNDP 288/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 89115 attempts, .
[[35mlola[0m][.] 70 EF STEQ 288/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 290 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 65/224 173/2000 DoubleLock-PT-p2s2-LTLFireability-15 20338698 m, 262194 m/sec, 21694603 t fired, .
[[35mlola[0m][.] 69 EF FNDP 293/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 90400 attempts, .
[[35mlola[0m][.] 70 EF STEQ 293/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 295 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-06: CONJ false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s2-LTLFireability-14: CONJ false findpath[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-03: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-05: CONJ 0 2 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-10: LTL/CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-11: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s2-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 62 LTL EXCL 72/224 176/2000 DoubleLock-PT-p2s2-LTLFireability-15 20672743 m, 66809 m/sec, 22050918 t fired, .
[[35mlola[0m][.] 69 EF FNDP 300/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 90709 attempts, .
[[35mlola[0m][.] 70 EF STEQ 300/3598 0/5 DoubleLock-PT-p2s2-LTLFireability-05 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 302 secs. Pages in use: 574
[[35mlola[0m][.] # running tasks: 3 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 419 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p2s2"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p2s2, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600620"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p2s2.tgz
mv DoubleLock-PT-p2s2 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;