MCC'2024- Execution of r137-tall-171631134600612

About the Execution of LoLA for DoubleLock-PT-p2s1

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16207.460	419968.00	425445.00	1639.30	?F?F?FF???FF??F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600612.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p2s1, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600612
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 480K
-rw-r--r-- 1 mcc users 5.4K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 57K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 19 15:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Apr 22 14:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Apr 22 14:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.9K Apr 12 13:38 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 98K Apr 12 13:38 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.9K Apr 12 13:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 68K Apr 12 13:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 97K May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-00
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-01
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-02
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-03
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-04
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-05
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-06
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-07
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-08
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-09
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-10
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-11
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-12
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-13
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-14
FORMULA_NAME DoubleLock-PT-p2s1-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717059988159

FORMULA DoubleLock-PT-p2s1-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p2s1-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717060408127

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 8 transitions removed,8 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 DoubleLock-PT-p2s1-LTLFireability-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 67 (type EXCL) for 27 DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] time limit : 120 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 65 (type FNDP) for 27 DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 66 (type EQUN) for 27 DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for DoubleLock-PT-p2s1-LTLFireability-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 72 (type EQUN) for 49 DoubleLock-PT-p2s1-LTLFireability-11
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 67 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 65 (type FNDP) for DoubleLock-PT-p2s1-LTLFireability-05 (obsolete)
[[35mlola[0m][W] CANCELED task # 66 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-05 (obsolete)
[[35mlola[0m][I] LAUNCH task # 59 (type EXCL) for 58 DoubleLock-PT-p2s1-LTLFireability-14
[[35mlola[0m][I] time limit : 128 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 59 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 52
[[35mlola[0m][I] fired transitions : 53
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 45 (type EXCL) for 42 DoubleLock-PT-p2s1-LTLFireability-10
[[35mlola[0m][I] time limit : 138 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 45 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-10
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DoubleLock-PT-p2s1-LTLFireability-06
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 31 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-06
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 69 (type EXCL) for 49 DoubleLock-PT-p2s1-LTLFireability-11
[[35mlola[0m][I] time limit : 189 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 65 (type FNDP) for DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 1
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 0
[[35mlola[0m][I] LAUNCH task # 77 (type EQUN) for 9 DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 66 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-05
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 82 (type EQUN) for 9 DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 69 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 57
[[35mlola[0m][I] fired transitions : 57
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 72 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-11 (obsolete)
[[35mlola[0m][I] LAUNCH task # 74 (type EXCL) for 9 DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] time limit : 257 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 74 (type EXCL) for DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 44
[[35mlola[0m][I] fired transitions : 44
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 77 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-03 (obsolete)
[[35mlola[0m][W] CANCELED task # 82 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p2s1-LTLFireability-00
[[35mlola[0m][I] time limit : 360 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 77 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 82 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 72 (type EQUN) for DoubleLock-PT-p2s1-LTLFireability-11
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 5/400 8/2000 DoubleLock-PT-p2s1-LTLFireability-00 1135956 m, 227191 m/sec, 1304240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 10/400 15/2000 DoubleLock-PT-p2s1-LTLFireability-00 2298043 m, 232417 m/sec, 2638488 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 15
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-01: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-11: F false state space / EG[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-14: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p2s1-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 15/400 23/2000 DoubleLock-PT-p2s1-LTLFireability-00 3453026 m, 230996 m/sec, 3964581 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
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[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-05: AG false state space[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-06: LTL false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-10: CONJ false LTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p2s1-LTLFireability-11: F false state space / EG[0m
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[[35mlola[0m][.]
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 408 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p2s1"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p2s1, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600612"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p2s1.tgz
mv DoubleLock-PT-p2s1 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;