About the Execution of LoLA for DoubleLock-PT-p1s3
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4528.995 | 3600000.00 | 10790708.00 | 10909.10 | FFFTFFTTTT?TFTFF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600606.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p1s3, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600606
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.0K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 19 15:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Apr 12 13:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 3.4M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-00
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-01
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-02
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-03
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-05
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-06
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-07
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-09
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-11
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-12
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-13
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-14
FORMULA_NAME DoubleLock-PT-p1s3-ReachabilityCardinality-2024-15
=== Now, execution of the tool begins
BK_START 1717059352138
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mReachabilityCardinality.xml[0m
[[35mlola[0m][I] Rule S: 256 transitions removed,132 places removed
[[35mlola[0m][I] LAUNCH task # 4 (type CNST) for 3 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-01
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 10 (type CNST) for 9 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-03
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 4 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-01
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 10 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 37 (type CNST) for 36 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-12
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 37 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-12
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 34 (type CNST) for 33 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-11
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[[35mlola[0m][I] FINISHED task # 34 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-00
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 1 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 19 (type CNST) for 18 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-06
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] FINISHED task # 19 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-06
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 16 (type CNST) for 15 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-05
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[[35mlola[0m][I] FINISHED task # 16 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-05
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 22 (type CNST) for 21 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-07
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] LAUNCH task # 28 (type CNST) for 27 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-09
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] LAUNCH task # 40 (type CNST) for 39 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-13
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[[35mlola[0m][I] FINISHED task # 28 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-09
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 40 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-13
[[35mlola[0m][I] result : true
[[35mlola[0m][I] FINISHED task # 22 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-07
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 43 (type CNST) for 42 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-14
[[35mlola[0m][I] time limit : 0 sec
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[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-02
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[[35mlola[0m][I] FINISHED task # 7 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] FINISHED task # 43 (type CNST) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-14
[[35mlola[0m][I] result : false
[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 30 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 874 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 48 (type FNDP) for 30 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 49 (type EQUN) for 30 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 52 (type FNDP) for 45 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-15
[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][I] FINISHED task # 52 (type FNDP) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-15
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 3
[[35mlola[0m][I] time used : 0
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[[35mlola[0m][I] LAUNCH task # 59 (type FNDP) for 12 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10: EF 0 0 3 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 EF FNDP 2/1748 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 23 attempts, .
[[35mlola[0m][.] 49 EF STEQ 2/1748 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 2/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5556 m, 1111 m/sec, 5557 t fired, .
[[35mlola[0m][.] 59 EF FNDP 1/1748 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 24 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10: EF 0 0 3 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 48 EF FNDP 7/1747 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 127 attempts, .
[[35mlola[0m][.] 49 EF STEQ 7/1747 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 7/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 31757 m, 5240 m/sec, 31757 t fired, .
[[35mlola[0m][.] 59 EF FNDP 6/1747 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 157 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-ReachabilityCardinality-2024-15: AG false findpath[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10: EF 0 0 3 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 48 EF FNDP 12/1742 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 251 attempts, .
[[35mlola[0m][.] 49 EF STEQ 12/1742 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 12/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 62741 m, 6196 m/sec, 62741 t fired, .
[[35mlola[0m][.] 59 EF FNDP 11/1742 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 304 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10: EF 0 0 3 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 17/1737 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 373 attempts, .
[[35mlola[0m][.] 49 EF STEQ 17/1737 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 17/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 93312 m, 6114 m/sec, 93312 t fired, .
[[35mlola[0m][.] 59 EF FNDP 16/1737 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 433 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 22/1732 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 491 attempts, .
[[35mlola[0m][.] 49 EF STEQ 22/1732 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 22/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 124441 m, 6225 m/sec, 124441 t fired, .
[[35mlola[0m][.] 59 EF FNDP 21/1732 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 573 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 27/1727 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 627 attempts, .
[[35mlola[0m][.] 49 EF STEQ 27/1727 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 27/1166 1/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 155252 m, 6162 m/sec, 155252 t fired, .
[[35mlola[0m][.] 59 EF FNDP 26/1727 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 709 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 32/1722 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 766 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 32/1166 2/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 186276 m, 6204 m/sec, 186276 t fired, .
[[35mlola[0m][.] 59 EF FNDP 31/1722 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 847 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 37/1717 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 898 attempts, .
[[35mlola[0m][.] 49 EF STEQ 37/1717 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 37/1166 2/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 218372 m, 6419 m/sec, 218372 t fired, .
[[35mlola[0m][.] 59 EF FNDP 36/1717 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 971 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 42/1712 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1035 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 42/1166 2/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 250480 m, 6421 m/sec, 250480 t fired, .
[[35mlola[0m][.] 59 EF FNDP 41/1712 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1101 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 47/1707 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1172 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 47/1166 2/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 281867 m, 6277 m/sec, 281867 t fired, .
[[35mlola[0m][.] 59 EF FNDP 46/1707 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1240 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 52/1702 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1307 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 52/1166 2/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 313172 m, 6261 m/sec, 313172 t fired, .
[[35mlola[0m][.] 59 EF FNDP 51/1702 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1380 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 57/1697 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1409 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 57/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 343940 m, 6153 m/sec, 343940 t fired, .
[[35mlola[0m][.] 59 EF FNDP 56/1697 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1487 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 62/1692 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1484 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 62/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 373398 m, 5891 m/sec, 373398 t fired, .
[[35mlola[0m][.] 59 EF FNDP 61/1692 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1551 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 67/1687 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1577 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 67/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 398795 m, 5079 m/sec, 398795 t fired, .
[[35mlola[0m][.] 59 EF FNDP 66/1687 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1666 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 72/1682 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1712 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 72/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 430422 m, 6325 m/sec, 430422 t fired, .
[[35mlola[0m][.] 59 EF FNDP 71/1682 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1804 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 77/1677 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1790 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 77/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 447682 m, 3452 m/sec, 447682 t fired, .
[[35mlola[0m][.] 59 EF FNDP 76/1677 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 1940 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 82/1672 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1919 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 82/1166 3/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 476981 m, 5859 m/sec, 476981 t fired, .
[[35mlola[0m][.] 59 EF FNDP 81/1672 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2074 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 87/1667 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2053 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 87/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 508676 m, 6339 m/sec, 508676 t fired, .
[[35mlola[0m][.] 59 EF FNDP 86/1667 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2205 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 92/1662 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2174 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 92/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 535920 m, 5448 m/sec, 535920 t fired, .
[[35mlola[0m][.] 59 EF FNDP 91/1662 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2345 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 97/1657 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2304 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 97/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 565589 m, 5933 m/sec, 565589 t fired, .
[[35mlola[0m][.] 59 EF FNDP 96/1657 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2479 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 102/1652 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2444 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 102/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 596752 m, 6232 m/sec, 596752 t fired, .
[[35mlola[0m][.] 59 EF FNDP 101/1652 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2614 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 107/1647 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2582 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 107/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 628105 m, 6270 m/sec, 628105 t fired, .
[[35mlola[0m][.] 59 EF FNDP 106/1647 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2753 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 112/1642 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2722 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 112/1166 4/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 660136 m, 6406 m/sec, 660136 t fired, .
[[35mlola[0m][.] 59 EF FNDP 111/1642 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 2884 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 3 0 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 117/1637 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2864 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 117/1166 5/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 692425 m, 6457 m/sec, 692425 t fired, .
[[35mlola[0m][.] 59 EF FNDP 116/1637 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 3015 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 122/1632 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3006 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 122/1166 5/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 724632 m, 6441 m/sec, 724632 t fired, .
[[35mlola[0m][.] 59 EF FNDP 121/1632 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 3148 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 127/1627 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3151 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 127/1166 5/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 756865 m, 6446 m/sec, 756865 t fired, .
[[35mlola[0m][.] 59 EF FNDP 126/1627 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04 3282 attempts, .
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[[35mlola[0m][I] FINISHED task # 59 (type FNDP) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-04
[[35mlola[0m][I] result : true
[[35mlola[0m][I] tried executions : 3383
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[[35mlola[0m][I] LAUNCH task # 55 (type FNDP) for 24 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08
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[[35mlola[0m][.] DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] 48 EF FNDP 132/3367 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3294 attempts, .
[[35mlola[0m][.] 49 EF STEQ 132/3367 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 132/1749 5/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 789150 m, 6457 m/sec, 789150 t fired, .
[[35mlola[0m][.] 55 EF FNDP 1/1683 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08 8 attempts, .
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[[35mlola[0m][.] 48 EF FNDP 137/3366 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3435 attempts, .
[[35mlola[0m][.] 49 EF STEQ 137/3366 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 137/1749 5/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 821453 m, 6460 m/sec, 821453 t fired, .
[[35mlola[0m][.] 55 EF FNDP 6/1682 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08 76 attempts, .
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[[35mlola[0m][I] FINISHED task # 55 (type FNDP) for DoubleLock-PT-p1s3-ReachabilityCardinality-2024-08
[[35mlola[0m][I] result : true
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[[35mlola[0m][.] 48 EF FNDP 142/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3579 attempts, .
[[35mlola[0m][.] 49 EF STEQ 142/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 142/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 853729 m, 6455 m/sec, 853729 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 147/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3717 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 147/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 884761 m, 6206 m/sec, 884761 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 152/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3856 attempts, .
[[35mlola[0m][.] 49 EF STEQ 152/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 sara not yet started (preprocessing).
[[35mlola[0m][.] 50 EF EXCL 152/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 915304 m, 6108 m/sec, 915304 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 157/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3993 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 157/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 946212 m, 6181 m/sec, 946212 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 162/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4125 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 162/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 976474 m, 6052 m/sec, 976474 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 167/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4264 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 167/3498 6/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1006680 m, 6041 m/sec, 1006680 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 172/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4407 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 172/3498 7/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1037604 m, 6184 m/sec, 1037604 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 177/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4546 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 177/3498 7/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1068648 m, 6208 m/sec, 1068648 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 182/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4687 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 182/3498 7/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1099236 m, 6117 m/sec, 1099236 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 187/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4822 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 187/3498 7/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1130052 m, 6163 m/sec, 1130052 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 192/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4965 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 192/3498 7/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1160632 m, 6116 m/sec, 1160632 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 197/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5115 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 197/3498 8/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1191077 m, 6089 m/sec, 1191077 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 202/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5261 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 202/3498 8/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1221913 m, 6167 m/sec, 1221913 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 207/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5403 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 207/3498 8/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1252235 m, 6064 m/sec, 1252235 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 212/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5542 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 212/3498 8/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1283021 m, 6157 m/sec, 1283021 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 217/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5683 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 217/3498 8/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1313857 m, 6167 m/sec, 1313857 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 222/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5828 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 222/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1345229 m, 6274 m/sec, 1345229 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 227/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5977 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 227/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1376382 m, 6230 m/sec, 1376382 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 232/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6117 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 232/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1407270 m, 6177 m/sec, 1407270 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 237/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6251 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 237/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1438158 m, 6177 m/sec, 1438158 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 242/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1469093 m, 6187 m/sec, 1469093 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 247/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6539 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 247/3498 9/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1500059 m, 6193 m/sec, 1500059 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 252/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6683 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 252/3498 10/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1530900 m, 6168 m/sec, 1530900 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 257/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6827 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 257/3498 10/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1562266 m, 6273 m/sec, 1562266 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 262/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6970 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 262/3498 10/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1593108 m, 6168 m/sec, 1593108 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 267/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7113 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 267/3498 10/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1623836 m, 6145 m/sec, 1623836 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 272/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7255 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 272/3498 10/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1654392 m, 6111 m/sec, 1654392 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 277/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1684892 m, 6100 m/sec, 1684892 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 282/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7547 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 282/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1715612 m, 6144 m/sec, 1715612 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 287/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7691 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 287/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1746270 m, 6131 m/sec, 1746270 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 292/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7833 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 292/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1776928 m, 6131 m/sec, 1776928 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 297/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7974 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 297/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1807517 m, 6117 m/sec, 1807517 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 302/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 8115 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 302/3498 11/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1838065 m, 6109 m/sec, 1838065 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 307/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 8256 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 307/3498 12/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1868381 m, 6063 m/sec, 1868381 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 312/3498 12/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1899121 m, 6148 m/sec, 1899121 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 317/3498 12/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1929893 m, 6154 m/sec, 1929893 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 322/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 8690 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 322/3498 12/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1960638 m, 6149 m/sec, 1960638 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 327/3498 12/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 1991094 m, 6091 m/sec, 1991094 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 332/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2021339 m, 6049 m/sec, 2021339 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 337/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2051117 m, 5955 m/sec, 2051117 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 342/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 9271 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 342/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2081285 m, 6033 m/sec, 2081285 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 347/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 9413 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 347/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2110984 m, 5939 m/sec, 2110984 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 352/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2141248 m, 6052 m/sec, 2141248 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 357/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 9702 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 357/3498 13/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2171584 m, 6067 m/sec, 2171584 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 362/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 9844 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 362/3498 14/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2201675 m, 6018 m/sec, 2201675 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 367/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 9983 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 367/3498 14/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2232212 m, 6107 m/sec, 2232212 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 372/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 10124 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 372/3498 14/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2262660 m, 6089 m/sec, 2262660 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 377/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 10267 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 377/3498 14/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2292827 m, 6033 m/sec, 2292827 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 382/3498 14/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2322980 m, 6030 m/sec, 2322980 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 387/3498 15/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2353147 m, 6033 m/sec, 2353148 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 392/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 10694 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 392/3498 15/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2383810 m, 6132 m/sec, 2383810 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 397/3498 15/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2415396 m, 6317 m/sec, 2415396 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 402/3498 15/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2446452 m, 6211 m/sec, 2446452 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 407/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 11135 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 407/3498 15/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2477272 m, 6164 m/sec, 2477272 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 417/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 11436 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 417/3498 16/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2539716 m, 6281 m/sec, 2539716 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 422/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 11579 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 422/3498 16/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2570358 m, 6128 m/sec, 2570358 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 427/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 11721 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 427/3498 16/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2601001 m, 6128 m/sec, 2601001 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 432/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 11866 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 432/3498 16/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2632153 m, 6230 m/sec, 2632153 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 437/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 12012 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 437/3498 16/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2663497 m, 6268 m/sec, 2663497 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 442/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 12156 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 442/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2694352 m, 6171 m/sec, 2694352 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 447/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 12305 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 447/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2725600 m, 6249 m/sec, 2725600 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 452/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 12452 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 452/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2756507 m, 6181 m/sec, 2756507 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 457/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2786862 m, 6071 m/sec, 2786862 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 462/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2818091 m, 6245 m/sec, 2818091 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 467/3498 17/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2848364 m, 6054 m/sec, 2848364 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 472/3498 18/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2879068 m, 6140 m/sec, 2879069 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 477/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 13186 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 477/3498 18/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2910390 m, 6264 m/sec, 2910390 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 482/3498 18/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 2942704 m, 6462 m/sec, 2942704 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 492/3498 18/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3005348 m, 6138 m/sec, 3005348 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 497/3498 19/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3036588 m, 6248 m/sec, 3036588 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 502/3498 19/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3067090 m, 6100 m/sec, 3067090 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 507/3498 19/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3097201 m, 6022 m/sec, 3097201 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 512/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 14214 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 512/3498 19/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3127547 m, 6069 m/sec, 3127547 t fired, .
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[[35mlola[0m][.] 48 EF FNDP 517/3498 0/5 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 14359 attempts, .
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[[35mlola[0m][.] 50 EF EXCL 517/3498 19/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3157897 m, 6070 m/sec, 3157897 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 527/3498 20/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3218602 m, 6121 m/sec, 3218602 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 532/3498 20/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3249150 m, 6109 m/sec, 3249150 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 537/3498 20/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3279749 m, 6119 m/sec, 3279749 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 542/3498 20/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3309994 m, 6049 m/sec, 3309994 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 547/3498 20/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3340282 m, 6057 m/sec, 3340282 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 552/3498 21/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3370508 m, 6045 m/sec, 3370508 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 562/3498 21/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3431896 m, 6064 m/sec, 3431896 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 567/3498 21/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3462001 m, 6021 m/sec, 3462001 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 572/3498 21/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3491964 m, 5992 m/sec, 3491964 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 577/3498 21/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3522064 m, 6020 m/sec, 3522064 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 582/3498 22/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3553139 m, 6215 m/sec, 3553139 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 587/3498 22/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3584425 m, 6257 m/sec, 3584425 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 592/3498 22/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3615620 m, 6239 m/sec, 3615620 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 597/3498 22/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3646830 m, 6242 m/sec, 3646830 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 602/3498 22/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3678356 m, 6305 m/sec, 3678356 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 607/3498 23/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3709960 m, 6320 m/sec, 3709960 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 612/3498 23/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3741564 m, 6320 m/sec, 3741564 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 617/3498 23/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3773161 m, 6319 m/sec, 3773161 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 622/3498 23/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3804797 m, 6327 m/sec, 3804797 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 627/3498 23/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3836382 m, 6317 m/sec, 3836382 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 632/3498 24/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3868018 m, 6327 m/sec, 3868018 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 637/3498 24/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3899656 m, 6327 m/sec, 3899656 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 642/3498 24/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3931272 m, 6323 m/sec, 3931272 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 647/3498 24/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3962881 m, 6321 m/sec, 3962881 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 652/3498 24/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 3994705 m, 6364 m/sec, 3994705 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 672/3498 25/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4122468 m, 6411 m/sec, 4122468 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 677/3498 25/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4153878 m, 6282 m/sec, 4153878 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 682/3498 25/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4185629 m, 6350 m/sec, 4185629 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 707/3498 26/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4346724 m, 6453 m/sec, 4346724 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 712/3498 27/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4378964 m, 6448 m/sec, 4378964 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 717/3498 27/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4411216 m, 6450 m/sec, 4411216 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 742/3498 28/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4572442 m, 6449 m/sec, 4572442 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 747/3498 28/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4604310 m, 6373 m/sec, 4604310 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 752/3498 28/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4636144 m, 6366 m/sec, 4636144 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 757/3498 28/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4667965 m, 6364 m/sec, 4667966 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 777/3498 29/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4795042 m, 6322 m/sec, 4795042 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 782/3498 29/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4826862 m, 6364 m/sec, 4826862 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 787/3498 29/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4858690 m, 6365 m/sec, 4858690 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 792/3498 30/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4890480 m, 6358 m/sec, 4890481 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 797/3498 30/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4922224 m, 6348 m/sec, 4922224 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 802/3498 30/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4954066 m, 6368 m/sec, 4954066 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 807/3498 30/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 4985873 m, 6361 m/sec, 4985873 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 812/3498 30/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5017696 m, 6364 m/sec, 5017696 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 817/3498 31/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5049480 m, 6356 m/sec, 5049480 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 822/3498 31/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5081286 m, 6361 m/sec, 5081286 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 827/3498 31/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5113116 m, 6366 m/sec, 5113116 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 852/3498 32/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5271496 m, 6250 m/sec, 5271496 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 922/3498 35/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5709976 m, 6182 m/sec, 5709976 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 927/3498 35/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5741382 m, 6281 m/sec, 5741382 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 932/3498 35/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5772773 m, 6278 m/sec, 5772773 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 937/3498 35/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5804425 m, 6330 m/sec, 5804425 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 957/3498 36/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5932177 m, 6385 m/sec, 5932177 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 962/3498 36/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5964034 m, 6371 m/sec, 5964034 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 967/3498 36/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 5995940 m, 6381 m/sec, 5995940 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 972/3498 36/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6027697 m, 6351 m/sec, 6027697 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 997/3498 37/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6184498 m, 5922 m/sec, 6184498 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 1067/3498 40/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 6615524 m, 6126 m/sec, 6615524 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 1212/3498 45/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7503006 m, 6240 m/sec, 7503006 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 1217/3498 45/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 7534260 m, 6250 m/sec, 7534260 t fired, .
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[[35mlola[0m][.] 50 EF EXCL 1317/3498 49/2000 DoubleLock-PT-p1s3-ReachabilityCardinality-2024-10 8166078 m, 6163 m/sec, 8166078 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s3"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s3, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600606"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s3.tgz
mv DoubleLock-PT-p1s3 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;