About the Execution of LoLA for DoubleLock-PT-p1s3
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16207.867 | 1143082.00 | 1174567.00 | 3939.70 | [undef] | Cannot compute |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600604.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p1s3, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600604
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 8.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 95K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 40K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.0K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 19K May 19 15:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 118K Apr 12 13:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 10K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 3.4M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s3-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717058342198
BK_STOP 1717059485280
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 256 transitions removed,132 places removed
[[35mlola[0m][I] LAUNCH task # 7 (type CNST) for 6 DoubleLock-PT-p1s3-LTLFireability-02
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 7 (type CNST) for DoubleLock-PT-p1s3-LTLFireability-02
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 6 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 DoubleLock-PT-p1s3-LTLFireability-08
[[35mlola[0m][I] time limit : 239 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 4/239 4/2000 DoubleLock-PT-p1s3-LTLFireability-08 362338 m, 72467 m/sec, 498191 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 4
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 9/239 8/2000 DoubleLock-PT-p1s3-LTLFireability-08 892238 m, 105980 m/sec, 1204722 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 8
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 14/239 13/2000 DoubleLock-PT-p1s3-LTLFireability-08 1413599 m, 104272 m/sec, 1899872 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 13
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 19/239 17/2000 DoubleLock-PT-p1s3-LTLFireability-08 1926868 m, 102653 m/sec, 2584227 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 17
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 24/239 22/2000 DoubleLock-PT-p1s3-LTLFireability-08 2451708 m, 104968 m/sec, 3284015 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 36 secs. Pages in use: 22
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 29/239 26/2000 DoubleLock-PT-p1s3-LTLFireability-08 2962315 m, 102121 m/sec, 3964824 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 41 secs. Pages in use: 26
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 34/239 31/2000 DoubleLock-PT-p1s3-LTLFireability-08 3473148 m, 102166 m/sec, 4645936 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 46 secs. Pages in use: 31
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 39/239 35/2000 DoubleLock-PT-p1s3-LTLFireability-08 3989594 m, 103289 m/sec, 5334529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 51 secs. Pages in use: 35
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 44/239 40/2000 DoubleLock-PT-p1s3-LTLFireability-08 4511794 m, 104440 m/sec, 6030797 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 56 secs. Pages in use: 40
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 49/239 44/2000 DoubleLock-PT-p1s3-LTLFireability-08 5034021 m, 104445 m/sec, 6727100 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 61 secs. Pages in use: 44
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 54/239 49/2000 DoubleLock-PT-p1s3-LTLFireability-08 5554793 m, 104154 m/sec, 7421462 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 66 secs. Pages in use: 49
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 59/239 53/2000 DoubleLock-PT-p1s3-LTLFireability-08 6076298 m, 104301 m/sec, 8116801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 71 secs. Pages in use: 53
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 64/239 58/2000 DoubleLock-PT-p1s3-LTLFireability-08 6597334 m, 104207 m/sec, 8811515 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 76 secs. Pages in use: 58
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 69/239 62/2000 DoubleLock-PT-p1s3-LTLFireability-08 7116517 m, 103836 m/sec, 9503759 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 81 secs. Pages in use: 62
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 74/239 67/2000 DoubleLock-PT-p1s3-LTLFireability-08 7631640 m, 103024 m/sec, 10190591 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 86 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 79/239 71/2000 DoubleLock-PT-p1s3-LTLFireability-08 8152462 m, 104164 m/sec, 10885020 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 91 secs. Pages in use: 71
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 84/239 76/2000 DoubleLock-PT-p1s3-LTLFireability-08 8665606 m, 102628 m/sec, 11569211 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 96 secs. Pages in use: 76
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 89/239 80/2000 DoubleLock-PT-p1s3-LTLFireability-08 9188977 m, 104674 m/sec, 12267042 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 101 secs. Pages in use: 80
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 94/239 85/2000 DoubleLock-PT-p1s3-LTLFireability-08 9711726 m, 104549 m/sec, 12964039 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 106 secs. Pages in use: 85
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 99/239 89/2000 DoubleLock-PT-p1s3-LTLFireability-08 10234765 m, 104607 m/sec, 13661422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 111 secs. Pages in use: 89
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 104/239 94/2000 DoubleLock-PT-p1s3-LTLFireability-08 10756231 m, 104293 m/sec, 14356712 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 116 secs. Pages in use: 94
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 109/239 98/2000 DoubleLock-PT-p1s3-LTLFireability-08 11278047 m, 104363 m/sec, 15052465 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 121 secs. Pages in use: 98
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 114/239 103/2000 DoubleLock-PT-p1s3-LTLFireability-08 11801819 m, 104754 m/sec, 15750831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 126 secs. Pages in use: 103
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 119/239 108/2000 DoubleLock-PT-p1s3-LTLFireability-08 12325009 m, 104638 m/sec, 16448418 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 131 secs. Pages in use: 108
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 124/239 112/2000 DoubleLock-PT-p1s3-LTLFireability-08 12847656 m, 104529 m/sec, 17145280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 136 secs. Pages in use: 112
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 129/239 117/2000 DoubleLock-PT-p1s3-LTLFireability-08 13369705 m, 104409 m/sec, 17841343 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 141 secs. Pages in use: 117
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 134/239 121/2000 DoubleLock-PT-p1s3-LTLFireability-08 13890336 m, 104126 m/sec, 18535518 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 146 secs. Pages in use: 121
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 139/239 126/2000 DoubleLock-PT-p1s3-LTLFireability-08 14409452 m, 103823 m/sec, 19227674 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 151 secs. Pages in use: 126
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 144/239 130/2000 DoubleLock-PT-p1s3-LTLFireability-08 14929933 m, 104096 m/sec, 19921650 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 156 secs. Pages in use: 130
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 149/239 135/2000 DoubleLock-PT-p1s3-LTLFireability-08 15451644 m, 104342 m/sec, 20617262 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 161 secs. Pages in use: 135
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 154/239 139/2000 DoubleLock-PT-p1s3-LTLFireability-08 15973520 m, 104375 m/sec, 21313096 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 166 secs. Pages in use: 139
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 159/239 144/2000 DoubleLock-PT-p1s3-LTLFireability-08 16494242 m, 104144 m/sec, 22007394 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 171 secs. Pages in use: 144
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 164/239 148/2000 DoubleLock-PT-p1s3-LTLFireability-08 17016653 m, 104482 m/sec, 22703941 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 176 secs. Pages in use: 148
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 169/239 153/2000 DoubleLock-PT-p1s3-LTLFireability-08 17538050 m, 104279 m/sec, 23399139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 181 secs. Pages in use: 153
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 174/239 157/2000 DoubleLock-PT-p1s3-LTLFireability-08 18059062 m, 104202 m/sec, 24093822 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 186 secs. Pages in use: 157
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 179/239 162/2000 DoubleLock-PT-p1s3-LTLFireability-08 18580283 m, 104244 m/sec, 24788782 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 191 secs. Pages in use: 162
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 184/239 166/2000 DoubleLock-PT-p1s3-LTLFireability-08 19101280 m, 104199 m/sec, 25483443 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 196 secs. Pages in use: 166
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 189/239 171/2000 DoubleLock-PT-p1s3-LTLFireability-08 19621416 m, 104027 m/sec, 26176960 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 201 secs. Pages in use: 171
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 194/239 175/2000 DoubleLock-PT-p1s3-LTLFireability-08 20142512 m, 104219 m/sec, 26871756 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 206 secs. Pages in use: 175
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 199/239 180/2000 DoubleLock-PT-p1s3-LTLFireability-08 20662452 m, 103988 m/sec, 27565009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 211 secs. Pages in use: 180
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 204/239 184/2000 DoubleLock-PT-p1s3-LTLFireability-08 21182300 m, 103969 m/sec, 28258139 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 216 secs. Pages in use: 184
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 209/239 189/2000 DoubleLock-PT-p1s3-LTLFireability-08 21702081 m, 103956 m/sec, 28951179 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 221 secs. Pages in use: 189
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 214/239 193/2000 DoubleLock-PT-p1s3-LTLFireability-08 22218981 m, 103380 m/sec, 29640377 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 226 secs. Pages in use: 193
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 219/239 198/2000 DoubleLock-PT-p1s3-LTLFireability-08 22740956 m, 104395 m/sec, 30336345 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 231 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 224/239 202/2000 DoubleLock-PT-p1s3-LTLFireability-08 23262240 m, 104256 m/sec, 31031390 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 236 secs. Pages in use: 202
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 229/239 207/2000 DoubleLock-PT-p1s3-LTLFireability-08 23782765 m, 104105 m/sec, 31725423 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 241 secs. Pages in use: 207
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 234/239 212/2000 DoubleLock-PT-p1s3-LTLFireability-08 24303450 m, 104137 m/sec, 32419672 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 246 secs. Pages in use: 212
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 239/239 216/2000 DoubleLock-PT-p1s3-LTLFireability-08 24821037 m, 103517 m/sec, 33109787 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 251 secs. Pages in use: 216
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 25 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-08 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 256 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p1s3-LTLFireability-15
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 25 (type EXCL) for 24 DoubleLock-PT-p1s3-LTLFireability-08
[[35mlola[0m][I] time limit : 3344 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 25 LTL EXCL 5/3344 5/5 DoubleLock-PT-p1s3-LTLFireability-08 524512 m, -4859305 m/sec, 714418 t fired, .
[[35mlola[0m][.] 46 LTL EXCL 5/238 5/2000 DoubleLock-PT-p1s3-LTLFireability-15 513952 m, 102790 m/sec, 700340 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 261 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 25 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-08 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 10/222 10/2000 DoubleLock-PT-p1s3-LTLFireability-15 1051550 m, 107519 m/sec, 1417136 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 266 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 15/238 14/2000 DoubleLock-PT-p1s3-LTLFireability-15 1584151 m, 106520 m/sec, 2127272 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 271 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 20/238 19/2000 DoubleLock-PT-p1s3-LTLFireability-15 2114068 m, 105983 m/sec, 2833829 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 276 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 25/238 24/2000 DoubleLock-PT-p1s3-LTLFireability-15 2643562 m, 105898 m/sec, 3539820 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 281 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 30/238 28/2000 DoubleLock-PT-p1s3-LTLFireability-15 3173294 m, 105946 m/sec, 4246132 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 286 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 35/238 33/2000 DoubleLock-PT-p1s3-LTLFireability-15 3702273 m, 105795 m/sec, 4951433 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 291 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 40/238 37/2000 DoubleLock-PT-p1s3-LTLFireability-15 4230167 m, 105578 m/sec, 5655293 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 296 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 45/238 42/2000 DoubleLock-PT-p1s3-LTLFireability-15 4759784 m, 105923 m/sec, 6361450 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 301 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 50/238 47/2000 DoubleLock-PT-p1s3-LTLFireability-15 5287831 m, 105609 m/sec, 7065512 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 306 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 55/238 51/2000 DoubleLock-PT-p1s3-LTLFireability-15 5815731 m, 105580 m/sec, 7769379 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 311 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 60/238 56/2000 DoubleLock-PT-p1s3-LTLFireability-15 6344096 m, 105673 m/sec, 8473864 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 316 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 65/238 60/2000 DoubleLock-PT-p1s3-LTLFireability-15 6872960 m, 105772 m/sec, 9179016 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 321 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 70/238 65/2000 DoubleLock-PT-p1s3-LTLFireability-15 7400830 m, 105574 m/sec, 9882844 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 326 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 75/238 70/2000 DoubleLock-PT-p1s3-LTLFireability-15 7927221 m, 105278 m/sec, 10584698 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 331 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 80/238 74/2000 DoubleLock-PT-p1s3-LTLFireability-15 8452095 m, 104974 m/sec, 11284529 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 336 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 85/238 79/2000 DoubleLock-PT-p1s3-LTLFireability-15 8978873 m, 105355 m/sec, 11986902 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 341 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 90/238 83/2000 DoubleLock-PT-p1s3-LTLFireability-15 9504602 m, 105145 m/sec, 12687873 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 346 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 95/238 88/2000 DoubleLock-PT-p1s3-LTLFireability-15 10029355 m, 104950 m/sec, 13387545 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 351 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 100/238 93/2000 DoubleLock-PT-p1s3-LTLFireability-15 10554786 m, 105086 m/sec, 14088118 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 356 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 105/238 97/2000 DoubleLock-PT-p1s3-LTLFireability-15 11078502 m, 104743 m/sec, 14786405 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 361 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 110/238 102/2000 DoubleLock-PT-p1s3-LTLFireability-15 11603686 m, 105036 m/sec, 15486652 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 366 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 115/238 106/2000 DoubleLock-PT-p1s3-LTLFireability-15 12131494 m, 105561 m/sec, 16190397 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 371 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 120/238 111/2000 DoubleLock-PT-p1s3-LTLFireability-15 12658106 m, 105322 m/sec, 16892546 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 376 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 125/238 116/2000 DoubleLock-PT-p1s3-LTLFireability-15 13182829 m, 104944 m/sec, 17592174 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 381 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 130/238 120/2000 DoubleLock-PT-p1s3-LTLFireability-15 13708073 m, 105048 m/sec, 18292503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 386 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 135/238 125/2000 DoubleLock-PT-p1s3-LTLFireability-15 14233868 m, 105159 m/sec, 18993563 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 391 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 140/238 129/2000 DoubleLock-PT-p1s3-LTLFireability-15 14758659 m, 104958 m/sec, 19693284 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 396 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 145/238 134/2000 DoubleLock-PT-p1s3-LTLFireability-15 15282540 m, 104776 m/sec, 20391792 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 401 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 150/238 138/2000 DoubleLock-PT-p1s3-LTLFireability-15 15809203 m, 105332 m/sec, 21094011 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 406 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 155/238 143/2000 DoubleLock-PT-p1s3-LTLFireability-15 16335740 m, 105307 m/sec, 21796058 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 411 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 160/238 148/2000 DoubleLock-PT-p1s3-LTLFireability-15 16860151 m, 104882 m/sec, 22495273 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 416 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 165/238 152/2000 DoubleLock-PT-p1s3-LTLFireability-15 17387426 m, 105455 m/sec, 23198305 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 421 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 170/238 157/2000 DoubleLock-PT-p1s3-LTLFireability-15 17914528 m, 105420 m/sec, 23901107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 426 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 175/238 161/2000 DoubleLock-PT-p1s3-LTLFireability-15 18441421 m, 105378 m/sec, 24603631 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 431 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 180/238 166/2000 DoubleLock-PT-p1s3-LTLFireability-15 18967699 m, 105255 m/sec, 25305334 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 436 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 185/238 171/2000 DoubleLock-PT-p1s3-LTLFireability-15 19493058 m, 105071 m/sec, 26005813 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 441 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 190/238 175/2000 DoubleLock-PT-p1s3-LTLFireability-15 20020773 m, 105543 m/sec, 26709436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 446 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 195/238 180/2000 DoubleLock-PT-p1s3-LTLFireability-15 20546709 m, 105187 m/sec, 27410682 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 451 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 200/238 184/2000 DoubleLock-PT-p1s3-LTLFireability-15 21072525 m, 105163 m/sec, 28111771 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 456 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 205/238 189/2000 DoubleLock-PT-p1s3-LTLFireability-15 21598184 m, 105131 m/sec, 28812649 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 461 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 210/238 194/2000 DoubleLock-PT-p1s3-LTLFireability-15 22123320 m, 105027 m/sec, 29512831 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 466 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 215/238 198/2000 DoubleLock-PT-p1s3-LTLFireability-15 22650968 m, 105529 m/sec, 30216361 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 471 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 220/238 203/2000 DoubleLock-PT-p1s3-LTLFireability-15 23177354 m, 105277 m/sec, 30918209 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 476 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 225/238 207/2000 DoubleLock-PT-p1s3-LTLFireability-15 23704758 m, 105480 m/sec, 31621415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 481 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 230/238 212/2000 DoubleLock-PT-p1s3-LTLFireability-15 24231406 m, 105329 m/sec, 32323612 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 486 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 46 LTL EXCL 235/238 217/2000 DoubleLock-PT-p1s3-LTLFireability-15 24757245 m, 105167 m/sec, 33024732 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 491 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 46 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-15 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 496 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 DoubleLock-PT-p1s3-LTLFireability-13
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 46 (type EXCL) for 45 DoubleLock-PT-p1s3-LTLFireability-15
[[35mlola[0m][I] time limit : 3104 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 5/238 5/2000 DoubleLock-PT-p1s3-LTLFireability-13 516693 m, 103338 m/sec, 703995 t fired, .
[[35mlola[0m][.] 46 LTL EXCL 5/3104 4/5 DoubleLock-PT-p1s3-LTLFireability-15 426220 m, -4866205 m/sec, 583366 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 501 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 46 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-15 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 10/238 9/2000 DoubleLock-PT-p1s3-LTLFireability-13 1031112 m, 102883 m/sec, 1389886 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 506 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 15/238 14/2000 DoubleLock-PT-p1s3-LTLFireability-13 1563307 m, 106439 m/sec, 2099482 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 511 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 20/238 19/2000 DoubleLock-PT-p1s3-LTLFireability-13 2093259 m, 105990 m/sec, 2806083 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 516 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 25/238 23/2000 DoubleLock-PT-p1s3-LTLFireability-13 2623030 m, 105954 m/sec, 3512446 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 521 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 30/238 28/2000 DoubleLock-PT-p1s3-LTLFireability-13 3152171 m, 105828 m/sec, 4217966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 526 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 35/238 32/2000 DoubleLock-PT-p1s3-LTLFireability-13 3680204 m, 105606 m/sec, 4922009 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 531 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 40/238 37/2000 DoubleLock-PT-p1s3-LTLFireability-13 4208546 m, 105668 m/sec, 5626466 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 536 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 45/238 42/2000 DoubleLock-PT-p1s3-LTLFireability-13 4736979 m, 105686 m/sec, 6331044 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 541 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 50/238 46/2000 DoubleLock-PT-p1s3-LTLFireability-13 5263937 m, 105391 m/sec, 7033653 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 546 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 55/238 51/2000 DoubleLock-PT-p1s3-LTLFireability-13 5790220 m, 105256 m/sec, 7735364 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 551 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 60/238 55/2000 DoubleLock-PT-p1s3-LTLFireability-13 6318274 m, 105610 m/sec, 8439437 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 556 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 65/238 60/2000 DoubleLock-PT-p1s3-LTLFireability-13 6845622 m, 105469 m/sec, 9142568 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 561 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 70/238 64/2000 DoubleLock-PT-p1s3-LTLFireability-13 7371333 m, 105142 m/sec, 9843514 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 566 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 75/238 69/2000 DoubleLock-PT-p1s3-LTLFireability-13 7893757 m, 104484 m/sec, 10540081 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 571 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 80/238 74/2000 DoubleLock-PT-p1s3-LTLFireability-13 8417534 m, 104755 m/sec, 11238449 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 576 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 85/238 78/2000 DoubleLock-PT-p1s3-LTLFireability-13 8942084 m, 104910 m/sec, 11937850 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 581 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 90/238 83/2000 DoubleLock-PT-p1s3-LTLFireability-13 9465857 m, 104754 m/sec, 12636213 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 586 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 95/238 87/2000 DoubleLock-PT-p1s3-LTLFireability-13 9991757 m, 105180 m/sec, 13337415 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 591 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 100/238 92/2000 DoubleLock-PT-p1s3-LTLFireability-13 10517510 m, 105150 m/sec, 14038416 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 596 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 105/238 96/2000 DoubleLock-PT-p1s3-LTLFireability-13 11042264 m, 104950 m/sec, 14738091 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 601 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 110/238 101/2000 DoubleLock-PT-p1s3-LTLFireability-13 11568562 m, 105259 m/sec, 15439819 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 606 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 115/238 106/2000 DoubleLock-PT-p1s3-LTLFireability-13 12095612 m, 105410 m/sec, 16142553 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 611 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 120/238 110/2000 DoubleLock-PT-p1s3-LTLFireability-13 12621670 m, 105211 m/sec, 16843963 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 616 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 125/238 115/2000 DoubleLock-PT-p1s3-LTLFireability-13 13147091 m, 105084 m/sec, 17544525 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 621 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 130/238 119/2000 DoubleLock-PT-p1s3-LTLFireability-13 13672231 m, 105028 m/sec, 18244711 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 626 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 135/238 124/2000 DoubleLock-PT-p1s3-LTLFireability-13 14198125 m, 105178 m/sec, 18945906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 631 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 140/238 128/2000 DoubleLock-PT-p1s3-LTLFireability-13 14723347 m, 105044 m/sec, 19646200 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 636 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 145/238 133/2000 DoubleLock-PT-p1s3-LTLFireability-13 15247074 m, 104745 m/sec, 20344504 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 641 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 150/238 137/2000 DoubleLock-PT-p1s3-LTLFireability-13 15772128 m, 105010 m/sec, 21044573 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 646 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 155/238 142/2000 DoubleLock-PT-p1s3-LTLFireability-13 16296965 m, 104967 m/sec, 21744359 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 651 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 160/238 147/2000 DoubleLock-PT-p1s3-LTLFireability-13 16821003 m, 104807 m/sec, 22443077 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 656 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 165/238 151/2000 DoubleLock-PT-p1s3-LTLFireability-13 17346716 m, 105142 m/sec, 23144026 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 661 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 170/238 156/2000 DoubleLock-PT-p1s3-LTLFireability-13 17869599 m, 104576 m/sec, 23841204 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 666 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 175/238 160/2000 DoubleLock-PT-p1s3-LTLFireability-13 18394108 m, 104901 m/sec, 24540547 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 671 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 180/238 165/2000 DoubleLock-PT-p1s3-LTLFireability-13 18917957 m, 104769 m/sec, 25239013 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 676 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 185/238 169/2000 DoubleLock-PT-p1s3-LTLFireability-13 19441348 m, 104678 m/sec, 25936868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 681 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 190/238 174/2000 DoubleLock-PT-p1s3-LTLFireability-13 19966614 m, 105053 m/sec, 26637225 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 686 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 195/238 178/2000 DoubleLock-PT-p1s3-LTLFireability-13 20490110 m, 104699 m/sec, 27335217 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 691 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 200/238 183/2000 DoubleLock-PT-p1s3-LTLFireability-13 21013664 m, 104710 m/sec, 28033289 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 696 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 205/238 188/2000 DoubleLock-PT-p1s3-LTLFireability-13 21536991 m, 104665 m/sec, 28731059 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 701 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 210/238 192/2000 DoubleLock-PT-p1s3-LTLFireability-13 22060013 m, 104604 m/sec, 29428421 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 706 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 215/238 197/2000 DoubleLock-PT-p1s3-LTLFireability-13 22585135 m, 105024 m/sec, 30128584 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 711 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 220/238 201/2000 DoubleLock-PT-p1s3-LTLFireability-13 23110306 m, 105034 m/sec, 30828811 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 716 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 225/238 206/2000 DoubleLock-PT-p1s3-LTLFireability-13 23634212 m, 104781 m/sec, 31527353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 721 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 230/238 210/2000 DoubleLock-PT-p1s3-LTLFireability-13 24157932 m, 104744 m/sec, 32225645 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 726 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 40 LTL EXCL 235/238 215/2000 DoubleLock-PT-p1s3-LTLFireability-13 24680716 m, 104556 m/sec, 32922693 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 731 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 40 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-13 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 736 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DoubleLock-PT-p1s3-LTLFireability-10
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 40 (type EXCL) for 39 DoubleLock-PT-p1s3-LTLFireability-13
[[35mlola[0m][I] time limit : 2864 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 5/238 5/2000 DoubleLock-PT-p1s3-LTLFireability-10 522346 m, 104469 m/sec, 711531 t fired, .
[[35mlola[0m][.] 40 LTL EXCL 5/2864 5/5 DoubleLock-PT-p1s3-LTLFireability-13 521017 m, -4831939 m/sec, 709761 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 741 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 40 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-13 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 10/238 10/2000 DoubleLock-PT-p1s3-LTLFireability-10 1064137 m, 108358 m/sec, 1433923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 746 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 2 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 15/238 14/2000 DoubleLock-PT-p1s3-LTLFireability-10 1595663 m, 106305 m/sec, 2142622 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 751 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 20/238 19/2000 DoubleLock-PT-p1s3-LTLFireability-10 2124966 m, 105860 m/sec, 2848357 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 756 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 25/238 24/2000 DoubleLock-PT-p1s3-LTLFireability-10 2653786 m, 105764 m/sec, 3553452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 761 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 30/238 28/2000 DoubleLock-PT-p1s3-LTLFireability-10 3183124 m, 105867 m/sec, 4259237 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 766 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 35/238 33/2000 DoubleLock-PT-p1s3-LTLFireability-10 3712159 m, 105807 m/sec, 4964617 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 771 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 40/238 37/2000 DoubleLock-PT-p1s3-LTLFireability-10 4239973 m, 105562 m/sec, 5668368 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 776 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 45/238 42/2000 DoubleLock-PT-p1s3-LTLFireability-10 4768358 m, 105677 m/sec, 6372880 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 781 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 50/238 47/2000 DoubleLock-PT-p1s3-LTLFireability-10 5296128 m, 105554 m/sec, 7076575 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 786 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 55/238 51/2000 DoubleLock-PT-p1s3-LTLFireability-10 5824305 m, 105635 m/sec, 7780810 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 791 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 60/238 56/2000 DoubleLock-PT-p1s3-LTLFireability-10 6352632 m, 105665 m/sec, 8485249 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 796 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 65/238 60/2000 DoubleLock-PT-p1s3-LTLFireability-10 6879700 m, 105413 m/sec, 9188003 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 801 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 70/238 65/2000 DoubleLock-PT-p1s3-LTLFireability-10 7404723 m, 105004 m/sec, 9888034 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 806 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 75/238 70/2000 DoubleLock-PT-p1s3-LTLFireability-10 7931321 m, 105319 m/sec, 10590165 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 811 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 80/238 74/2000 DoubleLock-PT-p1s3-LTLFireability-10 8456590 m, 105053 m/sec, 11290524 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 816 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 85/238 79/2000 DoubleLock-PT-p1s3-LTLFireability-10 8983315 m, 105345 m/sec, 11992825 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 821 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 90/238 83/2000 DoubleLock-PT-p1s3-LTLFireability-10 9509075 m, 105152 m/sec, 12693838 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 826 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 95/238 88/2000 DoubleLock-PT-p1s3-LTLFireability-10 10035001 m, 105185 m/sec, 13395073 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 831 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 100/238 92/2000 DoubleLock-PT-p1s3-LTLFireability-10 10559777 m, 104955 m/sec, 14094774 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 836 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 105/238 97/2000 DoubleLock-PT-p1s3-LTLFireability-10 11084011 m, 104846 m/sec, 14793752 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 841 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 110/238 102/2000 DoubleLock-PT-p1s3-LTLFireability-10 11610748 m, 105347 m/sec, 15496066 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 846 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 115/238 106/2000 DoubleLock-PT-p1s3-LTLFireability-10 12137150 m, 105280 m/sec, 16197937 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 851 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 120/238 111/2000 DoubleLock-PT-p1s3-LTLFireability-10 12663622 m, 105294 m/sec, 16899899 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 856 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 125/238 115/2000 DoubleLock-PT-p1s3-LTLFireability-10 13189315 m, 105138 m/sec, 17600823 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 861 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 130/238 120/2000 DoubleLock-PT-p1s3-LTLFireability-10 13706081 m, 103353 m/sec, 18289846 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 866 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 135/238 124/2000 DoubleLock-PT-p1s3-LTLFireability-10 14229847 m, 104753 m/sec, 18988199 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 871 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 140/238 129/2000 DoubleLock-PT-p1s3-LTLFireability-10 14754049 m, 104840 m/sec, 19687135 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 876 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 145/238 133/2000 DoubleLock-PT-p1s3-LTLFireability-10 15276941 m, 104578 m/sec, 20384326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 881 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 150/238 138/2000 DoubleLock-PT-p1s3-LTLFireability-10 15801739 m, 104959 m/sec, 21084056 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 886 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 155/238 143/2000 DoubleLock-PT-p1s3-LTLFireability-10 16325323 m, 104716 m/sec, 21782169 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 891 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 160/238 147/2000 DoubleLock-PT-p1s3-LTLFireability-10 16850334 m, 105002 m/sec, 22482182 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 896 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 165/238 152/2000 DoubleLock-PT-p1s3-LTLFireability-10 17375126 m, 104958 m/sec, 23181907 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 901 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 170/238 156/2000 DoubleLock-PT-p1s3-LTLFireability-10 17899626 m, 104900 m/sec, 23881240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 906 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 175/238 161/2000 DoubleLock-PT-p1s3-LTLFireability-10 18424646 m, 105004 m/sec, 24581267 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 911 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 180/238 165/2000 DoubleLock-PT-p1s3-LTLFireability-10 18949526 m, 104976 m/sec, 25281107 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 916 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 185/238 170/2000 DoubleLock-PT-p1s3-LTLFireability-10 19472550 m, 104604 m/sec, 25978473 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 921 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 190/238 175/2000 DoubleLock-PT-p1s3-LTLFireability-10 19996691 m, 104828 m/sec, 26677326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 926 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 195/238 179/2000 DoubleLock-PT-p1s3-LTLFireability-10 20519369 m, 104535 m/sec, 27374228 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 931 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 200/238 184/2000 DoubleLock-PT-p1s3-LTLFireability-10 21042877 m, 104701 m/sec, 28072240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 936 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 205/238 188/2000 DoubleLock-PT-p1s3-LTLFireability-10 21565562 m, 104537 m/sec, 28769153 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 941 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 210/238 193/2000 DoubleLock-PT-p1s3-LTLFireability-10 22088301 m, 104547 m/sec, 29466137 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 946 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 215/238 197/2000 DoubleLock-PT-p1s3-LTLFireability-10 22613461 m, 105032 m/sec, 30166353 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 951 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 220/238 202/2000 DoubleLock-PT-p1s3-LTLFireability-10 23138753 m, 105058 m/sec, 30866742 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 956 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 225/238 206/2000 DoubleLock-PT-p1s3-LTLFireability-10 23663012 m, 104851 m/sec, 31565753 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 961 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 230/238 211/2000 DoubleLock-PT-p1s3-LTLFireability-10 24188377 m, 105073 m/sec, 32266240 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 966 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 235/238 216/2000 DoubleLock-PT-p1s3-LTLFireability-10 24712303 m, 104785 m/sec, 32964809 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 971 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][W] CANCELED task # 31 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-10 (local timeout)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 976 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 28 (type EXCL) for 27 DoubleLock-PT-p1s3-LTLFireability-09
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 31 (type EXCL) for 30 DoubleLock-PT-p1s3-LTLFireability-10
[[35mlola[0m][I] time limit : 2624 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 28 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 112
[[35mlola[0m][I] fired transitions : 113
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 31 LTL EXCL 5/238 5/5 DoubleLock-PT-p1s3-LTLFireability-10 535484 m, -4835363 m/sec, 729051 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 981 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] CANCELED task # 31 (type EXCL) for DoubleLock-PT-p1s3-LTLFireability-10 (memory limit exceeded)
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 986 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 22 (type EXCL) for 21 DoubleLock-PT-p1s3-LTLFireability-07
[[35mlola[0m][I] time limit : 261 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 5/261 5/2000 DoubleLock-PT-p1s3-LTLFireability-07 537023 m, 107404 m/sec, 731102 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 991 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 10/261 10/2000 DoubleLock-PT-p1s3-LTLFireability-07 1073568 m, 107309 m/sec, 1446497 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 996 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 15/261 14/2000 DoubleLock-PT-p1s3-LTLFireability-07 1605849 m, 106456 m/sec, 2156203 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1001 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 20/261 19/2000 DoubleLock-PT-p1s3-LTLFireability-07 2131451 m, 105120 m/sec, 2857004 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1006 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 25/261 24/2000 DoubleLock-PT-p1s3-LTLFireability-07 2666849 m, 107079 m/sec, 3570868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1011 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 30/261 28/2000 DoubleLock-PT-p1s3-LTLFireability-07 3200161 m, 106662 m/sec, 4281951 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1016 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 35/261 33/2000 DoubleLock-PT-p1s3-LTLFireability-07 3731513 m, 106270 m/sec, 4990422 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1021 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 40/261 37/2000 DoubleLock-PT-p1s3-LTLFireability-07 4262527 m, 106202 m/sec, 5698440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1026 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 45/261 42/2000 DoubleLock-PT-p1s3-LTLFireability-07 4781848 m, 103864 m/sec, 6390868 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1031 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 50/261 47/2000 DoubleLock-PT-p1s3-LTLFireability-07 5306376 m, 104905 m/sec, 7090238 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1036 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 55/261 51/2000 DoubleLock-PT-p1s3-LTLFireability-07 5837890 m, 106302 m/sec, 7798923 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1041 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 60/261 56/2000 DoubleLock-PT-p1s3-LTLFireability-07 6369897 m, 106401 m/sec, 8508268 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1046 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 65/261 60/2000 DoubleLock-PT-p1s3-LTLFireability-07 6900961 m, 106212 m/sec, 9216354 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1051 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 70/261 65/2000 DoubleLock-PT-p1s3-LTLFireability-07 7431702 m, 106148 m/sec, 9924007 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1056 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 75/261 70/2000 DoubleLock-PT-p1s3-LTLFireability-07 7962783 m, 106216 m/sec, 10632117 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1061 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 80/261 74/2000 DoubleLock-PT-p1s3-LTLFireability-07 8492445 m, 105932 m/sec, 11338333 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1066 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 85/261 79/2000 DoubleLock-PT-p1s3-LTLFireability-07 9023454 m, 106201 m/sec, 12046344 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1071 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 90/261 83/2000 DoubleLock-PT-p1s3-LTLFireability-07 9553373 m, 105983 m/sec, 12752901 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1076 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 95/261 88/2000 DoubleLock-PT-p1s3-LTLFireability-07 10083153 m, 105956 m/sec, 13459277 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1081 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 100/261 93/2000 DoubleLock-PT-p1s3-LTLFireability-07 10612698 m, 105909 m/sec, 14165335 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1086 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 105/261 97/2000 DoubleLock-PT-p1s3-LTLFireability-07 11141560 m, 105772 m/sec, 14870485 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1091 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 110/261 102/2000 DoubleLock-PT-p1s3-LTLFireability-07 11672797 m, 106247 m/sec, 15578801 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1096 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 115/261 106/2000 DoubleLock-PT-p1s3-LTLFireability-07 12203525 m, 106145 m/sec, 16286440 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1101 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 120/261 111/2000 DoubleLock-PT-p1s3-LTLFireability-07 12733707 m, 106036 m/sec, 16993348 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1106 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 125/261 116/2000 DoubleLock-PT-p1s3-LTLFireability-07 13262127 m, 105684 m/sec, 17697906 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1111 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 130/261 120/2000 DoubleLock-PT-p1s3-LTLFireability-07 13787681 m, 105110 m/sec, 18398647 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1116 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 135/261 125/2000 DoubleLock-PT-p1s3-LTLFireability-07 14296874 m, 101838 m/sec, 19077569 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1121 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-02: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s3-LTLFireability-09: LTL false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-07: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-10: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s3-LTLFireability-15: LTL 0 0 0 0 1 0 1 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 22 LTL EXCL 153/261 126/2000 DoubleLock-PT-p1s3-LTLFireability-07 14410386 m, 22702 m/sec, 19228917 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 1141 secs. Pages in use: 221
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 406 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s3"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s3, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600604"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s3.tgz
mv DoubleLock-PT-p1s3 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;