About the Execution of LoLA for DoubleLock-PT-p1s2
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16206.348 | 907734.00 | 2754856.00 | 2606.20 | ?????????F???F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600596.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p1s2, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600596
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.8M
-rw-r--r-- 1 mcc users 6.9K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 19 15:48 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 19 18:16 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 13:39 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 152K Apr 12 13:39 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 3.4M May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s2-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717057057144
FORMULA DoubleLock-PT-p1s2-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s2-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717057964878
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 256 transitions removed,132 places removed
[[35mlola[0m][I] LAUNCH task # 32 (type CNST) for 31 DoubleLock-PT-p1s2-LTLFireability-09
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 32 (type CNST) for DoubleLock-PT-p1s2-LTLFireability-09
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-08: CONJ 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-13: INITIAL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 11 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 DoubleLock-PT-p1s2-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for DoubleLock-PT-p1s2-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-04: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-08: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-11: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 16 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 1 (type EXCL) for 0 DoubleLock-PT-p1s2-LTLFireability-00
[[35mlola[0m][I] time limit : 238 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 24 DoubleLock-PT-p1s2-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 24 DoubleLock-PT-p1s2-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 57 (type FNDP) for 40 DoubleLock-PT-p1s2-LTLFireability-12
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-08: CONJ 0 3 2 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 4/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 2516 m, 503 m/sec, 2524 t fired, .
[[35mlola[0m][.] 53 EF FNDP 4/1790 0/5 DoubleLock-PT-p1s2-LTLFireability-08 38 attempts, .
[[35mlola[0m][.] 54 EF STEQ 4/1790 0/5 DoubleLock-PT-p1s2-LTLFireability-08 sara not yet started (preprocessing).
[[35mlola[0m][.] 57 EF FNDP 4/3582 0/5 DoubleLock-PT-p1s2-LTLFireability-12 74 attempts, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 21 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] FINISHED task # 54 (type EQUN) for DoubleLock-PT-p1s2-LTLFireability-08
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] LAUNCH task # 64 (type EQUN) for 24 DoubleLock-PT-p1s2-LTLFireability-08
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-08: CONJ 0 2 2 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 9/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 5333 m, 563 m/sec, 5341 t fired, .
[[35mlola[0m][.] 53 EF FNDP 9/3576 0/5 DoubleLock-PT-p1s2-LTLFireability-08 100 attempts, .
[[35mlola[0m][.] 57 EF FNDP 9/3576 0/5 DoubleLock-PT-p1s2-LTLFireability-12 191 attempts, .
[[35mlola[0m][.] 64 EF STEQ 2/1788 0/5 DoubleLock-PT-p1s2-LTLFireability-08 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 26 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-00: LTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-08: CONJ 0 2 2 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 1 LTL EXCL 14/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 8146 m, 562 m/sec, 8154 t fired, .
[[35mlola[0m][.] 53 EF FNDP 14/3574 0/5 DoubleLock-PT-p1s2-LTLFireability-08 180 attempts, .
[[35mlola[0m][.] 57 EF FNDP 14/3574 0/5 DoubleLock-PT-p1s2-LTLFireability-12 309 attempts, .
[[35mlola[0m][.] 64 EF STEQ 7/1786 0/5 DoubleLock-PT-p1s2-LTLFireability-08 sara not yet started (preprocessing).
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 31 secs. Pages in use: 1
[[35mlola[0m][.] # running tasks: 4 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-09: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s2-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] 57 EF FNDP 19/3569 0/5 DoubleLock-PT-p1s2-LTLFireability-12 431 attempts, .
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[[35mlola[0m][.] 1 LTL EXCL 24/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 13782 m, 563 m/sec, 13790 t fired, .
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[[35mlola[0m][.] 57 EF FNDP 24/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-12 560 attempts, .
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[[35mlola[0m][.] 1 LTL EXCL 29/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 16467 m, 537 m/sec, 16475 t fired, .
[[35mlola[0m][.] 53 EF FNDP 29/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-08 444 attempts, .
[[35mlola[0m][.] 57 EF FNDP 29/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-12 689 attempts, .
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[[35mlola[0m][.] 1 LTL EXCL 34/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 18863 m, 479 m/sec, 18871 t fired, .
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[[35mlola[0m][.] 57 EF FNDP 34/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-12 811 attempts, .
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[[35mlola[0m][.] DoubleLock-PT-p1s2-LTLFireability-12: AG 0 1 2 0 1 0 0 0
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[[35mlola[0m][.] 1 LTL EXCL 39/238 1/2000 DoubleLock-PT-p1s2-LTLFireability-00 21682 m, 563 m/sec, 21690 t fired, .
[[35mlola[0m][.] 53 EF FNDP 39/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-08 634 attempts, .
[[35mlola[0m][.] 57 EF FNDP 39/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-12 930 attempts, .
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[[35mlola[0m][.] 57 EF FNDP 49/3583 0/5 DoubleLock-PT-p1s2-LTLFireability-12 1185 attempts, .
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/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s2"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s2, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600596"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s2.tgz
mv DoubleLock-PT-p1s2 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;