About the Execution of LoLA for DoubleLock-PT-p1s1
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
16204.512 | 166551.00 | 168074.00 | 250.40 | F??F???????T???F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134600588.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleLock-PT-p1s1, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134600588
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 576K
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 72K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.6K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 39K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Apr 22 14:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Apr 22 14:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Apr 22 14:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Apr 22 14:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Apr 12 13:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 153K Apr 12 13:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Apr 12 13:30 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 93K Apr 12 13:30 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 5 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 93K May 18 16:42 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-00
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-01
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-02
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-03
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-04
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-05
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-06
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-07
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-08
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-09
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-10
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-11
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-12
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-13
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-14
FORMULA_NAME DoubleLock-PT-p1s1-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1717055989212
FORMULA DoubleLock-PT-p1s1-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-LTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleLock-PT-p1s1-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1717056155763
--------------------
content from stderr:
[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] LAUNCH task # 1 (type CNST) for 0 DoubleLock-PT-p1s1-LTLFireability-00
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 1 (type CNST) for DoubleLock-PT-p1s1-LTLFireability-00
[[35mlola[0m][I] result : false
[[35mlola[0m][I] Rule S: 8 transitions removed,8 places removed
[[35mlola[0m][I] LAUNCH task # 50 (type CNST) for 49 DoubleLock-PT-p1s1-LTLFireability-11
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] LAUNCH task # 73 (type EXCL) for 9 DoubleLock-PT-p1s1-LTLFireability-03
[[35mlola[0m][I] time limit : 171 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 76 (type EQUN) for 9 DoubleLock-PT-p1s1-LTLFireability-03
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 50 (type CNST) for DoubleLock-PT-p1s1-LTLFireability-11
[[35mlola[0m][I] result : true
[[35mlola[0m][I] LAUNCH task # 81 (type EQUN) for 35 DoubleLock-PT-p1s1-LTLFireability-09
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type EXCL) for DoubleLock-PT-p1s1-LTLFireability-03
[[35mlola[0m][I] result : true
[[35mlola[0m][I] markings : 27
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 76 (type EQUN) for DoubleLock-PT-p1s1-LTLFireability-03 (obsolete)
[[35mlola[0m][I] LAUNCH task # 70 (type EXCL) for 65 DoubleLock-PT-p1s1-LTLFireability-15
[[35mlola[0m][I] time limit : 200 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 70 (type EXCL) for DoubleLock-PT-p1s1-LTLFireability-15
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 27
[[35mlola[0m][I] fired transitions : 27
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 60 (type EXCL) for 55 DoubleLock-PT-p1s1-LTLFireability-13
[[35mlola[0m][I] time limit : 225 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 76 (type EQUN) for DoubleLock-PT-p1s1-LTLFireability-03
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] FINISHED task # 81 (type EQUN) for DoubleLock-PT-p1s1-LTLFireability-09
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 5/225 23/2000 DoubleLock-PT-p1s1-LTLFireability-13 3194502 m, 638900 m/sec, 3194503 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 5 secs. Pages in use: 23
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 10/225 45/2000 DoubleLock-PT-p1s1-LTLFireability-13 6389943 m, 639088 m/sec, 6389944 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 10 secs. Pages in use: 45
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 15/225 67/2000 DoubleLock-PT-p1s1-LTLFireability-13 9556074 m, 633226 m/sec, 9556074 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 15 secs. Pages in use: 67
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 20/225 88/2000 DoubleLock-PT-p1s1-LTLFireability-13 12661478 m, 621080 m/sec, 12661479 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 20 secs. Pages in use: 88
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 25/225 110/2000 DoubleLock-PT-p1s1-LTLFireability-13 15771071 m, 621918 m/sec, 15771072 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 25 secs. Pages in use: 110
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 30/225 132/2000 DoubleLock-PT-p1s1-LTLFireability-13 18917634 m, 629312 m/sec, 18917635 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 30 secs. Pages in use: 132
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 35/225 154/2000 DoubleLock-PT-p1s1-LTLFireability-13 22091279 m, 634729 m/sec, 22091280 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 35 secs. Pages in use: 154
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 40/225 176/2000 DoubleLock-PT-p1s1-LTLFireability-13 25251452 m, 632034 m/sec, 25251452 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 40 secs. Pages in use: 176
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 45/225 198/2000 DoubleLock-PT-p1s1-LTLFireability-13 28402435 m, 630196 m/sec, 28402436 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 45 secs. Pages in use: 198
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 50/225 220/2000 DoubleLock-PT-p1s1-LTLFireability-13 31555326 m, 630578 m/sec, 31555326 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 50 secs. Pages in use: 220
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 55/225 241/2000 DoubleLock-PT-p1s1-LTLFireability-13 34693265 m, 627587 m/sec, 34693265 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 55 secs. Pages in use: 241
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 60/225 263/2000 DoubleLock-PT-p1s1-LTLFireability-13 37801826 m, 621712 m/sec, 37801827 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 60 secs. Pages in use: 263
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 65/225 285/2000 DoubleLock-PT-p1s1-LTLFireability-13 40903262 m, 620287 m/sec, 40903263 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 65 secs. Pages in use: 285
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 70/225 306/2000 DoubleLock-PT-p1s1-LTLFireability-13 44014976 m, 622342 m/sec, 44014976 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 70 secs. Pages in use: 306
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 75/225 328/2000 DoubleLock-PT-p1s1-LTLFireability-13 47144888 m, 625982 m/sec, 47144889 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 75 secs. Pages in use: 328
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 80/225 350/2000 DoubleLock-PT-p1s1-LTLFireability-13 50247565 m, 620535 m/sec, 50247566 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 80 secs. Pages in use: 350
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 85/225 371/2000 DoubleLock-PT-p1s1-LTLFireability-13 53354728 m, 621432 m/sec, 53354729 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 85 secs. Pages in use: 371
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 90/225 393/2000 DoubleLock-PT-p1s1-LTLFireability-13 56445114 m, 618077 m/sec, 56445115 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 90 secs. Pages in use: 393
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 95/225 414/2000 DoubleLock-PT-p1s1-LTLFireability-13 59537854 m, 618548 m/sec, 59537855 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 95 secs. Pages in use: 414
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 100/225 436/2000 DoubleLock-PT-p1s1-LTLFireability-13 62631762 m, 618781 m/sec, 62631763 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 100 secs. Pages in use: 436
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 105/225 457/2000 DoubleLock-PT-p1s1-LTLFireability-13 65694493 m, 612546 m/sec, 65694494 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 105 secs. Pages in use: 457
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 110/225 478/2000 DoubleLock-PT-p1s1-LTLFireability-13 68759409 m, 612983 m/sec, 68759409 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 110 secs. Pages in use: 478
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 115/225 499/2000 DoubleLock-PT-p1s1-LTLFireability-13 71812621 m, 610642 m/sec, 71812621 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 115 secs. Pages in use: 499
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 120/225 521/2000 DoubleLock-PT-p1s1-LTLFireability-13 74870966 m, 611669 m/sec, 74870966 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 120 secs. Pages in use: 521
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 125/225 542/2000 DoubleLock-PT-p1s1-LTLFireability-13 77931126 m, 612032 m/sec, 77931127 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 125 secs. Pages in use: 542
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 130/225 563/2000 DoubleLock-PT-p1s1-LTLFireability-13 80975171 m, 608809 m/sec, 80975172 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 130 secs. Pages in use: 563
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 135/225 584/2000 DoubleLock-PT-p1s1-LTLFireability-13 84020004 m, 608966 m/sec, 84020005 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 135 secs. Pages in use: 584
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 140/225 605/2000 DoubleLock-PT-p1s1-LTLFireability-13 87054718 m, 606942 m/sec, 87054718 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 140 secs. Pages in use: 605
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 145/225 626/2000 DoubleLock-PT-p1s1-LTLFireability-13 90106192 m, 610294 m/sec, 90106193 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 145 secs. Pages in use: 626
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 150/225 648/2000 DoubleLock-PT-p1s1-LTLFireability-13 93157374 m, 610236 m/sec, 93157375 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 150 secs. Pages in use: 648
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 155/225 669/2000 DoubleLock-PT-p1s1-LTLFireability-13 96199694 m, 608464 m/sec, 96199694 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 155 secs. Pages in use: 669
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 160/225 690/2000 DoubleLock-PT-p1s1-LTLFireability-13 99227536 m, 605568 m/sec, 99227536 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 160 secs. Pages in use: 690
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-00: INITIAL false preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-03: CONJ false state space / EG[0m
[[35mlola[0m][.] [1m[32mDoubleLock-PT-p1s1-LTLFireability-11: INITIAL true preprocessing[0m
[[35mlola[0m][.] [1m[31mDoubleLock-PT-p1s1-LTLFireability-15: CONJ false LTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-07: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-09: CONJ 0 2 0 0 3 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-10: CONJ 0 2 0 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-13: CONJ 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleLock-PT-p1s1-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 60 LTL EXCL 165/225 706/2000 DoubleLock-PT-p1s1-LTLFireability-13 101483556 m, 451204 m/sec, 101483556 t fired, .
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 165 secs. Pages in use: 706
[[35mlola[0m][.] # running tasks: 1 of 4. Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 23: 407 Killed $BK_TOOL --conf=/home/mcc/BenchKit/bin/myconf --formula=$BK_EXAMINATION.xml $LOLA_TIMELIMIT $LOLA_MEMLIMIT model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleLock-PT-p1s1"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleLock-PT-p1s1, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134600588"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DoubleLock-PT-p1s1.tgz
mv DoubleLock-PT-p1s1 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;