MCC'2024- Execution of r137-tall-171631134500578

About the Execution of LoLA for DoubleExponent-PT-200

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
10846.224	3600000.00	14202378.00	342.50	???????F??????F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134500578.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleExponent-PT-200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134500578
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 3.9M
-rw-r--r-- 1 mcc users 7.3K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K May 19 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 19 18:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.1K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 89K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.8K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 3.5M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-00
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-01
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-02
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-03
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-04
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-05
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-06
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-07
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-08
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-09
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-10
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2024-11
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2023-12
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2023-13
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2023-14
FORMULA_NAME DoubleExponent-PT-200-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717052821172

FORMULA DoubleExponent-PT-200-CTLFireability-2024-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleExponent-PT-200-CTLFireability-2023-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mCTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-07: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 3 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] LAUNCH task # 65 (type EXCL) for 3 DoubleExponent-PT-200-CTLFireability-2024-01
[[35mlola[0m][I] time limit : 146 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 68 (type EQUN) for 3 DoubleExponent-PT-200-CTLFireability-2024-01
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[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 65 (type EXCL) for DoubleExponent-PT-200-CTLFireability-2024-01
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[[35mlola[0m][I] markings : 8
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[[35mlola[0m][I] time used : 1
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][W] CANCELED task # 68 (type EQUN) for DoubleExponent-PT-200-CTLFireability-2024-01 (obsolete)
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 0 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 0 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 0 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 0 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 0 0 0 0
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[[35mlola[0m][I] time limit : 205 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 70 (type FNDP) for 37 DoubleExponent-PT-200-CTLFireability-2024-11
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[[35mlola[0m][I] LAUNCH task # 71 (type EQUN) for 37 DoubleExponent-PT-200-CTLFireability-2024-11
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[[35mlola[0m][I] time limit : 32000000 sec
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 1 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 3 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 0 0 0
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[[35mlola[0m][.] 70 EF FNDP 4/3481 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 3983 attempts, .
[[35mlola[0m][.] 71 EF STEQ 4/3481 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF EXCL 4/193 1/2000 DoubleExponent-PT-200-CTLFireability-2024-11 29619 m, 5923 m/sec, 29619 t fired, .
[[35mlola[0m][.] 73 EF FNDP 3/1739 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 5195 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 4 3 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 70 EF FNDP 9/3478 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 8567 attempts, .
[[35mlola[0m][.] 71 EF STEQ 9/1735 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF EXCL 9/193 1/2000 DoubleExponent-PT-200-CTLFireability-2024-11 65354 m, 7147 m/sec, 65353 t fired, .
[[35mlola[0m][.] 73 EF FNDP 8/1736 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 12623 attempts, .
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[[35mlola[0m][.] 72 EF EXCL 14/193 2/2000 DoubleExponent-PT-200-CTLFireability-2024-11 105441 m, 8017 m/sec, 105440 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 19/193 2/2000 DoubleExponent-PT-200-CTLFireability-2024-11 142761 m, 7464 m/sec, 142761 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 24/193 3/2000 DoubleExponent-PT-200-CTLFireability-2024-11 183380 m, 8123 m/sec, 183380 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 29/193 4/2000 DoubleExponent-PT-200-CTLFireability-2024-11 222589 m, 7841 m/sec, 222589 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 34/193 4/2000 DoubleExponent-PT-200-CTLFireability-2024-11 260468 m, 7575 m/sec, 260467 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 39/193 5/2000 DoubleExponent-PT-200-CTLFireability-2024-11 297843 m, 7475 m/sec, 297842 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 49/193 6/2000 DoubleExponent-PT-200-CTLFireability-2024-11 374733 m, 7475 m/sec, 374733 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 54/193 6/2000 DoubleExponent-PT-200-CTLFireability-2024-11 413208 m, 7695 m/sec, 413207 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 59/193 7/2000 DoubleExponent-PT-200-CTLFireability-2024-11 451409 m, 7640 m/sec, 451408 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 64/193 7/2000 DoubleExponent-PT-200-CTLFireability-2024-11 486969 m, 7112 m/sec, 486968 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 69/193 8/2000 DoubleExponent-PT-200-CTLFireability-2024-11 522431 m, 7092 m/sec, 522430 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 74/193 8/2000 DoubleExponent-PT-200-CTLFireability-2024-11 560680 m, 7649 m/sec, 560680 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 89/193 10/2000 DoubleExponent-PT-200-CTLFireability-2024-11 674125 m, 7600 m/sec, 674124 t fired, .
[[35mlola[0m][.] 73 EF FNDP 88/1659 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 144225 attempts, .
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[[35mlola[0m][.] 72 EF EXCL 94/193 10/2000 DoubleExponent-PT-200-CTLFireability-2024-11 709525 m, 7080 m/sec, 709524 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 99/193 11/2000 DoubleExponent-PT-200-CTLFireability-2024-11 746727 m, 7440 m/sec, 746727 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 104/193 12/2000 DoubleExponent-PT-200-CTLFireability-2024-11 784622 m, 7579 m/sec, 784621 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 129/193 14/2000 DoubleExponent-PT-200-CTLFireability-2024-11 966513 m, 7247 m/sec, 966512 t fired, .
[[35mlola[0m][.] 73 EF FNDP 128/1619 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 209460 attempts, .
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[[35mlola[0m][.] 72 EF EXCL 134/193 15/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1005404 m, 7778 m/sec, 1005403 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 139/193 15/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1041145 m, 7148 m/sec, 1041144 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 144/193 16/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1080539 m, 7878 m/sec, 1080538 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 149/193 16/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1118437 m, 7579 m/sec, 1118436 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 154/193 17/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1154430 m, 7198 m/sec, 1154429 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 159/193 17/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1190491 m, 7212 m/sec, 1190491 t fired, .
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[[35mlola[0m][.] 72 EF EXCL 169/193 18/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1265102 m, 7508 m/sec, 1265102 t fired, .
[[35mlola[0m][.] 73 EF FNDP 168/1579 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 274639 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 70 EF FNDP 174/3316 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 174355 attempts, .
[[35mlola[0m][.] 71 EF STEQ 174/1573 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 72 EF EXCL 174/193 19/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1302798 m, 7539 m/sec, 1302798 t fired, .
[[35mlola[0m][.] 73 EF FNDP 173/1574 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 282515 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 4 3 0 4 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 EF EXCL 179/193 19/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1339479 m, 7336 m/sec, 1339478 t fired, .
[[35mlola[0m][.] 73 EF FNDP 178/1569 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 290395 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 72 EF EXCL 184/193 20/2000 DoubleExponent-PT-200-CTLFireability-2024-11 1377353 m, 7574 m/sec, 1377352 t fired, .
[[35mlola[0m][.] 73 EF FNDP 183/1564 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 298942 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 194/1553 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 5/205 2/2000 DoubleExponent-PT-200-CTLFireability-2023-15 34327 m, 6865 m/sec, 68654 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 199/3291 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 198/1549 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 323633 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 204/3286 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 15/205 5/2000 DoubleExponent-PT-200-CTLFireability-2023-15 104679 m, 6904 m/sec, 209358 t fired, .
[[35mlola[0m][.] 70 EF FNDP 209/3281 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 209834 attempts, .
[[35mlola[0m][.] 71 EF STEQ 209/3281 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 208/1539 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 340323 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 20/205 6/2000 DoubleExponent-PT-200-CTLFireability-2023-15 139149 m, 6894 m/sec, 278297 t fired, .
[[35mlola[0m][.] 70 EF FNDP 214/3276 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 215225 attempts, .
[[35mlola[0m][.] 71 EF STEQ 214/3276 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 213/1534 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 348902 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 25/205 8/2000 DoubleExponent-PT-200-CTLFireability-2023-15 173820 m, 6934 m/sec, 347639 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 219/3271 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 30/205 9/2000 DoubleExponent-PT-200-CTLFireability-2023-15 207957 m, 6827 m/sec, 415914 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 224/3266 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 229/3261 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 55/205 16/2000 DoubleExponent-PT-200-CTLFireability-2023-15 379797 m, 6571 m/sec, 759593 t fired, .
[[35mlola[0m][.] 70 EF FNDP 249/3241 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 251792 attempts, .
[[35mlola[0m][.] 71 EF STEQ 249/3241 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 248/1499 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 407594 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 60/205 18/2000 DoubleExponent-PT-200-CTLFireability-2023-15 414670 m, 6974 m/sec, 829339 t fired, .
[[35mlola[0m][.] 70 EF FNDP 254/3236 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 256737 attempts, .
[[35mlola[0m][.] 71 EF STEQ 254/3236 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 65/205 19/2000 DoubleExponent-PT-200-CTLFireability-2023-15 449144 m, 6894 m/sec, 898287 t fired, .
[[35mlola[0m][.] 70 EF FNDP 259/3231 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 261686 attempts, .
[[35mlola[0m][.] 71 EF STEQ 259/3231 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 70/205 21/2000 DoubleExponent-PT-200-CTLFireability-2023-15 481305 m, 6432 m/sec, 962609 t fired, .
[[35mlola[0m][.] 70 EF FNDP 264/3226 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 266768 attempts, .
[[35mlola[0m][.] 71 EF STEQ 264/3226 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 70 EF FNDP 269/3221 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 271900 attempts, .
[[35mlola[0m][.] 71 EF STEQ 269/3221 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 274/3216 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 95/205 28/2000 DoubleExponent-PT-200-CTLFireability-2023-15 655157 m, 7096 m/sec, 1310314 t fired, .
[[35mlola[0m][.] 70 EF FNDP 289/3201 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 293014 attempts, .
[[35mlola[0m][.] 71 EF STEQ 289/3201 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 288/1459 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 473287 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 100/205 29/2000 DoubleExponent-PT-200-CTLFireability-2023-15 689918 m, 6952 m/sec, 1379836 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 294/3196 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 293/1454 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 481701 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 105/205 31/2000 DoubleExponent-PT-200-CTLFireability-2023-15 725273 m, 7071 m/sec, 1450545 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 299/3191 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 110/205 32/2000 DoubleExponent-PT-200-CTLFireability-2023-15 760048 m, 6955 m/sec, 1520095 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 304/3186 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 309/3181 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 135/205 40/2000 DoubleExponent-PT-200-CTLFireability-2023-15 936024 m, 7071 m/sec, 1872048 t fired, .
[[35mlola[0m][.] 70 EF FNDP 329/3161 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 334722 attempts, .
[[35mlola[0m][.] 71 EF STEQ 329/3161 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 328/1419 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 540476 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 140/205 41/2000 DoubleExponent-PT-200-CTLFireability-2023-15 970355 m, 6866 m/sec, 1940709 t fired, .
[[35mlola[0m][.] 70 EF FNDP 334/3156 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 340198 attempts, .
[[35mlola[0m][.] 71 EF STEQ 334/3156 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 333/1414 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 548880 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 145/205 42/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1003441 m, 6617 m/sec, 2006882 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 339/3151 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 62 CTL EXCL 150/205 44/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1039197 m, 7151 m/sec, 2078394 t fired, .
[[35mlola[0m][.] 70 EF FNDP 344/3146 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 350704 attempts, .
[[35mlola[0m][.] 71 EF STEQ 344/3146 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 349/3141 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 175/205 51/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1212668 m, 7038 m/sec, 2425335 t fired, .
[[35mlola[0m][.] 70 EF FNDP 369/3121 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 376950 attempts, .
[[35mlola[0m][.] 71 EF STEQ 369/3121 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 368/1379 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 607784 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 180/205 53/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1248573 m, 7181 m/sec, 2497145 t fired, .
[[35mlola[0m][.] 70 EF FNDP 374/3116 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 382211 attempts, .
[[35mlola[0m][.] 71 EF STEQ 374/3116 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 373/1374 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 616178 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 185/205 54/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1283720 m, 7029 m/sec, 2567439 t fired, .
[[35mlola[0m][.] 70 EF FNDP 379/3111 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 387518 attempts, .
[[35mlola[0m][.] 71 EF STEQ 379/3111 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 378/1369 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 624654 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 190/205 56/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1319003 m, 7056 m/sec, 2638005 t fired, .
[[35mlola[0m][.] 70 EF FNDP 384/3106 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 392720 attempts, .
[[35mlola[0m][.] 71 EF STEQ 384/3106 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 383/1364 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 632887 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 62 CTL EXCL 195/205 57/2000 DoubleExponent-PT-200-CTLFireability-2023-15 1353058 m, 6811 m/sec, 2706115 t fired, .
[[35mlola[0m][.] 70 EF FNDP 389/3101 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 397977 attempts, .
[[35mlola[0m][.] 71 EF STEQ 389/3101 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 388/1359 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 641484 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 394/3096 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 404/3086 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][I] time used : 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 5/220 3/2000 DoubleExponent-PT-200-CTLFireability-2023-13 65980 m, 13196 m/sec, 65981 t fired, .
[[35mlola[0m][.] 70 EF FNDP 409/3081 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 418387 attempts, .
[[35mlola[0m][.] 71 EF STEQ 409/3081 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 408/1339 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 673734 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 10/220 6/2000 DoubleExponent-PT-200-CTLFireability-2023-13 136125 m, 14029 m/sec, 136126 t fired, .
[[35mlola[0m][.] 70 EF FNDP 414/3076 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 423478 attempts, .
[[35mlola[0m][.] 71 EF STEQ 414/3076 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 413/1334 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 681616 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 15/220 9/2000 DoubleExponent-PT-200-CTLFireability-2023-13 200456 m, 12866 m/sec, 200457 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 419/3071 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 20/220 12/2000 DoubleExponent-PT-200-CTLFireability-2023-13 267696 m, 13448 m/sec, 267697 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 424/3066 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 429/3061 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 434/3056 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 439/3051 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 45/220 26/2000 DoubleExponent-PT-200-CTLFireability-2023-13 600060 m, 13677 m/sec, 600061 t fired, .
[[35mlola[0m][.] 70 EF FNDP 449/3041 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 458790 attempts, .
[[35mlola[0m][.] 71 EF STEQ 449/3041 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 448/1299 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 738325 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 50/220 28/2000 DoubleExponent-PT-200-CTLFireability-2023-13 667682 m, 13524 m/sec, 667683 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 454/3036 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 453/1294 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 746309 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 55/220 31/2000 DoubleExponent-PT-200-CTLFireability-2023-13 734578 m, 13379 m/sec, 734579 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 459/3031 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 60/220 34/2000 DoubleExponent-PT-200-CTLFireability-2023-13 802317 m, 13547 m/sec, 802318 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 464/3026 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 469/3021 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 85/220 48/2000 DoubleExponent-PT-200-CTLFireability-2023-13 1137523 m, 12363 m/sec, 1137524 t fired, .
[[35mlola[0m][.] 70 EF FNDP 489/3001 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 499728 attempts, .
[[35mlola[0m][.] 71 EF STEQ 489/3001 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 488/1259 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 803479 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 90/220 51/2000 DoubleExponent-PT-200-CTLFireability-2023-13 1208971 m, 14289 m/sec, 1208972 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 494/2996 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 56 CTL EXCL 125/220 71/2000 DoubleExponent-PT-200-CTLFireability-2023-13 1684882 m, 13503 m/sec, 1684882 t fired, .
[[35mlola[0m][.] 70 EF FNDP 529/2961 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 541603 attempts, .
[[35mlola[0m][.] 71 EF STEQ 529/2961 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 528/1219 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 870891 attempts, .
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[[35mlola[0m][.] 56 CTL EXCL 165/220 93/2000 DoubleExponent-PT-200-CTLFireability-2023-13 2224924 m, 13722 m/sec, 2224924 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 569/2921 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 568/1179 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 937542 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 609/2881 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 56 CTL EXCL 210/220 119/2000 DoubleExponent-PT-200-CTLFireability-2023-13 2819107 m, 13537 m/sec, 2819108 t fired, .
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[[35mlola[0m][.] 73 EF FNDP 643/1104 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1057868 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 20/219 11/2000 DoubleExponent-PT-200-CTLFireability-2023-12 260272 m, 13132 m/sec, 260272 t fired, .
[[35mlola[0m][.] 70 EF FNDP 649/2841 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 664733 attempts, .
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[[35mlola[0m][.] 73 EF FNDP 648/1099 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1066021 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 25/219 14/2000 DoubleExponent-PT-200-CTLFireability-2023-12 327633 m, 13472 m/sec, 327633 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 30/219 17/2000 DoubleExponent-PT-200-CTLFireability-2023-12 395823 m, 13638 m/sec, 395822 t fired, .
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[[35mlola[0m][.] 70 EF FNDP 684/2806 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 700269 attempts, .
[[35mlola[0m][.] 71 EF STEQ 684/2806 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 683/1064 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1122746 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 60/219 34/2000 DoubleExponent-PT-200-CTLFireability-2023-12 795885 m, 12875 m/sec, 795885 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 65/219 37/2000 DoubleExponent-PT-200-CTLFireability-2023-12 863800 m, 13583 m/sec, 863799 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 70/219 39/2000 DoubleExponent-PT-200-CTLFireability-2023-12 929523 m, 13144 m/sec, 929522 t fired, .
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[[35mlola[0m][.] 71 EF STEQ 704/2786 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 53 CTL EXCL 95/219 53/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1247096 m, 13384 m/sec, 1247096 t fired, .
[[35mlola[0m][.] 70 EF FNDP 724/2766 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 739822 attempts, .
[[35mlola[0m][.] 71 EF STEQ 724/2766 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 723/1024 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1186275 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 100/219 55/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1313924 m, 13365 m/sec, 1313924 t fired, .
[[35mlola[0m][.] 70 EF FNDP 729/2761 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 745324 attempts, .
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[[35mlola[0m][.] 73 EF FNDP 728/1019 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1194705 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 105/219 58/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1380606 m, 13336 m/sec, 1380606 t fired, .
[[35mlola[0m][.] 70 EF FNDP 734/2756 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 750432 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 110/219 61/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1447503 m, 13379 m/sec, 1447503 t fired, .
[[35mlola[0m][.] 70 EF FNDP 739/2751 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 755504 attempts, .
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[[35mlola[0m][.] 71 EF STEQ 744/2746 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 749/2741 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 754/2736 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] 71 EF STEQ 759/2731 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 53 CTL EXCL 135/219 75/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1777078 m, 13249 m/sec, 1777078 t fired, .
[[35mlola[0m][.] 70 EF FNDP 764/2726 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 781537 attempts, .
[[35mlola[0m][.] 71 EF STEQ 764/2726 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 763/984 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1252411 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 53 CTL EXCL 140/219 77/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1842235 m, 13031 m/sec, 1842235 t fired, .
[[35mlola[0m][.] 70 EF FNDP 769/2721 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 786834 attempts, .
[[35mlola[0m][.] 71 EF STEQ 769/2721 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 768/979 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1260752 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 53 CTL EXCL 145/219 80/2000 DoubleExponent-PT-200-CTLFireability-2023-12 1909843 m, 13521 m/sec, 1909843 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 70 EF FNDP 779/2711 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 797178 attempts, .
[[35mlola[0m][.] 71 EF STEQ 779/2711 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 71 EF STEQ 784/2706 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 783/964 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1285792 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 175/219 97/2000 DoubleExponent-PT-200-CTLFireability-2023-12 2315363 m, 13101 m/sec, 2315363 t fired, .
[[35mlola[0m][.] 70 EF FNDP 804/2686 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 823230 attempts, .
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[[35mlola[0m][.] 73 EF FNDP 803/944 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1318113 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 53 CTL EXCL 180/219 100/2000 DoubleExponent-PT-200-CTLFireability-2023-12 2379345 m, 12796 m/sec, 2379344 t fired, .
[[35mlola[0m][.] 70 EF FNDP 809/2681 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 828732 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
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[[35mlola[0m][.] 53 CTL EXCL 185/219 103/2000 DoubleExponent-PT-200-CTLFireability-2023-12 2444504 m, 13031 m/sec, 2444504 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 53 CTL EXCL 215/219 121/2000 DoubleExponent-PT-200-CTLFireability-2023-12 2861293 m, 14305 m/sec, 2861292 t fired, .
[[35mlola[0m][.] 70 EF FNDP 844/2646 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 865378 attempts, .
[[35mlola[0m][.] 71 EF STEQ 844/2646 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 843/904 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1384771 attempts, .
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[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 2 2 0 5 1 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 70 EF FNDP 849/2641 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 870540 attempts, .
[[35mlola[0m][.] 71 EF STEQ 849/2641 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 848/899 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1393332 attempts, .
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[[35mlola[0m][I] LAUNCH task # 50 (type EXCL) for 37 DoubleExponent-PT-200-CTLFireability-2024-11
[[35mlola[0m][I] time limit : 219 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] FINISHED task # 50 (type EXCL) for DoubleExponent-PT-200-CTLFireability-2024-11
[[35mlola[0m][I] result : false
[[35mlola[0m][I] markings : 25
[[35mlola[0m][I] fired transitions : 25
[[35mlola[0m][I] time used : 0
[[35mlola[0m][I] memory pages used : 1
[[35mlola[0m][I] LAUNCH task # 32 (type EXCL) for 31 DoubleExponent-PT-200-CTLFireability-2024-09
[[35mlola[0m][I] time limit : 263 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 5/263 2/2000 DoubleExponent-PT-200-CTLFireability-2024-09 36749 m, 7349 m/sec, 73498 t fired, .
[[35mlola[0m][.] 70 EF FNDP 854/2636 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 875824 attempts, .
[[35mlola[0m][.] 71 EF STEQ 854/2636 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 853/894 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1401357 attempts, .
[[35mlola[0m][.]
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[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 10/263 4/2000 DoubleExponent-PT-200-CTLFireability-2024-09 72888 m, 7227 m/sec, 145776 t fired, .
[[35mlola[0m][.] 70 EF FNDP 859/2631 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 880934 attempts, .
[[35mlola[0m][.] 71 EF STEQ 859/2631 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 858/889 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1409656 attempts, .
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[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 15/263 5/2000 DoubleExponent-PT-200-CTLFireability-2024-09 107725 m, 6967 m/sec, 215450 t fired, .
[[35mlola[0m][.] 70 EF FNDP 864/2626 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 886058 attempts, .
[[35mlola[0m][.] 71 EF STEQ 864/2626 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 863/884 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1417924 attempts, .
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[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 20/263 6/2000 DoubleExponent-PT-200-CTLFireability-2024-09 143247 m, 7104 m/sec, 286495 t fired, .
[[35mlola[0m][.] 70 EF FNDP 869/2621 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 891131 attempts, .
[[35mlola[0m][.] 71 EF STEQ 869/2621 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 868/879 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1426326 attempts, .
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[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 32 CTL EXCL 25/263 8/2000 DoubleExponent-PT-200-CTLFireability-2024-09 179859 m, 7322 m/sec, 359718 t fired, .
[[35mlola[0m][.] 70 EF FNDP 874/2616 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 896237 attempts, .
[[35mlola[0m][.] 71 EF STEQ 874/2616 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
[[35mlola[0m][.] 73 EF FNDP 873/874 0/5 DoubleExponent-PT-200-CTLFireability-2024-10 1434833 attempts, .
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[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2024-07: CTL false CTL model checker[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-200-CTLFireability-2023-14: CTL false CTL model checker[0m
[[35mlola[0m][.]
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-00: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-03: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 2 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 32 CTL EXCL 30/263 10/2000 DoubleExponent-PT-200-CTLFireability-2024-09 215110 m, 7050 m/sec, 430220 t fired, .
[[35mlola[0m][.] 70 EF FNDP 879/2611 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 901289 attempts, .
[[35mlola[0m][.] 71 EF STEQ 879/2611 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 sara not yet started (preprocessing).
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[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] FINISHED task # 73 (type FNDP) for DoubleExponent-PT-200-CTLFireability-2024-10
[[35mlola[0m][I] result : unknown
[[35mlola[0m][I] tried executions : 1442828
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 35/263 11/2000 DoubleExponent-PT-200-CTLFireability-2024-09 250406 m, 7059 m/sec, 500812 t fired, .
[[35mlola[0m][.] 70 EF FNDP 884/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 906344 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 40/263 12/2000 DoubleExponent-PT-200-CTLFireability-2024-09 286507 m, 7220 m/sec, 573014 t fired, .
[[35mlola[0m][.] 70 EF FNDP 889/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 911437 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 45/263 14/2000 DoubleExponent-PT-200-CTLFireability-2024-09 322314 m, 7161 m/sec, 644629 t fired, .
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[[35mlola[0m][.] 70 EF FNDP 924/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 946854 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 150/263 45/2000 DoubleExponent-PT-200-CTLFireability-2024-09 1069075 m, 6700 m/sec, 2138151 t fired, .
[[35mlola[0m][.] 70 EF FNDP 999/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1024312 attempts, .
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[[35mlola[0m][.] 70 EF FNDP 1039/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1065865 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 230/263 69/2000 DoubleExponent-PT-200-CTLFireability-2024-09 1631569 m, 7115 m/sec, 3263138 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1079/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1106584 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 32 CTL EXCL 235/263 70/2000 DoubleExponent-PT-200-CTLFireability-2024-09 1665938 m, 6873 m/sec, 3331876 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1084/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1111635 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 70 EF FNDP 1089/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1116465 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 5/263 2/2000 DoubleExponent-PT-200-CTLFireability-2024-08 33915 m, 6783 m/sec, 67829 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1119/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1146757 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 10/263 3/2000 DoubleExponent-PT-200-CTLFireability-2024-08 65646 m, 6346 m/sec, 131292 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1124/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1151833 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 45/263 13/2000 DoubleExponent-PT-200-CTLFireability-2024-08 299667 m, 6970 m/sec, 599334 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1159/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1186449 attempts, .
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[[35mlola[0m][.] 29 CTL EXCL 50/263 14/2000 DoubleExponent-PT-200-CTLFireability-2024-08 332715 m, 6609 m/sec, 665430 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 85/263 24/2000 DoubleExponent-PT-200-CTLFireability-2024-08 568965 m, 6791 m/sec, 1137929 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1199/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1228326 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 125/263 36/2000 DoubleExponent-PT-200-CTLFireability-2024-08 842500 m, 7100 m/sec, 1684999 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1239/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1269647 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 165/263 47/2000 DoubleExponent-PT-200-CTLFireability-2024-08 1111403 m, 6178 m/sec, 2222805 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1279/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1311166 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 245/263 69/2000 DoubleExponent-PT-200-CTLFireability-2024-08 1629449 m, 6385 m/sec, 3258898 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1359/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1391281 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.]
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[[35mlola[0m][.] 29 CTL EXCL 250/263 70/2000 DoubleExponent-PT-200-CTLFireability-2024-08 1661958 m, 6501 m/sec, 3323915 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1364/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1396114 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 29 CTL EXCL 255/263 71/2000 DoubleExponent-PT-200-CTLFireability-2024-08 1694920 m, 6592 m/sec, 3389839 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1369/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1401223 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-01: DISJ 0 1 0 0 3 0 0 1
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 70 EF FNDP 1374/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1406149 attempts, .
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[[35mlola[0m][.] 70 EF FNDP 1379/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1410933 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 17 CTL EXCL 5/300 3/2000 DoubleExponent-PT-200-CTLFireability-2024-04 70224 m, 14044 m/sec, 70252 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1384/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1415953 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 17 CTL EXCL 15/300 9/2000 DoubleExponent-PT-200-CTLFireability-2024-04 205420 m, 13509 m/sec, 205448 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1394/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1426205 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 17 CTL EXCL 55/300 30/2000 DoubleExponent-PT-200-CTLFireability-2024-04 718004 m, 12705 m/sec, 718031 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1434/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1466196 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-10: EF 0 1 1 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2024-11: DISJ 0 0 2 0 6 1 0 2
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-15: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] 17 CTL EXCL 95/300 52/2000 DoubleExponent-PT-200-CTLFireability-2024-04 1234373 m, 13175 m/sec, 1234401 t fired, .
[[35mlola[0m][.] 70 EF FNDP 1474/3485 0/5 DoubleExponent-PT-200-CTLFireability-2024-11 1505850 attempts, .
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-13: CTL 0 0 0 0 1 1 0 0
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[[35mlola[0m][.] DoubleExponent-PT-200-CTLFireability-2023-12: CTL 0 0 0 0 1 1 0 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleExponent-PT-200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134500578"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-200.tgz
mv DoubleExponent-PT-200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;