MCC'2024- Execution of r137-tall-171631134500572

About the Execution of LoLA for DoubleExponent-PT-100

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	2540372.00	0.00	0.00	?????????????F??	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134500572.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleExponent-PT-100, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134500572
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 19 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.8M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-00
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-01
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-02
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-03
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-04
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-05
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-06
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-07
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-08
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-09
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-10
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-11
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-12
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-13
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-14
FORMULA_NAME DoubleExponent-PT-100-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1717050949191

FORMULA DoubleExponent-PT-100-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717053489563

--------------------
content from stderr:

[[35mlola[0m][I] LoLA will run for 3600 seconds at most ([1m[36m--timelimit[0m)
[[35mlola[0m][W] [1m[33munknown unit in memory specification: using default[0m
[[35mlola[0m][I] MEM LIMIT 5
[[35mlola[0m][I] NET
[[35mlola[0m][I] reading [1m[34mnet[0m from [4m[34mmodel.pnml[0m
[[35mlola[0m][I] input: PNML file ([1m[36m--pnmlnet[0m)
[[35mlola[0m][I] reading pnml
[[35mlola[0m][I] PNML file contains place/transition net
[[35mlola[0m][I] closed [1m[34mnet[0m file [4m[34mmodel.pnml[0m
[[35mlola[0m][I] finished parsing
[[35mlola[0m][I] Reading formula.
[[35mlola[0m][I] Using XML format ([1m[36m--xmlformula[0m)
[[35mlola[0m][I] reading XML formula
[[35mlola[0m][I] reading [1m[34mformula[0m from [4m[34mLTLFireability.xml[0m
[[35mlola[0m][I] Rule S: 0 transitions removed,0 places removed
[[35mlola[0m][I] LAUNCH task # 44 (type CNST) for 43 DoubleExponent-PT-100-LTLFireability-13
[[35mlola[0m][I] time limit : 0 sec
[[35mlola[0m][I] memory limit: 0 pages
[[35mlola[0m][I] FINISHED task # 44 (type CNST) for DoubleExponent-PT-100-LTLFireability-13
[[35mlola[0m][I] result : false
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-100-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 0 0 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 0 0 0 0 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.]
[[35mlola[0m][.] Time elapsed: 7 secs. Pages in use: 0
[[35mlola[0m][.] # running tasks: 0 of 4. Visible: 16
[[35mlola[0m][I] LAUNCH task # 55 (type EXCL) for 12 DoubleExponent-PT-100-LTLFireability-04
[[35mlola[0m][I] time limit : 224 sec
[[35mlola[0m][I] memory limit: 2000 pages
[[35mlola[0m][I] LAUNCH task # 53 (type FNDP) for 12 DoubleExponent-PT-100-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] LAUNCH task # 54 (type EQUN) for 12 DoubleExponent-PT-100-LTLFireability-04
[[35mlola[0m][I] time limit : 32000000 sec
[[35mlola[0m][I] memory limit: 5 pages
[[35mlola[0m][I] [1m FINISHED FORMULA: CATEGORY VALUE PRODUCED BY[0m
[[35mlola[0m][.] [1m[31mDoubleExponent-PT-100-LTLFireability-13: INITIAL false preprocessing[0m
[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 0 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 0 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 2/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 --
[[35mlola[0m][.] 54 EF STEQ 2/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 55 EF EXCL 2/224 1/2000 DoubleExponent-PT-100-LTLFireability-04 49074 m, 9814 m/sec, 49073 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 1 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 7/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 12234 attempts, .
[[35mlola[0m][.] 54 EF STEQ 7/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 55 EF EXCL 7/224 3/2000 DoubleExponent-PT-100-LTLFireability-04 155198 m, 21224 m/sec, 155197 t fired, .
[[35mlola[0m][.]
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[[35mlola[0m][.]
[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 1 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 12/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 33485 attempts, .
[[35mlola[0m][.] 54 EF STEQ 12/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 55 EF EXCL 12/224 4/2000 DoubleExponent-PT-100-LTLFireability-04 292959 m, 27552 m/sec, 292958 t fired, .
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[[35mlola[0m][.] [1m PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS[0m
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 1 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 17/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 54767 attempts, .
[[35mlola[0m][.] 54 EF STEQ 17/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 55 EF EXCL 17/224 6/2000 DoubleExponent-PT-100-LTLFireability-04 427729 m, 26954 m/sec, 427729 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 1 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-10: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-15: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.]
[[35mlola[0m][.] [1m TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS[0m
[[35mlola[0m][.] 53 EF FNDP 22/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 75725 attempts, .
[[35mlola[0m][.] 54 EF STEQ 22/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 sara not yet started (preprocessing).
[[35mlola[0m][.] 55 EF EXCL 22/224 8/2000 DoubleExponent-PT-100-LTLFireability-04 564287 m, 27311 m/sec, 564286 t fired, .
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[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-04: CONJ 0 1 3 0 2 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
[[35mlola[0m][.] DoubleExponent-PT-100-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
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[[35mlola[0m][.] 41 LTL EXCL 5/257 5/2000 DoubleExponent-PT-100-LTLFireability-12 172631 m, 34526 m/sec, 190925 t fired, .
[[35mlola[0m][.] 53 EF FNDP 247/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 980983 attempts, .
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[[35mlola[0m][.] 41 LTL EXCL 10/257 9/2000 DoubleExponent-PT-100-LTLFireability-12 345871 m, 34648 m/sec, 382592 t fired, .
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[[35mlola[0m][.] 41 LTL EXCL 15/257 13/2000 DoubleExponent-PT-100-LTLFireability-12 522995 m, 35424 m/sec, 578551 t fired, .
[[35mlola[0m][.] 53 EF FNDP 257/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 1022166 attempts, .
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[[35mlola[0m][.] 41 LTL EXCL 20/257 18/2000 DoubleExponent-PT-100-LTLFireability-12 699979 m, 35396 m/sec, 774369 t fired, .
[[35mlola[0m][.] 53 EF FNDP 262/3590 0/5 DoubleExponent-PT-100-LTLFireability-04 1042907 attempts, .
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[[35mlola[0m][.] 41 LTL EXCL 25/257 22/2000 DoubleExponent-PT-100-LTLFireability-12 875617 m, 35127 m/sec, 968631 t fired, .
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[[35mlola[0m][.] 41 LTL EXCL 30/257 26/2000 DoubleExponent-PT-100-LTLFireability-12 1052543 m, 35385 m/sec, 1164372 t fired, .
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[[35mlola[0m][.] 41 LTL EXCL 35/257 31/2000 DoubleExponent-PT-100-LTLFireability-12 1226710 m, 34833 m/sec, 1357057 t fired, .
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[[35mlola[0m][.] 41 LTL EXCL 40/257 35/2000 DoubleExponent-PT-100-LTLFireability-12 1401625 m, 34983 m/sec, 1550587 t fired, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-100"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleExponent-PT-100, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134500572"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-100.tgz
mv DoubleExponent-PT-100 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;