fond
Model Checking Contest 2024
14th edition, Geneva, Switzerland, June 25, 2024
Execution of r137-tall-171631134500570
Last Updated
July 7, 2024

About the Execution of LoLA for DoubleExponent-PT-100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
0.000 2071336.00 0.00 0.00 ???F??????T????? normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2024-input.r137-tall-171631134500570.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2024-input.qcow2 backing_fmt=qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5568
Executing tool lola
Input is DoubleExponent-PT-100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-171631134500570
=====================================================================


--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.2M
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K May 14 13:22 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K May 14 13:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K May 14 13:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 18 16:42 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.2K May 18 16:42 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K May 19 07:09 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K May 19 15:47 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 19 07:17 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K May 19 18:15 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K May 14 13:22 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K May 14 13:22 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.2K May 14 13:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K May 14 13:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 19 07:11 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K May 19 15:25 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 18 16:42 equiv_col
-rw-r--r-- 1 mcc users 4 May 18 16:42 instance
-rw-r--r-- 1 mcc users 6 May 18 16:42 iscolored
-rw-r--r-- 1 mcc users 1.8M May 18 16:42 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-00
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-01
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-02
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-03
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-04
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-05
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-06
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-07
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-08
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-09
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-10
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2024-11
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2023-12
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2023-13
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2023-14
FORMULA_NAME DoubleExponent-PT-100-CTLFireability-2023-15

=== Now, execution of the tool begins

BK_START 1717050740125

FORMULA DoubleExponent-PT-100-CTLFireability-2024-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DoubleExponent-PT-100-CTLFireability-2024-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1717052811461

--------------------
content from stderr:

[lola][I] LoLA will run for 3600 seconds at most (--timelimit)
[lola][W] unknown unit in memory specification: using default
[lola][I] MEM LIMIT 5
[lola][I] NET
[lola][I] reading net from model.pnml
[lola][I] input: PNML file (--pnmlnet)
[lola][I] reading pnml
[lola][I] PNML file contains place/transition net
[lola][I] closed net file model.pnml
[lola][I] finished parsing
[lola][I] Reading formula.
[lola][I] Using XML format (--xmlformula)
[lola][I] reading XML formula
[lola][I] reading formula from CTLFireability.xml
[lola][I] Rule S: 0 transitions removed,0 places removed
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.]
[lola][.] Time elapsed: 48 secs. Pages in use: 0
[lola][.] # running tasks: 0 of 4. Visible: 16
[lola][I] LAUNCH task # 31 (type EXCL) for 30 DoubleExponent-PT-100-CTLFireability-2024-10
[lola][I] time limit : 208 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 31 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-10
[lola][I] result : true
[lola][I] markings : 8
[lola][I] fired transitions : 8
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 53 (type EXCL) for 9 DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] time limit : 221 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 56 (type EQUN) for 9 DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 58 (type EQUN) for 9 DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 63 (type EQUN) for 43 DoubleExponent-PT-100-CTLFireability-2023-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 53 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] result : true
[lola][I] markings : 8
[lola][I] fired transitions : 7
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][W] CANCELED task # 56 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2024-03 (obsolete)
[lola][W] CANCELED task # 58 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2024-03 (obsolete)
[lola][I] LAUNCH task # 66 (type EXCL) for 0 DoubleExponent-PT-100-CTLFireability-2024-00
[lola][I] time limit : 236 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 69 (type EQUN) for 0 DoubleExponent-PT-100-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] LAUNCH task # 71 (type EQUN) for 0 DoubleExponent-PT-100-CTLFireability-2024-00
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 56 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I] FINISHED task # 69 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2024-00
[lola][I] result : unknown
[lola][I] LAUNCH task # 65 (type EQUN) for 43 DoubleExponent-PT-100-CTLFireability-2023-13
[lola][I] time limit : 32000000 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 58 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2024-03
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 0 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 2 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 0 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 0 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 6/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 65 EF STEQ 0/3543 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 6/236 2/2000 DoubleExponent-PT-100-CTLFireability-2024-00 75183 m, 15036 m/sec, 75182 t fired, .
[lola][.] 71 EF STEQ 6/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 57 secs. Pages in use: 2
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] FINISHED task # 65 (type EQUN) for DoubleExponent-PT-100-CTLFireability-2023-13
[lola][I] result : unknown
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 11/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 11/236 3/2000 DoubleExponent-PT-100-CTLFireability-2024-00 176492 m, 20261 m/sec, 176491 t fired, .
[lola][.] 71 EF STEQ 11/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 62 secs. Pages in use: 3
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 16/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 16/236 4/2000 DoubleExponent-PT-100-CTLFireability-2024-00 290414 m, 22784 m/sec, 290413 t fired, .
[lola][.] 71 EF STEQ 16/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 67 secs. Pages in use: 4
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 21/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 21/236 6/2000 DoubleExponent-PT-100-CTLFireability-2024-00 404547 m, 22826 m/sec, 404547 t fired, .
[lola][.] 71 EF STEQ 21/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 72 secs. Pages in use: 6
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 26/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 26/236 7/2000 DoubleExponent-PT-100-CTLFireability-2024-00 518632 m, 22817 m/sec, 518631 t fired, .
[lola][.] 71 EF STEQ 26/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 77 secs. Pages in use: 7
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 31/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 31/236 9/2000 DoubleExponent-PT-100-CTLFireability-2024-00 636448 m, 23563 m/sec, 636447 t fired, .
[lola][.] 71 EF STEQ 31/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 82 secs. Pages in use: 9
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 36/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 36/236 11/2000 DoubleExponent-PT-100-CTLFireability-2024-00 755473 m, 23805 m/sec, 755472 t fired, .
[lola][.] 71 EF STEQ 36/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 87 secs. Pages in use: 11
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 41/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 41/236 12/2000 DoubleExponent-PT-100-CTLFireability-2024-00 874351 m, 23775 m/sec, 874351 t fired, .
[lola][.] 71 EF STEQ 41/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 92 secs. Pages in use: 12
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 46/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 46/236 14/2000 DoubleExponent-PT-100-CTLFireability-2024-00 992975 m, 23724 m/sec, 992974 t fired, .
[lola][.] 71 EF STEQ 46/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 97 secs. Pages in use: 14
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 51/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 51/236 15/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1111259 m, 23656 m/sec, 1111258 t fired, .
[lola][.] 71 EF STEQ 51/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 102 secs. Pages in use: 15
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 56/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 56/236 17/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1229539 m, 23656 m/sec, 1229538 t fired, .
[lola][.] 71 EF STEQ 56/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 107 secs. Pages in use: 17
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 61/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 61/236 19/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1347924 m, 23677 m/sec, 1347924 t fired, .
[lola][.] 71 EF STEQ 61/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 112 secs. Pages in use: 19
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 66/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 66/236 20/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1466480 m, 23711 m/sec, 1466479 t fired, .
[lola][.] 71 EF STEQ 66/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 117 secs. Pages in use: 20
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 71/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 71/236 22/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1584900 m, 23684 m/sec, 1584900 t fired, .
[lola][.] 71 EF STEQ 71/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 122 secs. Pages in use: 22
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 76/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 76/236 24/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1703228 m, 23665 m/sec, 1703227 t fired, .
[lola][.] 71 EF STEQ 76/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 127 secs. Pages in use: 24
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 81/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 81/236 25/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1821450 m, 23644 m/sec, 1821450 t fired, .
[lola][.] 71 EF STEQ 81/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 132 secs. Pages in use: 25
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 86/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 86/236 27/2000 DoubleExponent-PT-100-CTLFireability-2024-00 1939510 m, 23612 m/sec, 1939509 t fired, .
[lola][.] 71 EF STEQ 86/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 137 secs. Pages in use: 27
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 91/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 91/236 28/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2053393 m, 22776 m/sec, 2053392 t fired, .
[lola][.] 71 EF STEQ 91/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 142 secs. Pages in use: 28
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 96/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 96/236 30/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2167075 m, 22736 m/sec, 2167075 t fired, .
[lola][.] 71 EF STEQ 96/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 147 secs. Pages in use: 30
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 101/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 101/236 31/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2281130 m, 22811 m/sec, 2281129 t fired, .
[lola][.] 71 EF STEQ 101/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 152 secs. Pages in use: 31
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 106/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 106/236 33/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2395315 m, 22837 m/sec, 2395314 t fired, .
[lola][.] 71 EF STEQ 106/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 157 secs. Pages in use: 33
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 111/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 111/236 34/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2509702 m, 22877 m/sec, 2509701 t fired, .
[lola][.] 71 EF STEQ 111/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 162 secs. Pages in use: 34
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 116/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 116/236 36/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2623801 m, 22819 m/sec, 2623801 t fired, .
[lola][.] 71 EF STEQ 116/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 167 secs. Pages in use: 36
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 121/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 121/236 37/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2739288 m, 23097 m/sec, 2739288 t fired, .
[lola][.] 71 EF STEQ 121/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 172 secs. Pages in use: 37
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 126/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 126/236 39/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2856207 m, 23383 m/sec, 2856206 t fired, .
[lola][.] 71 EF STEQ 126/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 177 secs. Pages in use: 39
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 131/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 131/236 41/2000 DoubleExponent-PT-100-CTLFireability-2024-00 2971589 m, 23076 m/sec, 2971588 t fired, .
[lola][.] 71 EF STEQ 131/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 182 secs. Pages in use: 41
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 136/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 136/236 42/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3087745 m, 23231 m/sec, 3087744 t fired, .
[lola][.] 71 EF STEQ 136/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 187 secs. Pages in use: 42
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 141/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 141/236 44/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3204238 m, 23298 m/sec, 3204237 t fired, .
[lola][.] 71 EF STEQ 141/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 192 secs. Pages in use: 44
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 146/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 146/236 45/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3320662 m, 23284 m/sec, 3320661 t fired, .
[lola][.] 71 EF STEQ 146/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 197 secs. Pages in use: 45
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 151/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 151/236 47/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3437594 m, 23386 m/sec, 3437593 t fired, .
[lola][.] 71 EF STEQ 151/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 202 secs. Pages in use: 47
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 156/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 156/236 48/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3554164 m, 23314 m/sec, 3554163 t fired, .
[lola][.] 71 EF STEQ 156/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 207 secs. Pages in use: 48
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 161/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 161/236 50/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3670373 m, 23241 m/sec, 3670372 t fired, .
[lola][.] 71 EF STEQ 161/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 212 secs. Pages in use: 50
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 166/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 166/236 51/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3785552 m, 23035 m/sec, 3785551 t fired, .
[lola][.] 71 EF STEQ 166/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 217 secs. Pages in use: 51
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 171/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 171/236 53/2000 DoubleExponent-PT-100-CTLFireability-2024-00 3902683 m, 23426 m/sec, 3902683 t fired, .
[lola][.] 71 EF STEQ 171/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 222 secs. Pages in use: 53
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 176/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 176/236 54/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4020646 m, 23592 m/sec, 4020646 t fired, .
[lola][.] 71 EF STEQ 176/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 227 secs. Pages in use: 54
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 181/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 181/236 56/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4137890 m, 23448 m/sec, 4137889 t fired, .
[lola][.] 71 EF STEQ 181/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 232 secs. Pages in use: 56
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 186/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 186/236 57/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4254710 m, 23364 m/sec, 4254710 t fired, .
[lola][.] 71 EF STEQ 186/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 237 secs. Pages in use: 57
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 191/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 191/236 59/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4372688 m, 23595 m/sec, 4372687 t fired, .
[lola][.] 71 EF STEQ 191/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 242 secs. Pages in use: 59
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 196/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 196/236 61/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4490391 m, 23540 m/sec, 4490390 t fired, .
[lola][.] 71 EF STEQ 196/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 247 secs. Pages in use: 61
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 201/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 201/236 62/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4607388 m, 23399 m/sec, 4607388 t fired, .
[lola][.] 71 EF STEQ 201/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 252 secs. Pages in use: 62
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 206/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 206/236 64/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4724502 m, 23422 m/sec, 4724501 t fired, .
[lola][.] 71 EF STEQ 206/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 257 secs. Pages in use: 64
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 211/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 211/236 65/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4840980 m, 23295 m/sec, 4840979 t fired, .
[lola][.] 71 EF STEQ 211/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 262 secs. Pages in use: 65
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 216/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 216/236 67/2000 DoubleExponent-PT-100-CTLFireability-2024-00 4955604 m, 22924 m/sec, 4955603 t fired, .
[lola][.] 71 EF STEQ 216/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 267 secs. Pages in use: 67
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 221/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 221/236 68/2000 DoubleExponent-PT-100-CTLFireability-2024-00 5072108 m, 23300 m/sec, 5072107 t fired, .
[lola][.] 71 EF STEQ 221/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 272 secs. Pages in use: 68
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 226/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 226/236 70/2000 DoubleExponent-PT-100-CTLFireability-2024-00 5189886 m, 23555 m/sec, 5189885 t fired, .
[lola][.] 71 EF STEQ 226/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 277 secs. Pages in use: 70
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 231/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 231/236 71/2000 DoubleExponent-PT-100-CTLFireability-2024-00 5308130 m, 23648 m/sec, 5308130 t fired, .
[lola][.] 71 EF STEQ 231/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 282 secs. Pages in use: 71
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 236/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 236/236 73/2000 DoubleExponent-PT-100-CTLFireability-2024-00 5425759 m, 23525 m/sec, 5425759 t fired, .
[lola][.] 71 EF STEQ 236/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 287 secs. Pages in use: 73
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][W] CANCELED task # 66 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-00 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 1 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 241/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 241/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 292 secs. Pages in use: 74
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 50 (type EXCL) for 49 DoubleExponent-PT-100-CTLFireability-2023-15
[lola][I] time limit : 236 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 66 (type EXCL) for 0 DoubleExponent-PT-100-CTLFireability-2024-00
[lola][I] time limit : 3308 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 50 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2023-15
[lola][I] result : false
[lola][I] markings : 3672
[lola][I] fired transitions : 3708
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 246/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 5/236 2/5 DoubleExponent-PT-100-CTLFireability-2024-00 107462 m, -1063659 m/sec, 107461 t fired, .
[lola][.] 71 EF STEQ 246/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 297 secs. Pages in use: 78
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 251/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 10/236 3/5 DoubleExponent-PT-100-CTLFireability-2024-00 219430 m, 22393 m/sec, 219430 t fired, .
[lola][.] 71 EF STEQ 251/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 302 secs. Pages in use: 80
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 2 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 256/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 66 EFEG EXCL 15/236 5/5 DoubleExponent-PT-100-CTLFireability-2024-00 329777 m, 22069 m/sec, 329776 t fired, .
[lola][.] 71 EF STEQ 256/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 307 secs. Pages in use: 84
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] CANCELED task # 66 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-00 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ 0 2 0 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL 0 1 0 0 1 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 261/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 261/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 312 secs. Pages in use: 85
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 47 (type EXCL) for 46 DoubleExponent-PT-100-CTLFireability-2023-14
[lola][I] time limit : 252 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 47 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2023-14
[lola][I] result : false
[lola][I] markings : 25
[lola][I] fired transitions : 50
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 41 (type EXCL) for 36 DoubleExponent-PT-100-CTLFireability-2023-12
[lola][I] time limit : 274 sec
[lola][I] memory limit: 2000 pages
[lola][I] FINISHED task # 41 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2023-12
[lola][I] result : false
[lola][I] markings : 1
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I] LAUNCH task # 28 (type EXCL) for 27 DoubleExponent-PT-100-CTLFireability-2024-09
[lola][I] time limit : 328 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 5/328 4/2000 DoubleExponent-PT-100-CTLFireability-2024-09 168609 m, 33721 m/sec, 168609 t fired, .
[lola][.] 63 EF STEQ 266/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 266/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 317 secs. Pages in use: 86
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 10/328 8/2000 DoubleExponent-PT-100-CTLFireability-2024-09 337568 m, 33791 m/sec, 337567 t fired, .
[lola][.] 63 EF STEQ 271/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 271/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 322 secs. Pages in use: 92
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 15/328 12/2000 DoubleExponent-PT-100-CTLFireability-2024-09 507007 m, 33887 m/sec, 507007 t fired, .
[lola][.] 63 EF STEQ 276/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 276/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 327 secs. Pages in use: 97
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 20/328 15/2000 DoubleExponent-PT-100-CTLFireability-2024-09 676204 m, 33839 m/sec, 676204 t fired, .
[lola][.] 63 EF STEQ 281/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 281/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 332 secs. Pages in use: 102
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 25/328 19/2000 DoubleExponent-PT-100-CTLFireability-2024-09 845471 m, 33853 m/sec, 845470 t fired, .
[lola][.] 63 EF STEQ 286/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 286/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 337 secs. Pages in use: 107
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 30/328 23/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1014506 m, 33807 m/sec, 1014506 t fired, .
[lola][.] 63 EF STEQ 291/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 291/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 342 secs. Pages in use: 113
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 35/328 27/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1183814 m, 33861 m/sec, 1183814 t fired, .
[lola][.] 63 EF STEQ 296/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 296/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 347 secs. Pages in use: 118
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 40/328 30/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1352157 m, 33668 m/sec, 1352157 t fired, .
[lola][.] 63 EF STEQ 301/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 301/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 352 secs. Pages in use: 123
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 45/328 34/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1517425 m, 33053 m/sec, 1517425 t fired, .
[lola][.] 63 EF STEQ 306/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 306/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 357 secs. Pages in use: 128
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 50/328 38/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1682734 m, 33061 m/sec, 1682734 t fired, .
[lola][.] 63 EF STEQ 311/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 311/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 362 secs. Pages in use: 134
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 55/328 41/2000 DoubleExponent-PT-100-CTLFireability-2024-09 1848674 m, 33188 m/sec, 1848674 t fired, .
[lola][.] 63 EF STEQ 316/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 316/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 367 secs. Pages in use: 138
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 60/328 45/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2015324 m, 33330 m/sec, 2015324 t fired, .
[lola][.] 63 EF STEQ 321/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 321/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 372 secs. Pages in use: 144
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 65/328 49/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2184380 m, 33811 m/sec, 2184380 t fired, .
[lola][.] 63 EF STEQ 326/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 326/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 377 secs. Pages in use: 150
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 70/328 53/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2353054 m, 33734 m/sec, 2353054 t fired, .
[lola][.] 63 EF STEQ 331/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 331/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 382 secs. Pages in use: 155
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 75/328 57/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2519417 m, 33272 m/sec, 2519416 t fired, .
[lola][.] 63 EF STEQ 336/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 336/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 387 secs. Pages in use: 161
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 80/328 60/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2679168 m, 31950 m/sec, 2679168 t fired, .
[lola][.] 63 EF STEQ 341/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 341/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 392 secs. Pages in use: 165
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 85/328 64/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2838705 m, 31907 m/sec, 2838705 t fired, .
[lola][.] 63 EF STEQ 346/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 346/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 397 secs. Pages in use: 171
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 90/328 68/2000 DoubleExponent-PT-100-CTLFireability-2024-09 2998751 m, 32009 m/sec, 2998751 t fired, .
[lola][.] 63 EF STEQ 351/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 351/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 402 secs. Pages in use: 176
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 95/328 72/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3162075 m, 32664 m/sec, 3162075 t fired, .
[lola][.] 63 EF STEQ 356/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 356/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 407 secs. Pages in use: 182
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 100/328 75/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3324213 m, 32427 m/sec, 3324212 t fired, .
[lola][.] 63 EF STEQ 361/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 361/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 412 secs. Pages in use: 186
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 105/328 79/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3491906 m, 33538 m/sec, 3491906 t fired, .
[lola][.] 63 EF STEQ 366/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 366/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 417 secs. Pages in use: 192
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 110/328 83/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3659853 m, 33589 m/sec, 3659853 t fired, .
[lola][.] 63 EF STEQ 371/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 371/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 422 secs. Pages in use: 197
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 115/328 86/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3827505 m, 33530 m/sec, 3827505 t fired, .
[lola][.] 63 EF STEQ 376/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 376/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 427 secs. Pages in use: 202
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 120/328 90/2000 DoubleExponent-PT-100-CTLFireability-2024-09 3988940 m, 32287 m/sec, 3988940 t fired, .
[lola][.] 63 EF STEQ 381/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 381/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 432 secs. Pages in use: 207
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 125/328 93/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4151038 m, 32419 m/sec, 4151037 t fired, .
[lola][.] 63 EF STEQ 386/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 386/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 437 secs. Pages in use: 212
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 130/328 97/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4312173 m, 32227 m/sec, 4312173 t fired, .
[lola][.] 63 EF STEQ 391/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 391/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 442 secs. Pages in use: 217
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 135/328 101/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4475263 m, 32618 m/sec, 4475263 t fired, .
[lola][.] 63 EF STEQ 396/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 396/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 447 secs. Pages in use: 223
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 140/328 104/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4641554 m, 33258 m/sec, 4641554 t fired, .
[lola][.] 63 EF STEQ 401/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 401/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 452 secs. Pages in use: 227
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 145/328 108/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4804153 m, 32519 m/sec, 4804153 t fired, .
[lola][.] 63 EF STEQ 406/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 406/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 457 secs. Pages in use: 233
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 150/328 112/2000 DoubleExponent-PT-100-CTLFireability-2024-09 4969765 m, 33122 m/sec, 4969765 t fired, .
[lola][.] 63 EF STEQ 411/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 411/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 462 secs. Pages in use: 238
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 155/328 115/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5136564 m, 33359 m/sec, 5136564 t fired, .
[lola][.] 63 EF STEQ 416/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 416/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 467 secs. Pages in use: 243
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 160/328 119/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5303351 m, 33357 m/sec, 5303351 t fired, .
[lola][.] 63 EF STEQ 421/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 421/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 472 secs. Pages in use: 249
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 165/328 122/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5470887 m, 33507 m/sec, 5470887 t fired, .
[lola][.] 63 EF STEQ 426/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 426/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 477 secs. Pages in use: 253
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 170/328 126/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5638637 m, 33550 m/sec, 5638637 t fired, .
[lola][.] 63 EF STEQ 431/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 431/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 482 secs. Pages in use: 259
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 175/328 130/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5806452 m, 33563 m/sec, 5806452 t fired, .
[lola][.] 63 EF STEQ 436/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 436/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 487 secs. Pages in use: 264
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 180/328 133/2000 DoubleExponent-PT-100-CTLFireability-2024-09 5974224 m, 33554 m/sec, 5974224 t fired, .
[lola][.] 63 EF STEQ 441/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 441/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 492 secs. Pages in use: 269
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 185/328 137/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6142330 m, 33621 m/sec, 6142330 t fired, .
[lola][.] 63 EF STEQ 446/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 446/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 497 secs. Pages in use: 274
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 190/328 141/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6310018 m, 33537 m/sec, 6310018 t fired, .
[lola][.] 63 EF STEQ 451/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 451/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 502 secs. Pages in use: 280
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 195/328 144/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6478254 m, 33647 m/sec, 6478254 t fired, .
[lola][.] 63 EF STEQ 456/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 456/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 507 secs. Pages in use: 284
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 200/328 148/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6645911 m, 33531 m/sec, 6645911 t fired, .
[lola][.] 63 EF STEQ 461/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 461/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 512 secs. Pages in use: 290
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 205/328 152/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6813791 m, 33576 m/sec, 6813791 t fired, .
[lola][.] 63 EF STEQ 466/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 466/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 517 secs. Pages in use: 296
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 210/328 155/2000 DoubleExponent-PT-100-CTLFireability-2024-09 6981631 m, 33568 m/sec, 6981631 t fired, .
[lola][.] 63 EF STEQ 471/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 471/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 522 secs. Pages in use: 300
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 215/328 159/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7149330 m, 33539 m/sec, 7149330 t fired, .
[lola][.] 63 EF STEQ 476/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 476/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 527 secs. Pages in use: 306
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 220/328 162/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7317004 m, 33534 m/sec, 7317004 t fired, .
[lola][.] 63 EF STEQ 481/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 481/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 532 secs. Pages in use: 310
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 225/328 166/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7483282 m, 33255 m/sec, 7483282 t fired, .
[lola][.] 63 EF STEQ 486/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 486/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 537 secs. Pages in use: 316
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 230/328 170/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7650761 m, 33495 m/sec, 7650760 t fired, .
[lola][.] 63 EF STEQ 491/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 491/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 542 secs. Pages in use: 321
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 235/328 173/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7818280 m, 33503 m/sec, 7818280 t fired, .
[lola][.] 63 EF STEQ 496/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 496/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 547 secs. Pages in use: 326
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 240/328 177/2000 DoubleExponent-PT-100-CTLFireability-2024-09 7986000 m, 33544 m/sec, 7986000 t fired, .
[lola][.] 63 EF STEQ 501/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 501/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 552 secs. Pages in use: 331
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 245/328 181/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8153870 m, 33574 m/sec, 8153870 t fired, .
[lola][.] 63 EF STEQ 506/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 506/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 557 secs. Pages in use: 337
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 250/328 184/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8321853 m, 33596 m/sec, 8321853 t fired, .
[lola][.] 63 EF STEQ 511/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 511/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 562 secs. Pages in use: 342
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 255/328 188/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8489767 m, 33582 m/sec, 8489767 t fired, .
[lola][.] 63 EF STEQ 516/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 516/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 567 secs. Pages in use: 347
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 260/328 191/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8657673 m, 33581 m/sec, 8657673 t fired, .
[lola][.] 63 EF STEQ 521/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 521/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 572 secs. Pages in use: 352
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 265/328 195/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8825522 m, 33569 m/sec, 8825522 t fired, .
[lola][.] 63 EF STEQ 526/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 526/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 577 secs. Pages in use: 357
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 270/328 199/2000 DoubleExponent-PT-100-CTLFireability-2024-09 8993295 m, 33554 m/sec, 8993294 t fired, .
[lola][.] 63 EF STEQ 531/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 531/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 582 secs. Pages in use: 363
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 275/328 202/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9160969 m, 33534 m/sec, 9160969 t fired, .
[lola][.] 63 EF STEQ 536/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 536/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 587 secs. Pages in use: 367
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 280/328 206/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9328708 m, 33547 m/sec, 9328708 t fired, .
[lola][.] 63 EF STEQ 541/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 541/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 592 secs. Pages in use: 373
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 285/328 210/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9496504 m, 33559 m/sec, 9496504 t fired, .
[lola][.] 63 EF STEQ 546/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 546/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 597 secs. Pages in use: 379
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 290/328 213/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9664258 m, 33550 m/sec, 9664258 t fired, .
[lola][.] 63 EF STEQ 551/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 551/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 602 secs. Pages in use: 383
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 295/328 217/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9832001 m, 33548 m/sec, 9832001 t fired, .
[lola][.] 63 EF STEQ 556/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 556/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 607 secs. Pages in use: 389
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 300/328 220/2000 DoubleExponent-PT-100-CTLFireability-2024-09 9999944 m, 33588 m/sec, 9999944 t fired, .
[lola][.] 63 EF STEQ 561/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 561/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 612 secs. Pages in use: 393
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 305/328 224/2000 DoubleExponent-PT-100-CTLFireability-2024-09 10167987 m, 33608 m/sec, 10167987 t fired, .
[lola][.] 63 EF STEQ 566/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 566/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 617 secs. Pages in use: 399
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 310/328 228/2000 DoubleExponent-PT-100-CTLFireability-2024-09 10335734 m, 33549 m/sec, 10335733 t fired, .
[lola][.] 63 EF STEQ 571/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 571/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 622 secs. Pages in use: 404
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 315/328 231/2000 DoubleExponent-PT-100-CTLFireability-2024-09 10503130 m, 33479 m/sec, 10503130 t fired, .
[lola][.] 63 EF STEQ 576/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 576/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 627 secs. Pages in use: 409
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 320/328 235/2000 DoubleExponent-PT-100-CTLFireability-2024-09 10670561 m, 33486 m/sec, 10670561 t fired, .
[lola][.] 63 EF STEQ 581/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 581/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 632 secs. Pages in use: 415
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 28 CTL EXCL 325/328 239/2000 DoubleExponent-PT-100-CTLFireability-2024-09 10837843 m, 33456 m/sec, 10837843 t fired, .
[lola][.] 63 EF STEQ 586/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 586/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 637 secs. Pages in use: 420
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][W] CANCELED task # 28 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-09 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 1 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 591/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 591/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 642 secs. Pages in use: 425
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 25 (type EXCL) for 24 DoubleExponent-PT-100-CTLFireability-2024-08
[lola][I] time limit : 328 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 28 (type EXCL) for 27 DoubleExponent-PT-100-CTLFireability-2024-09
[lola][I] time limit : 2958 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 5/328 2/2000 DoubleExponent-PT-100-CTLFireability-2024-08 71543 m, 14308 m/sec, 135519 t fired, .
[lola][.] 28 CTL EXCL 5/2958 3/5 DoubleExponent-PT-100-CTLFireability-2024-09 131401 m, -2141288 m/sec, 131401 t fired, .
[lola][.] 63 EF STEQ 596/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 596/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 647 secs. Pages in use: 431
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] CANCELED task # 28 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-09 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 10/328 4/2000 DoubleExponent-PT-100-CTLFireability-2024-08 149013 m, 15494 m/sec, 282236 t fired, .
[lola][.] 63 EF STEQ 601/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 601/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 652 secs. Pages in use: 435
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 15/328 6/2000 DoubleExponent-PT-100-CTLFireability-2024-08 237348 m, 17667 m/sec, 449493 t fired, .
[lola][.] 63 EF STEQ 606/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 606/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 657 secs. Pages in use: 435
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 20/328 8/2000 DoubleExponent-PT-100-CTLFireability-2024-08 324998 m, 17530 m/sec, 615506 t fired, .
[lola][.] 63 EF STEQ 611/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 611/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 662 secs. Pages in use: 438
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 25/328 10/2000 DoubleExponent-PT-100-CTLFireability-2024-08 412447 m, 17489 m/sec, 781088 t fired, .
[lola][.] 63 EF STEQ 616/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 616/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 667 secs. Pages in use: 442
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 30/328 12/2000 DoubleExponent-PT-100-CTLFireability-2024-08 499657 m, 17442 m/sec, 946237 t fired, .
[lola][.] 63 EF STEQ 621/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 621/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 672 secs. Pages in use: 445
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 35/328 14/2000 DoubleExponent-PT-100-CTLFireability-2024-08 587608 m, 17590 m/sec, 1112816 t fired, .
[lola][.] 63 EF STEQ 626/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 626/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 677 secs. Pages in use: 449
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 40/328 15/2000 DoubleExponent-PT-100-CTLFireability-2024-08 675422 m, 17562 m/sec, 1279090 t fired, .
[lola][.] 63 EF STEQ 631/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 631/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 682 secs. Pages in use: 452
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 45/328 17/2000 DoubleExponent-PT-100-CTLFireability-2024-08 763133 m, 17542 m/sec, 1445199 t fired, .
[lola][.] 63 EF STEQ 636/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 636/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 687 secs. Pages in use: 455
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 50/328 19/2000 DoubleExponent-PT-100-CTLFireability-2024-08 850464 m, 17466 m/sec, 1610572 t fired, .
[lola][.] 63 EF STEQ 641/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 641/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 692 secs. Pages in use: 459
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 55/328 21/2000 DoubleExponent-PT-100-CTLFireability-2024-08 937812 m, 17469 m/sec, 1775978 t fired, .
[lola][.] 63 EF STEQ 646/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 646/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 697 secs. Pages in use: 462
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 60/328 23/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1025257 m, 17489 m/sec, 1941589 t fired, .
[lola][.] 63 EF STEQ 651/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 651/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 702 secs. Pages in use: 466
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 65/328 25/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1112749 m, 17498 m/sec, 2107238 t fired, .
[lola][.] 63 EF STEQ 656/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 656/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 707 secs. Pages in use: 469
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 70/328 27/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1200084 m, 17467 m/sec, 2272647 t fired, .
[lola][.] 63 EF STEQ 661/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 661/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 712 secs. Pages in use: 473
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 75/328 29/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1287392 m, 17461 m/sec, 2437983 t fired, .
[lola][.] 63 EF STEQ 666/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 666/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 717 secs. Pages in use: 477
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 80/328 31/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1374383 m, 17398 m/sec, 2602721 t fired, .
[lola][.] 63 EF STEQ 671/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 671/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 722 secs. Pages in use: 480
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 85/328 33/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1461184 m, 17360 m/sec, 2767097 t fired, .
[lola][.] 63 EF STEQ 676/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 676/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 727 secs. Pages in use: 484
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 90/328 35/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1547851 m, 17333 m/sec, 2931192 t fired, .
[lola][.] 63 EF STEQ 681/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 681/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 732 secs. Pages in use: 487
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 95/328 37/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1634956 m, 17421 m/sec, 3096165 t fired, .
[lola][.] 63 EF STEQ 686/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 686/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 737 secs. Pages in use: 491
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 100/328 39/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1721758 m, 17360 m/sec, 3260521 t fired, .
[lola][.] 63 EF STEQ 691/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 691/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 742 secs. Pages in use: 494
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 105/328 41/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1808605 m, 17369 m/sec, 3424990 t fired, .
[lola][.] 63 EF STEQ 696/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 696/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 747 secs. Pages in use: 498
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 110/328 42/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1895257 m, 17330 m/sec, 3589098 t fired, .
[lola][.] 63 EF STEQ 701/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 701/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 752 secs. Pages in use: 500
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 115/328 44/2000 DoubleExponent-PT-100-CTLFireability-2024-08 1982015 m, 17351 m/sec, 3753373 t fired, .
[lola][.] 63 EF STEQ 706/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 706/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 757 secs. Pages in use: 504
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 120/328 46/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2069115 m, 17420 m/sec, 3918324 t fired, .
[lola][.] 63 EF STEQ 711/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 711/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 762 secs. Pages in use: 508
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 125/328 48/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2156781 m, 17533 m/sec, 4084307 t fired, .
[lola][.] 63 EF STEQ 716/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 716/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 767 secs. Pages in use: 511
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 130/328 50/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2244015 m, 17446 m/sec, 4249514 t fired, .
[lola][.] 63 EF STEQ 721/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 721/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 772 secs. Pages in use: 515
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 135/328 52/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2331837 m, 17564 m/sec, 4415795 t fired, .
[lola][.] 63 EF STEQ 726/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 726/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 777 secs. Pages in use: 518
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 140/328 54/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2419549 m, 17542 m/sec, 4582010 t fired, .
[lola][.] 63 EF STEQ 731/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 731/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 782 secs. Pages in use: 522
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 145/328 56/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2506953 m, 17480 m/sec, 4747595 t fired, .
[lola][.] 63 EF STEQ 736/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 736/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 787 secs. Pages in use: 525
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 150/328 59/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2594895 m, 17588 m/sec, 4914168 t fired, .
[lola][.] 63 EF STEQ 741/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 741/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 792 secs. Pages in use: 530
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 155/328 61/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2683151 m, 17651 m/sec, 5081326 t fired, .
[lola][.] 63 EF STEQ 746/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 746/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 797 secs. Pages in use: 534
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 160/328 63/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2770664 m, 17502 m/sec, 5247069 t fired, .
[lola][.] 63 EF STEQ 751/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 751/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 802 secs. Pages in use: 537
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 165/328 65/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2858266 m, 17520 m/sec, 5412989 t fired, .
[lola][.] 63 EF STEQ 756/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 756/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 807 secs. Pages in use: 541
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 170/328 67/2000 DoubleExponent-PT-100-CTLFireability-2024-08 2945624 m, 17471 m/sec, 5578429 t fired, .
[lola][.] 63 EF STEQ 761/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 761/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 812 secs. Pages in use: 544
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 175/328 69/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3033137 m, 17502 m/sec, 5744165 t fired, .
[lola][.] 63 EF STEQ 766/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 766/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 817 secs. Pages in use: 548
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 180/328 71/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3120471 m, 17466 m/sec, 5909567 t fired, .
[lola][.] 63 EF STEQ 771/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 771/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 822 secs. Pages in use: 551
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 185/328 73/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3207545 m, 17414 m/sec, 6074452 t fired, .
[lola][.] 63 EF STEQ 776/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 776/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 827 secs. Pages in use: 555
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 190/328 74/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3294998 m, 17490 m/sec, 6240057 t fired, .
[lola][.] 63 EF STEQ 781/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 781/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 832 secs. Pages in use: 557
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 195/328 76/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3380355 m, 17071 m/sec, 6401731 t fired, .
[lola][.] 63 EF STEQ 786/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 786/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 837 secs. Pages in use: 561
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 200/328 78/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3468236 m, 17576 m/sec, 6568151 t fired, .
[lola][.] 63 EF STEQ 791/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 791/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 842 secs. Pages in use: 565
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 205/328 80/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3555706 m, 17494 m/sec, 6733779 t fired, .
[lola][.] 63 EF STEQ 796/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 796/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 847 secs. Pages in use: 568
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 210/328 82/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3633037 m, 15466 m/sec, 6880212 t fired, .
[lola][.] 63 EF STEQ 801/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 801/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 852 secs. Pages in use: 572
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 215/328 84/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3718207 m, 17034 m/sec, 7041516 t fired, .
[lola][.] 63 EF STEQ 806/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 806/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 857 secs. Pages in use: 575
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 220/328 86/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3805043 m, 17367 m/sec, 7205965 t fired, .
[lola][.] 63 EF STEQ 811/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 811/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 862 secs. Pages in use: 579
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 225/328 88/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3893490 m, 17689 m/sec, 7373454 t fired, .
[lola][.] 63 EF STEQ 816/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 816/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 867 secs. Pages in use: 582
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 230/328 90/2000 DoubleExponent-PT-100-CTLFireability-2024-08 3981782 m, 17658 m/sec, 7540645 t fired, .
[lola][.] 63 EF STEQ 821/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 821/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 872 secs. Pages in use: 586
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 235/328 92/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4070068 m, 17657 m/sec, 7707811 t fired, .
[lola][.] 63 EF STEQ 826/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 826/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 877 secs. Pages in use: 589
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 240/328 94/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4158600 m, 17706 m/sec, 7875438 t fired, .
[lola][.] 63 EF STEQ 831/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 831/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 882 secs. Pages in use: 593
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 245/328 96/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4246881 m, 17656 m/sec, 8042651 t fired, .
[lola][.] 63 EF STEQ 836/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 836/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 887 secs. Pages in use: 596
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 250/328 98/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4335239 m, 17671 m/sec, 8209989 t fired, .
[lola][.] 63 EF STEQ 841/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 841/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 892 secs. Pages in use: 600
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 255/328 100/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4423551 m, 17662 m/sec, 8377200 t fired, .
[lola][.] 63 EF STEQ 846/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 846/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 897 secs. Pages in use: 603
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 260/328 101/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4511868 m, 17663 m/sec, 8544442 t fired, .
[lola][.] 63 EF STEQ 851/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 851/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 902 secs. Pages in use: 606
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 265/328 103/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4599999 m, 17626 m/sec, 8711314 t fired, .
[lola][.] 63 EF STEQ 856/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 856/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 907 secs. Pages in use: 609
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 270/328 105/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4688127 m, 17625 m/sec, 8878181 t fired, .
[lola][.] 63 EF STEQ 861/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 861/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 912 secs. Pages in use: 613
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 275/328 107/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4776387 m, 17652 m/sec, 9045297 t fired, .
[lola][.] 63 EF STEQ 866/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 866/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 917 secs. Pages in use: 617
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 280/328 109/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4864511 m, 17624 m/sec, 9212196 t fired, .
[lola][.] 63 EF STEQ 871/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 871/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 922 secs. Pages in use: 620
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 285/328 111/2000 DoubleExponent-PT-100-CTLFireability-2024-08 4952707 m, 17639 m/sec, 9379217 t fired, .
[lola][.] 63 EF STEQ 876/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 876/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 927 secs. Pages in use: 624
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 290/328 113/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5040602 m, 17579 m/sec, 9545653 t fired, .
[lola][.] 63 EF STEQ 881/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 881/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 932 secs. Pages in use: 627
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 295/328 115/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5128819 m, 17643 m/sec, 9712696 t fired, .
[lola][.] 63 EF STEQ 886/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 886/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 937 secs. Pages in use: 631
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 300/328 117/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5217032 m, 17642 m/sec, 9879725 t fired, .
[lola][.] 63 EF STEQ 891/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 891/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 942 secs. Pages in use: 634
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 305/328 119/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5305388 m, 17671 m/sec, 10047029 t fired, .
[lola][.] 63 EF STEQ 896/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 896/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 947 secs. Pages in use: 638
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 310/328 121/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5393681 m, 17658 m/sec, 10214205 t fired, .
[lola][.] 63 EF STEQ 901/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 901/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 952 secs. Pages in use: 641
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 315/328 123/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5481817 m, 17627 m/sec, 10381085 t fired, .
[lola][.] 63 EF STEQ 906/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 906/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 957 secs. Pages in use: 645
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 320/328 124/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5570170 m, 17670 m/sec, 10548382 t fired, .
[lola][.] 63 EF STEQ 911/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 911/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 962 secs. Pages in use: 647
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 25 CTL EXCL 325/328 127/2000 DoubleExponent-PT-100-CTLFireability-2024-08 5658429 m, 17651 m/sec, 10715543 t fired, .
[lola][.] 63 EF STEQ 916/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 916/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 967 secs. Pages in use: 652
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][W] CANCELED task # 25 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-08 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 1 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 921/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 921/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 972 secs. Pages in use: 655
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 19 (type EXCL) for 18 DoubleExponent-PT-100-CTLFireability-2024-06
[lola][I] time limit : 328 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 25 (type EXCL) for 24 DoubleExponent-PT-100-CTLFireability-2024-08
[lola][I] time limit : 2628 sec
[lola][I] memory limit: 5 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 5/328 2/2000 DoubleExponent-PT-100-CTLFireability-2024-06 71242 m, 14248 m/sec, 142484 t fired, .
[lola][.] 25 CTL EXCL 5/2628 2/5 DoubleExponent-PT-100-CTLFireability-2024-08 67466 m, -1118192 m/sec, 127809 t fired, .
[lola][.] 63 EF STEQ 926/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 926/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 977 secs. Pages in use: 660
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 10/328 4/2000 DoubleExponent-PT-100-CTLFireability-2024-06 138398 m, 13431 m/sec, 276796 t fired, .
[lola][.] 25 CTL EXCL 10/292 4/5 DoubleExponent-PT-100-CTLFireability-2024-08 141174 m, 14741 m/sec, 267358 t fired, .
[lola][.] 63 EF STEQ 931/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 931/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 982 secs. Pages in use: 665
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 15/328 5/2000 DoubleExponent-PT-100-CTLFireability-2024-06 210064 m, 14333 m/sec, 420128 t fired, .
[lola][.] 25 CTL EXCL 15/292 5/5 DoubleExponent-PT-100-CTLFireability-2024-08 212780 m, 14321 m/sec, 402987 t fired, .
[lola][.] 63 EF STEQ 936/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 936/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 987 secs. Pages in use: 668
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I] CANCELED task # 25 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-08 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 20/328 7/2000 DoubleExponent-PT-100-CTLFireability-2024-06 297109 m, 17409 m/sec, 594218 t fired, .
[lola][.] 63 EF STEQ 941/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 941/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 992 secs. Pages in use: 668
[lola][.] # running tasks: 4 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 25/328 9/2000 DoubleExponent-PT-100-CTLFireability-2024-06 386656 m, 17909 m/sec, 773311 t fired, .
[lola][.] 63 EF STEQ 946/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 946/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 997 secs. Pages in use: 670
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 30/328 11/2000 DoubleExponent-PT-100-CTLFireability-2024-06 476096 m, 17888 m/sec, 952192 t fired, .
[lola][.] 63 EF STEQ 951/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 951/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1002 secs. Pages in use: 674
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 35/328 13/2000 DoubleExponent-PT-100-CTLFireability-2024-06 565517 m, 17884 m/sec, 1131033 t fired, .
[lola][.] 63 EF STEQ 956/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 956/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1007 secs. Pages in use: 677
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 40/328 15/2000 DoubleExponent-PT-100-CTLFireability-2024-06 655117 m, 17920 m/sec, 1310233 t fired, .
[lola][.] 63 EF STEQ 961/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 961/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1012 secs. Pages in use: 681
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 45/328 17/2000 DoubleExponent-PT-100-CTLFireability-2024-06 744482 m, 17873 m/sec, 1488964 t fired, .
[lola][.] 63 EF STEQ 966/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 966/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1017 secs. Pages in use: 684
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 50/328 19/2000 DoubleExponent-PT-100-CTLFireability-2024-06 833831 m, 17869 m/sec, 1667662 t fired, .
[lola][.] 63 EF STEQ 971/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 971/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1022 secs. Pages in use: 688
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 55/328 21/2000 DoubleExponent-PT-100-CTLFireability-2024-06 922895 m, 17812 m/sec, 1845789 t fired, .
[lola][.] 63 EF STEQ 976/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 976/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1027 secs. Pages in use: 691
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 60/328 23/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1010651 m, 17551 m/sec, 2021301 t fired, .
[lola][.] 63 EF STEQ 981/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 981/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1032 secs. Pages in use: 695
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 65/328 25/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1098090 m, 17487 m/sec, 2196180 t fired, .
[lola][.] 63 EF STEQ 986/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 986/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1037 secs. Pages in use: 699
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 70/328 27/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1185761 m, 17534 m/sec, 2371521 t fired, .
[lola][.] 63 EF STEQ 991/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 991/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1042 secs. Pages in use: 702
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 75/328 29/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1273208 m, 17489 m/sec, 2546416 t fired, .
[lola][.] 63 EF STEQ 996/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 996/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1047 secs. Pages in use: 706
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 80/328 31/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1360678 m, 17494 m/sec, 2721355 t fired, .
[lola][.] 63 EF STEQ 1001/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1001/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1052 secs. Pages in use: 709
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 85/328 33/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1448330 m, 17530 m/sec, 2896659 t fired, .
[lola][.] 63 EF STEQ 1006/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1006/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1057 secs. Pages in use: 713
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 90/328 35/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1535732 m, 17480 m/sec, 3071463 t fired, .
[lola][.] 63 EF STEQ 1011/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1011/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1062 secs. Pages in use: 716
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 95/328 36/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1623549 m, 17563 m/sec, 3247098 t fired, .
[lola][.] 63 EF STEQ 1016/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1016/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1067 secs. Pages in use: 719
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 100/328 38/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1711407 m, 17571 m/sec, 3422813 t fired, .
[lola][.] 63 EF STEQ 1021/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1021/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1072 secs. Pages in use: 722
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 105/328 40/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1799142 m, 17547 m/sec, 3598284 t fired, .
[lola][.] 63 EF STEQ 1026/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1026/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1077 secs. Pages in use: 726
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 110/328 42/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1887198 m, 17611 m/sec, 3774395 t fired, .
[lola][.] 63 EF STEQ 1031/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1031/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1082 secs. Pages in use: 730
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 115/328 44/2000 DoubleExponent-PT-100-CTLFireability-2024-06 1975402 m, 17640 m/sec, 3950804 t fired, .
[lola][.] 63 EF STEQ 1036/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1036/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1087 secs. Pages in use: 733
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 120/328 46/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2063506 m, 17620 m/sec, 4127012 t fired, .
[lola][.] 63 EF STEQ 1041/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1041/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1092 secs. Pages in use: 737
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 125/328 48/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2151697 m, 17638 m/sec, 4303394 t fired, .
[lola][.] 63 EF STEQ 1046/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1046/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1097 secs. Pages in use: 740
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 130/328 50/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2239955 m, 17651 m/sec, 4479909 t fired, .
[lola][.] 63 EF STEQ 1051/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1051/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1102 secs. Pages in use: 744
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 135/328 52/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2328285 m, 17666 m/sec, 4656569 t fired, .
[lola][.] 63 EF STEQ 1056/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1056/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1107 secs. Pages in use: 747
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 140/328 54/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2416137 m, 17570 m/sec, 4832273 t fired, .
[lola][.] 63 EF STEQ 1061/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1061/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1112 secs. Pages in use: 751
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 145/328 56/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2504442 m, 17661 m/sec, 5008884 t fired, .
[lola][.] 63 EF STEQ 1066/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1066/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1117 secs. Pages in use: 755
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 150/328 58/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2592791 m, 17669 m/sec, 5185581 t fired, .
[lola][.] 63 EF STEQ 1071/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1071/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1122 secs. Pages in use: 758
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 155/328 61/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2680205 m, 17482 m/sec, 5360410 t fired, .
[lola][.] 63 EF STEQ 1076/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1076/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1127 secs. Pages in use: 763
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 160/328 63/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2767587 m, 17476 m/sec, 5535174 t fired, .
[lola][.] 63 EF STEQ 1081/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1081/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1132 secs. Pages in use: 766
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 165/328 65/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2855499 m, 17582 m/sec, 5710998 t fired, .
[lola][.] 63 EF STEQ 1086/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1086/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1137 secs. Pages in use: 770
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 170/328 67/2000 DoubleExponent-PT-100-CTLFireability-2024-06 2943645 m, 17629 m/sec, 5887289 t fired, .
[lola][.] 63 EF STEQ 1091/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1091/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1142 secs. Pages in use: 773
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 175/328 69/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3031895 m, 17650 m/sec, 6063789 t fired, .
[lola][.] 63 EF STEQ 1096/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1096/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1147 secs. Pages in use: 777
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 180/328 71/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3119480 m, 17517 m/sec, 6238960 t fired, .
[lola][.] 63 EF STEQ 1101/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1101/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1152 secs. Pages in use: 780
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 185/328 73/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3206741 m, 17452 m/sec, 6413481 t fired, .
[lola][.] 63 EF STEQ 1106/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1106/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1157 secs. Pages in use: 784
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 190/328 74/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3293934 m, 17438 m/sec, 6587868 t fired, .
[lola][.] 63 EF STEQ 1111/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1111/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1162 secs. Pages in use: 787
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 195/328 77/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3381361 m, 17485 m/sec, 6762721 t fired, .
[lola][.] 63 EF STEQ 1116/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1116/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1167 secs. Pages in use: 791
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 200/328 78/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3468953 m, 17518 m/sec, 6937906 t fired, .
[lola][.] 63 EF STEQ 1121/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1121/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1172 secs. Pages in use: 794
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 205/328 80/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3556363 m, 17482 m/sec, 7112725 t fired, .
[lola][.] 63 EF STEQ 1126/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1126/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1177 secs. Pages in use: 797
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 210/328 82/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3643524 m, 17432 m/sec, 7287048 t fired, .
[lola][.] 63 EF STEQ 1131/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1131/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1182 secs. Pages in use: 801
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 215/328 84/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3731085 m, 17512 m/sec, 7462169 t fired, .
[lola][.] 63 EF STEQ 1136/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1136/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1187 secs. Pages in use: 804
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 220/328 86/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3818734 m, 17529 m/sec, 7637467 t fired, .
[lola][.] 63 EF STEQ 1141/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1141/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1192 secs. Pages in use: 808
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 225/328 88/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3906804 m, 17614 m/sec, 7813607 t fired, .
[lola][.] 63 EF STEQ 1146/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1146/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1197 secs. Pages in use: 811
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 230/328 90/2000 DoubleExponent-PT-100-CTLFireability-2024-06 3994673 m, 17573 m/sec, 7989345 t fired, .
[lola][.] 63 EF STEQ 1151/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1151/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1202 secs. Pages in use: 815
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 235/328 92/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4082559 m, 17577 m/sec, 8165117 t fired, .
[lola][.] 63 EF STEQ 1156/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1156/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1207 secs. Pages in use: 819
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 240/328 94/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4169701 m, 17428 m/sec, 8339401 t fired, .
[lola][.] 63 EF STEQ 1161/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1161/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1212 secs. Pages in use: 822
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 245/328 96/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4257590 m, 17577 m/sec, 8515180 t fired, .
[lola][.] 63 EF STEQ 1166/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1166/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1217 secs. Pages in use: 826
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 250/328 98/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4344525 m, 17387 m/sec, 8689050 t fired, .
[lola][.] 63 EF STEQ 1171/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1171/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1222 secs. Pages in use: 829
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 255/328 100/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4431584 m, 17411 m/sec, 8863167 t fired, .
[lola][.] 63 EF STEQ 1176/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1176/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1227 secs. Pages in use: 833
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 260/328 102/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4518947 m, 17472 m/sec, 9037893 t fired, .
[lola][.] 63 EF STEQ 1181/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1181/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1232 secs. Pages in use: 836
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 265/328 104/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4606052 m, 17421 m/sec, 9212104 t fired, .
[lola][.] 63 EF STEQ 1186/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1186/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1237 secs. Pages in use: 840
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 270/328 105/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4693736 m, 17536 m/sec, 9387472 t fired, .
[lola][.] 63 EF STEQ 1191/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1191/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1242 secs. Pages in use: 842
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 275/328 107/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4781527 m, 17558 m/sec, 9563053 t fired, .
[lola][.] 63 EF STEQ 1196/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1196/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1247 secs. Pages in use: 846
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 280/328 109/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4869249 m, 17544 m/sec, 9738497 t fired, .
[lola][.] 63 EF STEQ 1201/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1201/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1252 secs. Pages in use: 850
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 285/328 111/2000 DoubleExponent-PT-100-CTLFireability-2024-06 4956969 m, 17544 m/sec, 9913937 t fired, .
[lola][.] 63 EF STEQ 1206/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1206/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1257 secs. Pages in use: 853
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 290/328 113/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5044512 m, 17508 m/sec, 10089024 t fired, .
[lola][.] 63 EF STEQ 1211/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1211/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1262 secs. Pages in use: 857
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 295/328 115/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5131966 m, 17490 m/sec, 10263931 t fired, .
[lola][.] 63 EF STEQ 1216/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1216/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1267 secs. Pages in use: 860
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 300/328 117/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5219382 m, 17483 m/sec, 10438763 t fired, .
[lola][.] 63 EF STEQ 1221/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1221/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1272 secs. Pages in use: 864
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 305/328 119/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5306848 m, 17493 m/sec, 10613696 t fired, .
[lola][.] 63 EF STEQ 1226/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1226/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1277 secs. Pages in use: 867
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 310/328 121/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5393956 m, 17421 m/sec, 10787912 t fired, .
[lola][.] 63 EF STEQ 1231/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1231/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1282 secs. Pages in use: 871
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 315/328 123/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5481103 m, 17429 m/sec, 10962206 t fired, .
[lola][.] 63 EF STEQ 1236/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1236/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1287 secs. Pages in use: 874
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 320/328 124/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5568721 m, 17523 m/sec, 11137442 t fired, .
[lola][.] 63 EF STEQ 1241/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1241/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1292 secs. Pages in use: 877
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 325/328 126/2000 DoubleExponent-PT-100-CTLFireability-2024-06 5655996 m, 17455 m/sec, 11311992 t fired, .
[lola][.] 63 EF STEQ 1246/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1246/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1297 secs. Pages in use: 881
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][W] CANCELED task # 19 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-06 (local timeout)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 1 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 1251/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1251/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1302 secs. Pages in use: 884
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 16 (type EXCL) for 15 DoubleExponent-PT-100-CTLFireability-2024-05
[lola][I] time limit : 328 sec
[lola][I] memory limit: 2000 pages
[lola][I] LAUNCH task # 19 (type EXCL) for 18 DoubleExponent-PT-100-CTLFireability-2024-06
[lola][I] time limit : 2298 sec
[lola][I] memory limit: 5 pages
[lola][I] FINISHED task # 16 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-05
[lola][I] result : false
[lola][I] markings : 28
[lola][I] fired transitions : 50
[lola][I] time used : 0
[lola][I] memory pages used : 1
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 5/328 2/5 DoubleExponent-PT-100-CTLFireability-2024-06 83567 m, -1114485 m/sec, 167134 t fired, .
[lola][.] 63 EF STEQ 1256/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1256/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1307 secs. Pages in use: 888
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 19 CTL EXCL 10/328 4/5 DoubleExponent-PT-100-CTLFireability-2024-06 170754 m, 17437 m/sec, 341507 t fired, .
[lola][.] 63 EF STEQ 1261/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1261/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1312 secs. Pages in use: 891
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] CANCELED task # 19 (type EXCL) for DoubleExponent-PT-100-CTLFireability-2024-06 (memory limit exceeded)
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 63 EF STEQ 1266/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1266/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1317 secs. Pages in use: 893
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I] LAUNCH task # 13 (type EXCL) for 12 DoubleExponent-PT-100-CTLFireability-2024-04
[lola][I] time limit : 380 sec
[lola][I] memory limit: 2000 pages
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 5/380 2/2000 DoubleExponent-PT-100-CTLFireability-2024-04 45171 m, 9034 m/sec, 175899 t fired, .
[lola][.] 63 EF STEQ 1271/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1271/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1322 secs. Pages in use: 893
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 10/380 3/2000 DoubleExponent-PT-100-CTLFireability-2024-04 90259 m, 9017 m/sec, 351457 t fired, .
[lola][.] 63 EF STEQ 1276/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1276/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1327 secs. Pages in use: 895
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 15/380 3/2000 DoubleExponent-PT-100-CTLFireability-2024-04 135234 m, 8995 m/sec, 526573 t fired, .
[lola][.] 63 EF STEQ 1281/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1281/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1332 secs. Pages in use: 896
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 20/380 5/2000 DoubleExponent-PT-100-CTLFireability-2024-04 180218 m, 8996 m/sec, 701756 t fired, .
[lola][.] 63 EF STEQ 1286/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1286/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1337 secs. Pages in use: 900
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 25/380 5/2000 DoubleExponent-PT-100-CTLFireability-2024-04 224324 m, 8821 m/sec, 873439 t fired, .
[lola][.] 63 EF STEQ 1291/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1291/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1342 secs. Pages in use: 901
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 30/380 6/2000 DoubleExponent-PT-100-CTLFireability-2024-04 268779 m, 8891 m/sec, 1046545 t fired, .
[lola][.] 63 EF STEQ 1296/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1296/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1347 secs. Pages in use: 904
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 35/380 7/2000 DoubleExponent-PT-100-CTLFireability-2024-04 312379 m, 8720 m/sec, 1216331 t fired, .
[lola][.] 63 EF STEQ 1301/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1301/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1352 secs. Pages in use: 907
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 40/380 8/2000 DoubleExponent-PT-100-CTLFireability-2024-04 356754 m, 8875 m/sec, 1389131 t fired, .
[lola][.] 63 EF STEQ 1306/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1306/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1357 secs. Pages in use: 909
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 45/380 9/2000 DoubleExponent-PT-100-CTLFireability-2024-04 401482 m, 8945 m/sec, 1563271 t fired, .
[lola][.] 63 EF STEQ 1311/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1311/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1362 secs. Pages in use: 912
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 50/380 10/2000 DoubleExponent-PT-100-CTLFireability-2024-04 446130 m, 8929 m/sec, 1737114 t fired, .
[lola][.] 63 EF STEQ 1316/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1316/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1367 secs. Pages in use: 914
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 55/380 11/2000 DoubleExponent-PT-100-CTLFireability-2024-04 490876 m, 8949 m/sec, 1911316 t fired, .
[lola][.] 63 EF STEQ 1321/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1321/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1372 secs. Pages in use: 917
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 60/380 12/2000 DoubleExponent-PT-100-CTLFireability-2024-04 535470 m, 8918 m/sec, 2084986 t fired, .
[lola][.] 63 EF STEQ 1326/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1326/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1377 secs. Pages in use: 919
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 65/380 13/2000 DoubleExponent-PT-100-CTLFireability-2024-04 580181 m, 8942 m/sec, 2259064 t fired, .
[lola][.] 63 EF STEQ 1331/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1331/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1382 secs. Pages in use: 922
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 70/380 14/2000 DoubleExponent-PT-100-CTLFireability-2024-04 624904 m, 8944 m/sec, 2433226 t fired, .
[lola][.] 63 EF STEQ 1336/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1336/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1387 secs. Pages in use: 924
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 75/380 15/2000 DoubleExponent-PT-100-CTLFireability-2024-04 669613 m, 8941 m/sec, 2607295 t fired, .
[lola][.] 63 EF STEQ 1341/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1341/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1392 secs. Pages in use: 927
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 80/380 16/2000 DoubleExponent-PT-100-CTLFireability-2024-04 714082 m, 8893 m/sec, 2780454 t fired, .
[lola][.] 63 EF STEQ 1346/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1346/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1397 secs. Pages in use: 929
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 85/380 17/2000 DoubleExponent-PT-100-CTLFireability-2024-04 758531 m, 8889 m/sec, 2953463 t fired, .
[lola][.] 63 EF STEQ 1351/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1351/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1402 secs. Pages in use: 932
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 90/380 18/2000 DoubleExponent-PT-100-CTLFireability-2024-04 803136 m, 8921 m/sec, 3127143 t fired, .
[lola][.] 63 EF STEQ 1356/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1356/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1407 secs. Pages in use: 934
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 95/380 19/2000 DoubleExponent-PT-100-CTLFireability-2024-04 847552 m, 8883 m/sec, 3300122 t fired, .
[lola][.] 63 EF STEQ 1361/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1361/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1412 secs. Pages in use: 937
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 100/380 20/2000 DoubleExponent-PT-100-CTLFireability-2024-04 891977 m, 8885 m/sec, 3473148 t fired, .
[lola][.] 63 EF STEQ 1366/3549 0/5 DoubleExponent-PT-100-CTLFireability-2023-13 sara not yet started (preprocessing).
[lola][.] 71 EF STEQ 1366/3549 0/5 DoubleExponent-PT-100-CTLFireability-2024-00 sara not yet started (preprocessing).
[lola][.]
[lola][.] Time elapsed: 1417 secs. Pages in use: 939
[lola][.] # running tasks: 3 of 4. Visible: 16
[lola][I]  FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-03: AGAF false state space /EFEG
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-05: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-10: CTL true CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-12: CONJ false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-14: CTL false CTL model checker
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-15: CTL false CTL model checker
[lola][.]
[lola][.]  PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-00: EFEG 0 0 1 0 2 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-01: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-02: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-04: CTL 0 0 1 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-06: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-07: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-08: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-09: CTL 0 0 0 0 1 0 1 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2024-11: CTL 0 1 0 0 1 0 0 0
[lola][.] DoubleExponent-PT-100-CTLFireability-2023-13: AGAF 0 1 1 0 2 0 0 0
[lola][.]
[lola][.]  TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
[lola][.] 13 CTL EXCL 105/380 21/2000 DoubleExponent-PT-100-CTLFireability-2024-04 935500 m, 8704 m/sec, 3642584 t fired, .

========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DoubleExponent-PT-100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5568"
echo " Executing tool lola"
echo " Input is DoubleExponent-PT-100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-171631134500570"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DoubleExponent-PT-100.tgz
mv DoubleExponent-PT-100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;